[dv] update dv template to also include derived clocks
Signed-off-by: Timothy Chen <timothytim@google.com>
[dv, sw] DV fixes for clock division
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/tb__xbar_connect.sv.tpl b/hw/top_earlgrey/data/tb__xbar_connect.sv.tpl
index 896b14b..abdd408 100644
--- a/hw/top_earlgrey/data/tb__xbar_connect.sv.tpl
+++ b/hw/top_earlgrey/data/tb__xbar_connect.sv.tpl
@@ -16,7 +16,7 @@
clk_src[clk] = src
clk_freq = OrderedDict()
-for clock in top["clocks"]["srcs"]:
+for clock in top["clocks"]["srcs"] + top["clocks"]["derived_srcs"]:
if clock["name"] in clk_src.values():
clk_freq[clock["name"]] = clock["freq"]
diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
index 9645d10..e51ee6e 100644
--- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv
+++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
@@ -7,7 +7,7 @@
// Testbench settings
bit stub_cpu;
bit en_uart_logger;
- int uart_baud_rate = uart_agent_pkg::BaudRate2Mbps;
+ int uart_baud_rate = uart_agent_pkg::BaudRate1Mbps;
bit use_gpio_for_sw_test_status;
bit initialize_ram;
diff --git a/sw/device/lib/arch/device_sim_dv.c b/sw/device/lib/arch/device_sim_dv.c
index 5b8c147..8bcac67 100644
--- a/sw/device/lib/arch/device_sim_dv.c
+++ b/sw/device/lib/arch/device_sim_dv.c
@@ -13,13 +13,13 @@
// TODO: DV testbench completely randomizes these. Need to add code to
// retrieve these from a preloaded memory location set by the testbench.
-const uint64_t kClockFreqCpuHz = 50 * 1000 * 1000; // 50MHz
+const uint64_t kClockFreqCpuHz = 100 * 1000 * 1000; // 100MHz
-const uint64_t kClockFreqPeripheralHz = 50 * 1000 * 1000; // 50MHz
+const uint64_t kClockFreqPeripheralHz = 24 * 1000 * 1000; // 24MHz
const uint64_t kClockFreqUsbHz = 48 * 1000 * 1000; // 48MHz
-const uint64_t kUartBaudrate = 2 * (1 << 20); // 2Mib/s
+const uint64_t kUartBaudrate = 1 << 20; // 1Mbps
// No Device Stop Address in our DV simulator.
const uintptr_t kDeviceStopAddress = 0;
