| commit | dc169daafd8f2ad80d29b1658f15c91b1aec0144 | [log] [tgz] |
|---|---|---|
| author | Greg Chadwick <gac@lowrisc.org> | Mon Apr 04 16:08:02 2022 +0100 |
| committer | Greg Chadwick <mail@gregchadwick.co.uk> | Mon Apr 04 19:47:16 2022 +0100 |
| tree | 67ca9c6560cb5326d394f5ccd9c7e9774be52560 | |
| parent | 6a0a34bb165c6b005a5f8d179e566cec34ff024a [diff] |
[prim,rtl] Fix RW collision bug in prim_1p_ram_scr When a read collides with buffered write data only the bits that have been written by a partial write should be forwarded. Otherwise the read data should come directly from the memory as normal. Previously prim_ram_1p_scr would forward bits from the buffered write data if they had been written and otherwise just produce 0 for read bits that weren't part of a buffered partial write. Signed-off-by: Greg Chadwick <gac@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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