[dv/chip] remove shadow_reg error test
This PR removes the shadow_reg error test in chip-level because:
1. Shadow reg errors: update errors and storage errors are fully
verified in block level testbenchs.
2. The alert connections will be covered by top-level alert test.
3. Maintain this extra alert test and backdoor probe errors requires
additional effort, which I do not think is worth it.
Signed-off-by: Cindy Chen <chencindy@google.com>
diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson
index 3adaa8d..e3c22af 100644
--- a/hw/top_earlgrey/data/chip_testplan.hjson
+++ b/hw/top_earlgrey/data/chip_testplan.hjson
@@ -10,7 +10,6 @@
// TODO: remove the common testplans if not applicable
import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
"hw/dv/tools/dvsim/testplans/enable_reg_testplan.hjson",
- "hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
"hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
"hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index ff13127..b3428b4 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -274,12 +274,6 @@
"+initialize_ram=1",
"+sw_test_timeout_ns=50000000"]
}
- {
- name: chip_shadow_reg_errors
- uvm_test_seq: chip_shadow_reg_errors_vseq
- en_run_modes: ["stub_cpu_mode"]
- run_opts: ["+en_scb=0"]
- }
// The test below is added in the included tl_access_tests.hjson.
// We just need to append the stub_cpu_mode run mode to it.
{
diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core
index 5eefdd5..61e5eb3 100644
--- a/hw/top_earlgrey/dv/env/chip_env.core
+++ b/hw/top_earlgrey/dv/env/chip_env.core
@@ -31,7 +31,6 @@
- seq_lib/chip_base_vseq.sv: {is_include_file: true}
- seq_lib/chip_stub_cpu_base_vseq.sv: {is_include_file: true}
- seq_lib/chip_common_vseq.sv: {is_include_file: true}
- - seq_lib/chip_shadow_reg_errors_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_base_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_uart_tx_rx_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_gpio_smoke_vseq.sv: {is_include_file: true}
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_shadow_reg_errors_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_shadow_reg_errors_vseq.sv
deleted file mode 100644
index be470d3..0000000
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_shadow_reg_errors_vseq.sv
+++ /dev/null
@@ -1,66 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-// This sequence tests shadow_registers' update error and storage error
-// The sequence will loop thorugh all shadow_regs from each IP
-// It will create update error by first write value 'h5555_5555 to shadow_reg, then write value
-// 'haaaa_aaaa as second write, and check the corresponding alert handshake
-// It will create storage error by randomly backdoor write to shadow register's committed_val or
-// shadow_val, and check the corresponding alert handshake
-class chip_shadow_reg_errors_vseq extends chip_common_vseq;
- `uvm_object_utils(chip_shadow_reg_errors_vseq)
- `uvm_object_new
-
- // Most of the shadow_reg related tasks are from `dv/sv/cip_lib/cip_base_vseq.sv`
- virtual task body();
- dv_base_reg shadowed_csrs[$];
-
- // Get all shadowed_regs from each IP
- ral.get_shadowed_regs(shadowed_csrs);
- shadowed_csrs.shuffle();
-
- foreach (shadowed_csrs[i]) begin
- bit alert_triggered;
- string alert_name;
- bit [TL_DW-1:0] origin_val, poke_val;
- bkdr_reg_path_e kind;
-
- // Create update error
- wr_shadowed_reg_update_err(shadowed_csrs[i], alert_triggered);
-
- // Check update error alerts
- alert_name = shadowed_csrs[i].get_update_err_alert_name();
- `DV_SPINWAIT(while (!alert_triggered && !cfg.m_alert_agent_cfg[alert_name].vif.get_alert())
- cfg.clk_rst_vif.wait_clks(1);,
- $sformatf("%0s update_err alert not detected", shadowed_csrs[i].get_name()));
- `DV_SPINWAIT(cfg.m_alert_agent_cfg[alert_name].vif.wait_ack_complete();,
- $sformatf("timeout for alert:%0s", alert_name))
-
- // Create storage error, randomly choose to poke committed or shadow value
- `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(kind, kind inside
- {BkdrRegPathRtlCommitted, BkdrRegPathRtlShadow};)
- csr_peek(.ptr(shadowed_csrs[i]), .value(origin_val), .kind(kind));
- poke_val = gen_storage_err_val(shadowed_csrs[i], origin_val, 0);
- csr_poke(.ptr(shadowed_csrs[i]), .value(poke_val), .kind(kind), .predict(1));
-
- // Check storage error alerts
- alert_name = shadowed_csrs[i].get_storage_err_alert_name();
- `DV_SPINWAIT(while (!cfg.m_alert_agent_cfg[alert_name].vif.get_alert())
- cfg.clk_rst_vif.wait_clks(1);,
- $sformatf("%0s storage_err alert not detected", shadowed_csrs[i].get_name()));
- csr_poke(.ptr(shadowed_csrs[i]), .value(origin_val), .kind(kind), .predict(1));
- `DV_SPINWAIT(cfg.m_alert_agent_cfg[alert_name].vif.wait_ack_complete();,
- $sformatf("timeout for alert:%0s", alert_name))
- end
- endtask : body
-
- // Generally we should get update error if first write of the register is 'h5555_5555,
- // and the second write is 'haaaa_aaaa
- // If any shadow reg does not follow this, can add additional requirements to this task
- virtual task wr_shadowed_reg_update_err(dv_base_reg csr, output bit alert_triggered);
- csr_wr(.ptr(csr), .value('h5555_5555), .en_shadow_wr(0), .predict(1));
- shadow_reg_wr(.csr(csr), .wdata('haaaa_aaaa), .alert_triggered(alert_triggered));
- endtask : wr_shadowed_reg_update_err
-
-endclass
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv
index 9f30fb8..eedac76 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv
@@ -5,7 +5,6 @@
`include "chip_base_vseq.sv"
`include "chip_stub_cpu_base_vseq.sv"
`include "chip_common_vseq.sv"
-`include "chip_shadow_reg_errors_vseq.sv"
`include "chip_sw_base_vseq.sv"
`include "chip_sw_uart_tx_rx_vseq.sv"
`include "chip_sw_gpio_smoke_vseq.sv"
