commit da341bfe385c6aca906ead47ba7110bd9a8273f6
author Rupert Swarbrick <rswarbrick@lowrisc.org> Wed Mar 10 15:45:25 2021 +0000
committer Rupert Swarbrick <rswarbrick@gmail.com> Wed Mar 10 18:15:55 2021 +0000
tree 1bf4edf185999e6b28180cdd5d1d3dfc84fdcc06
parent 857acb2cbc3e9924213db76e724460df7dc96af9

[ibex] Just take the bottom 32 bits of dm::FooAddress

The pulp_riscv_dbg module is presumably designed to support 64-bit
systems, so its addresses are 64 bits wide. Slice out the bottom 32
bits explicitly, avoiding width mismatch warnings for the addition and
then for setting a 32-bit parameter with the 64-bit result.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 38e1357..31530a6 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -259,8 +259,8 @@
     .BranchPredictor          (0),
     .DbgTriggerEn             (1),
     .SecureIbex               (0),
-    .DmHaltAddr               (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
-    .DmExceptionAddr          (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
+    .DmHaltAddr               (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress[31:0]),
+    .DmExceptionAddr          (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress[31:0]),
     .PipeLine                 (IbexPipeLine)
   ) u_rv_core_ibex (
     // clock and reset

hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index cdd2a4b..93e1f7a 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -656,8 +656,8 @@
     .BranchPredictor          (0),
     .DbgTriggerEn             (1),
     .SecureIbex               (0),
-    .DmHaltAddr               (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
-    .DmExceptionAddr          (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
+    .DmHaltAddr               (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress[31:0]),
+    .DmExceptionAddr          (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress[31:0]),
     .PipeLine                 (IbexPipeLine)
   ) u_rv_core_ibex (
     // clock and reset