[otp rtl] Update OTP ctrl field names to fix #4051
This change updates `read` and `write` fields of OTP CSR
`direct_access_cmd` to `rd` and `wr` respectively to fix #4051.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson b/hw/ip/otp_ctrl/data/otp_ctrl.hjson
index 212d113..42b93f9 100644
--- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson
+++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson
@@ -803,7 +803,7 @@
"excl:CsrNonInitTests:CsrExclWrite"],
fields: [
{ bits: "0",
- name: "READ",
+ name: "RD",
desc: '''
Initiates a readout sequence that reads the location specified
by !!DIRECT_ACCESS_ADDRESS. The command places the data read into
@@ -811,7 +811,7 @@
'''
}
{ bits: "1",
- name: "WRITE",
+ name: "WR",
desc: '''
Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0
and !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by
diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl
index ce625bd..c0bb473 100644
--- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl
+++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl
@@ -492,7 +492,7 @@
"excl:CsrNonInitTests:CsrExclWrite"],
fields: [
{ bits: "0",
- name: "READ",
+ name: "RD",
desc: '''
Initiates a readout sequence that reads the location specified
by !!DIRECT_ACCESS_ADDRESS. The command places the data read into
@@ -500,7 +500,7 @@
'''
}
{ bits: "1",
- name: "WRITE",
+ name: "WR",
desc: '''
Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0
and !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
index 7ffda82..51dcd64 100644
--- a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
+++ b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
@@ -237,12 +237,12 @@
// Any write to this register triggers a DAI command.
assign dai_req = reg2hw.direct_access_cmd.digest.qe |
- reg2hw.direct_access_cmd.write.qe |
- reg2hw.direct_access_cmd.read.qe;
+ reg2hw.direct_access_cmd.wr.qe |
+ reg2hw.direct_access_cmd.rd.qe;
assign dai_cmd = dai_cmd_e'({reg2hw.direct_access_cmd.digest.q,
- reg2hw.direct_access_cmd.write.q,
- reg2hw.direct_access_cmd.read.q});
+ reg2hw.direct_access_cmd.wr.q,
+ reg2hw.direct_access_cmd.rd.q});
assign dai_addr = reg2hw.direct_access_address.q;
assign dai_wdata = reg2hw.direct_access_wdata;
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv
index 75e6444..608a16e 100644
--- a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv
+++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv
@@ -116,11 +116,11 @@
struct packed {
logic q;
logic qe;
- } read;
+ } rd;
struct packed {
logic q;
logic qe;
- } write;
+ } wr;
struct packed {
logic q;
logic qe;
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
index e07f2c4..ce4d6f4 100644
--- a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
+++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
@@ -191,10 +191,10 @@
logic err_code_err_code_8_re;
logic direct_access_regwen_qs;
logic direct_access_regwen_re;
- logic direct_access_cmd_read_wd;
- logic direct_access_cmd_read_we;
- logic direct_access_cmd_write_wd;
- logic direct_access_cmd_write_we;
+ logic direct_access_cmd_rd_wd;
+ logic direct_access_cmd_rd_we;
+ logic direct_access_cmd_wr_wd;
+ logic direct_access_cmd_wr_we;
logic direct_access_cmd_digest_wd;
logic direct_access_cmd_digest_we;
logic [10:0] direct_access_address_qs;
@@ -818,34 +818,34 @@
// R[direct_access_cmd]: V(True)
- // F[read]: 0:0
+ // F[rd]: 0:0
prim_subreg_ext #(
.DW (1)
- ) u_direct_access_cmd_read (
+ ) u_direct_access_cmd_rd (
.re (1'b0),
// qualified with register enable
- .we (direct_access_cmd_read_we & direct_access_regwen_qs),
- .wd (direct_access_cmd_read_wd),
+ .we (direct_access_cmd_rd_we & direct_access_regwen_qs),
+ .wd (direct_access_cmd_rd_wd),
.d ('0),
.qre (),
- .qe (reg2hw.direct_access_cmd.read.qe),
- .q (reg2hw.direct_access_cmd.read.q ),
+ .qe (reg2hw.direct_access_cmd.rd.qe),
+ .q (reg2hw.direct_access_cmd.rd.q ),
.qs ()
);
- // F[write]: 1:1
+ // F[wr]: 1:1
prim_subreg_ext #(
.DW (1)
- ) u_direct_access_cmd_write (
+ ) u_direct_access_cmd_wr (
.re (1'b0),
// qualified with register enable
- .we (direct_access_cmd_write_we & direct_access_regwen_qs),
- .wd (direct_access_cmd_write_wd),
+ .we (direct_access_cmd_wr_we & direct_access_regwen_qs),
+ .wd (direct_access_cmd_wr_wd),
.d ('0),
.qre (),
- .qe (reg2hw.direct_access_cmd.write.qe),
- .q (reg2hw.direct_access_cmd.write.q ),
+ .qe (reg2hw.direct_access_cmd.wr.qe),
+ .q (reg2hw.direct_access_cmd.wr.q ),
.qs ()
);
@@ -1564,11 +1564,11 @@
assign direct_access_regwen_re = addr_hit[6] && reg_re;
- assign direct_access_cmd_read_we = addr_hit[7] & reg_we & ~wr_err;
- assign direct_access_cmd_read_wd = reg_wdata[0];
+ assign direct_access_cmd_rd_we = addr_hit[7] & reg_we & ~wr_err;
+ assign direct_access_cmd_rd_wd = reg_wdata[0];
- assign direct_access_cmd_write_we = addr_hit[7] & reg_we & ~wr_err;
- assign direct_access_cmd_write_wd = reg_wdata[1];
+ assign direct_access_cmd_wr_we = addr_hit[7] & reg_we & ~wr_err;
+ assign direct_access_cmd_wr_wd = reg_wdata[1];
assign direct_access_cmd_digest_we = addr_hit[7] & reg_we & ~wr_err;
assign direct_access_cmd_digest_wd = reg_wdata[2];
diff --git a/sw/device/lib/dif/dif_otp_ctrl.c b/sw/device/lib/dif/dif_otp_ctrl.c
index 5de15e0..44e31cb 100644
--- a/sw/device/lib/dif/dif_otp_ctrl.c
+++ b/sw/device/lib/dif/dif_otp_ctrl.c
@@ -558,7 +558,7 @@
OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, address);
uint32_t cmd =
- bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_READ_BIT, true);
+ bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT, true);
mmio_region_write32(otp->params.base_addr,
OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, cmd);
@@ -647,7 +647,7 @@
OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, value);
uint32_t cmd =
- bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_WRITE_BIT, true);
+ bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true);
mmio_region_write32(otp->params.base_addr,
OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, cmd);
@@ -696,7 +696,7 @@
OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, value >> 32);
uint32_t cmd =
- bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_WRITE_BIT, true);
+ bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true);
mmio_region_write32(otp->params.base_addr,
OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, cmd);
@@ -746,7 +746,7 @@
}
bitfield_bit32_index_t cmd_bit = is_sw
- ? OTP_CTRL_DIRECT_ACCESS_CMD_WRITE_BIT
+ ? OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT
: OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_BIT;
uint32_t cmd = bitfield_bit32_write(0, cmd_bit, true);
mmio_region_write32(otp->params.base_addr,
diff --git a/sw/device/tests/dif/dif_otp_ctrl_unittest.cc b/sw/device/tests/dif/dif_otp_ctrl_unittest.cc
index 244c02c..4219104 100644
--- a/sw/device/tests/dif/dif_otp_ctrl_unittest.cc
+++ b/sw/device/tests/dif/dif_otp_ctrl_unittest.cc
@@ -382,7 +382,7 @@
{{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}});
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, 0x620);
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET,
- {{OTP_CTRL_DIRECT_ACCESS_CMD_READ_BIT, true}});
+ {{OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT, true}});
EXPECT_EQ(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionHwCfg,
/*address=*/0x20),
@@ -404,7 +404,7 @@
{{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}});
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, 0x738);
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET,
- {{OTP_CTRL_DIRECT_ACCESS_CMD_READ_BIT, true}});
+ {{OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT, true}});
EXPECT_EQ(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionSecret2,
/*address=*/0x8),
@@ -480,7 +480,7 @@
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, 0x620);
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, 0x12345678);
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET,
- {{OTP_CTRL_DIRECT_ACCESS_CMD_WRITE_BIT, true}});
+ {{OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true}});
EXPECT_EQ(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionHwCfg,
/*address=*/0x20, /*value=*/0x12345678),
@@ -495,7 +495,7 @@
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, 0x90abcdef);
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, 0x12345678);
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET,
- {{OTP_CTRL_DIRECT_ACCESS_CMD_WRITE_BIT, true}});
+ {{OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true}});
EXPECT_EQ(
dif_otp_ctrl_dai_program64(&otp_, kDifOtpCtrlPartitionSecret2,
@@ -573,7 +573,7 @@
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, 0x00abcdef);
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, 0xabcdef00);
EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET,
- {{OTP_CTRL_DIRECT_ACCESS_CMD_WRITE_BIT, true}});
+ {{OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true}});
EXPECT_EQ(dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartitionCreatorSwCfg,
/*digest=*/0xabcdef0000abcdef),
