[hmac] Add MSG_FIFO Emtpy signal
This commit is a follow-up of Issue #1276.
Software doesn't need FIFO_FULL interrupt but the status register is
sufficient. So, fifo full interrupt is removed and fifo_empty interrupt
is added.
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/ip/hmac/data/hmac.hjson b/hw/ip/hmac/data/hmac.hjson
index b92fba4..de0c168 100644
--- a/hw/ip/hmac/data/hmac.hjson
+++ b/hw/ip/hmac/data/hmac.hjson
@@ -9,8 +9,8 @@
{ name: "hmac_done",
desc: "HMAC-256 completes a message with key"
}
- { name: "fifo_full",
- desc: "Message FIFO full condition"
+ { name: "fifo_empty",
+ desc: "Message FIFO empty condition"
}
{ name: "hmac_err",
desc: "HMAC error occurred. ERR_CODE register shows which error occurred"
diff --git a/hw/ip/hmac/rtl/hmac.sv b/hw/ip/hmac/rtl/hmac.sv
index 217e700..8ded78c 100644
--- a/hw/ip/hmac/rtl/hmac.sv
+++ b/hw/ip/hmac/rtl/hmac.sv
@@ -18,7 +18,7 @@
output tlul_pkg::tl_d2h_t tl_o,
output logic intr_hmac_done_o,
- output logic intr_fifo_full_o,
+ output logic intr_fifo_empty_o,
output logic intr_hmac_err_o,
// alerts
@@ -192,17 +192,18 @@
////////////////
// Interrupts //
////////////////
- logic fifo_full_q;
+ logic fifo_empty_q, fifo_empty_event;
always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) fifo_full_q <= 1'b0;
- else fifo_full_q <= fifo_full;
+ if (!rst_ni) begin
+ fifo_empty_q <= '1; // By default, it is empty
+ end else if (!hmac_fifo_wsel) begin
+ fifo_empty_q <= fifo_empty;
+ end
end
-
- logic fifo_full_event;
- assign fifo_full_event = fifo_full & !fifo_full_q;
+ assign fifo_empty_event = fifo_empty & ~fifo_empty_q;
logic [2:0] event_intr;
- assign event_intr = {err_valid, fifo_full_event, reg_hash_done};
+ assign event_intr = {err_valid, fifo_empty_event, reg_hash_done};
// instantiate interrupt hardware primitive
prim_intr_hw #(.Width(1)) intr_hw_hmac_done (
@@ -215,15 +216,15 @@
.hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_done.d),
.intr_o (intr_hmac_done_o)
);
- prim_intr_hw #(.Width(1)) intr_hw_fifo_full (
+ prim_intr_hw #(.Width(1)) intr_hw_fifo_empty (
.event_intr_i (event_intr[1]),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fifo_full.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.fifo_full.q),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.fifo_full.qe),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.fifo_full.q),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.fifo_full.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.fifo_full.d),
- .intr_o (intr_fifo_full_o)
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fifo_empty.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.fifo_empty.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.fifo_empty.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.fifo_empty.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.fifo_empty.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.fifo_empty.d),
+ .intr_o (intr_fifo_empty_o)
);
prim_intr_hw #(.Width(1)) intr_hw_hmac_err (
.event_intr_i (event_intr[2]),
@@ -565,7 +566,7 @@
// All outputs should be known value after reset
`ASSERT_KNOWN(IntrHmacDoneOKnown, intr_hmac_done_o)
- `ASSERT_KNOWN(IntrFifoFullOKnown, intr_fifo_full_o)
+ `ASSERT_KNOWN(IntrFifoEmptyOKnown, intr_fifo_empty_o)
`ASSERT_KNOWN(TlODValidKnown, tl_o.d_valid)
`ASSERT_KNOWN(TlOAReadyKnown, tl_o.a_ready)
diff --git a/hw/ip/hmac/rtl/hmac_core.sv b/hw/ip/hmac/rtl/hmac_core.sv
index 7a2beb3..a1c9515 100644
--- a/hw/ip/hmac/rtl/hmac_core.sv
+++ b/hw/ip/hmac/rtl/hmac_core.sv
@@ -227,6 +227,7 @@
StMsg: begin
sel_rdata = SelFifo;
+ fifo_wsel = (round_q == Outer);
if ( (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
&& (txcount >= sha_message_length)) begin
@@ -276,6 +277,7 @@
StOPad: begin
sel_rdata = SelOPad;
+ fifo_wsel = 1'b1; // Remained HMAC select to indicate HMAC is in second stage
if (txcnt_eq_blksz) begin
st_d = StMsg;
diff --git a/hw/ip/hmac/rtl/hmac_reg_pkg.sv b/hw/ip/hmac/rtl/hmac_reg_pkg.sv
index d9ac641..5ab5b02 100644
--- a/hw/ip/hmac/rtl/hmac_reg_pkg.sv
+++ b/hw/ip/hmac/rtl/hmac_reg_pkg.sv
@@ -18,7 +18,7 @@
} hmac_done;
struct packed {
logic q;
- } fifo_full;
+ } fifo_empty;
struct packed {
logic q;
} hmac_err;
@@ -30,7 +30,7 @@
} hmac_done;
struct packed {
logic q;
- } fifo_full;
+ } fifo_empty;
struct packed {
logic q;
} hmac_err;
@@ -44,7 +44,7 @@
struct packed {
logic q;
logic qe;
- } fifo_full;
+ } fifo_empty;
struct packed {
logic q;
logic qe;
@@ -100,7 +100,7 @@
struct packed {
logic d;
logic de;
- } fifo_full;
+ } fifo_empty;
struct packed {
logic d;
logic de;
diff --git a/hw/ip/hmac/rtl/hmac_reg_top.sv b/hw/ip/hmac/rtl/hmac_reg_top.sv
index ef1c1ed..ef6ffd5 100644
--- a/hw/ip/hmac/rtl/hmac_reg_top.sv
+++ b/hw/ip/hmac/rtl/hmac_reg_top.sv
@@ -120,25 +120,25 @@
logic intr_state_hmac_done_qs;
logic intr_state_hmac_done_wd;
logic intr_state_hmac_done_we;
- logic intr_state_fifo_full_qs;
- logic intr_state_fifo_full_wd;
- logic intr_state_fifo_full_we;
+ logic intr_state_fifo_empty_qs;
+ logic intr_state_fifo_empty_wd;
+ logic intr_state_fifo_empty_we;
logic intr_state_hmac_err_qs;
logic intr_state_hmac_err_wd;
logic intr_state_hmac_err_we;
logic intr_enable_hmac_done_qs;
logic intr_enable_hmac_done_wd;
logic intr_enable_hmac_done_we;
- logic intr_enable_fifo_full_qs;
- logic intr_enable_fifo_full_wd;
- logic intr_enable_fifo_full_we;
+ logic intr_enable_fifo_empty_qs;
+ logic intr_enable_fifo_empty_wd;
+ logic intr_enable_fifo_empty_we;
logic intr_enable_hmac_err_qs;
logic intr_enable_hmac_err_wd;
logic intr_enable_hmac_err_we;
logic intr_test_hmac_done_wd;
logic intr_test_hmac_done_we;
- logic intr_test_fifo_full_wd;
- logic intr_test_fifo_full_we;
+ logic intr_test_fifo_empty_wd;
+ logic intr_test_fifo_empty_we;
logic intr_test_hmac_err_wd;
logic intr_test_hmac_err_we;
logic cfg_hmac_en_qs;
@@ -234,29 +234,29 @@
);
- // F[fifo_full]: 1:1
+ // F[fifo_empty]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
- ) u_intr_state_fifo_full (
+ ) u_intr_state_fifo_empty (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_state_fifo_full_we),
- .wd (intr_state_fifo_full_wd),
+ .we (intr_state_fifo_empty_we),
+ .wd (intr_state_fifo_empty_wd),
// from internal hardware
- .de (hw2reg.intr_state.fifo_full.de),
- .d (hw2reg.intr_state.fifo_full.d ),
+ .de (hw2reg.intr_state.fifo_empty.de),
+ .d (hw2reg.intr_state.fifo_empty.d ),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.fifo_full.q ),
+ .q (reg2hw.intr_state.fifo_empty.q ),
// to register interface (read)
- .qs (intr_state_fifo_full_qs)
+ .qs (intr_state_fifo_empty_qs)
);
@@ -314,18 +314,18 @@
);
- // F[fifo_full]: 1:1
+ // F[fifo_empty]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_intr_enable_fifo_full (
+ ) u_intr_enable_fifo_empty (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_enable_fifo_full_we),
- .wd (intr_enable_fifo_full_wd),
+ .we (intr_enable_fifo_empty_we),
+ .wd (intr_enable_fifo_empty_wd),
// from internal hardware
.de (1'b0),
@@ -333,10 +333,10 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.fifo_full.q ),
+ .q (reg2hw.intr_enable.fifo_empty.q ),
// to register interface (read)
- .qs (intr_enable_fifo_full_qs)
+ .qs (intr_enable_fifo_empty_qs)
);
@@ -383,17 +383,17 @@
);
- // F[fifo_full]: 1:1
+ // F[fifo_empty]: 1:1
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_fifo_full (
+ ) u_intr_test_fifo_empty (
.re (1'b0),
- .we (intr_test_fifo_full_we),
- .wd (intr_test_fifo_full_wd),
+ .we (intr_test_fifo_empty_we),
+ .wd (intr_test_fifo_empty_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.fifo_full.qe),
- .q (reg2hw.intr_test.fifo_full.q ),
+ .qe (reg2hw.intr_test.fifo_empty.qe),
+ .q (reg2hw.intr_test.fifo_empty.q ),
.qs ()
);
@@ -977,8 +977,8 @@
assign intr_state_hmac_done_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_hmac_done_wd = reg_wdata[0];
- assign intr_state_fifo_full_we = addr_hit[0] & reg_we & ~wr_err;
- assign intr_state_fifo_full_wd = reg_wdata[1];
+ assign intr_state_fifo_empty_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_fifo_empty_wd = reg_wdata[1];
assign intr_state_hmac_err_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_hmac_err_wd = reg_wdata[2];
@@ -986,8 +986,8 @@
assign intr_enable_hmac_done_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_hmac_done_wd = reg_wdata[0];
- assign intr_enable_fifo_full_we = addr_hit[1] & reg_we & ~wr_err;
- assign intr_enable_fifo_full_wd = reg_wdata[1];
+ assign intr_enable_fifo_empty_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_fifo_empty_wd = reg_wdata[1];
assign intr_enable_hmac_err_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_hmac_err_wd = reg_wdata[2];
@@ -995,8 +995,8 @@
assign intr_test_hmac_done_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_hmac_done_wd = reg_wdata[0];
- assign intr_test_fifo_full_we = addr_hit[2] & reg_we & ~wr_err;
- assign intr_test_fifo_full_wd = reg_wdata[1];
+ assign intr_test_fifo_empty_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_fifo_empty_wd = reg_wdata[1];
assign intr_test_hmac_err_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_hmac_err_wd = reg_wdata[2];
@@ -1081,13 +1081,13 @@
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = intr_state_hmac_done_qs;
- reg_rdata_next[1] = intr_state_fifo_full_qs;
+ reg_rdata_next[1] = intr_state_fifo_empty_qs;
reg_rdata_next[2] = intr_state_hmac_err_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = intr_enable_hmac_done_qs;
- reg_rdata_next[1] = intr_enable_fifo_full_qs;
+ reg_rdata_next[1] = intr_enable_fifo_empty_qs;
reg_rdata_next[2] = intr_enable_hmac_err_qs;
end
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index c661050..6f63bb1 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -394,7 +394,7 @@
type: interrupt
}
{
- name: fifo_full
+ name: fifo_empty
width: 1
type: interrupt
}
@@ -1327,7 +1327,7 @@
type: interrupt
}
{
- name: hmac_fifo_full
+ name: hmac_fifo_empty
width: 1
type: interrupt
}
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index d111b9e..dfc5e03 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -207,7 +207,7 @@
logic intr_flash_ctrl_op_error;
logic intr_rv_timer_timer_expired_0_0;
logic intr_hmac_hmac_done;
- logic intr_hmac_fifo_full;
+ logic intr_hmac_fifo_empty;
logic intr_hmac_hmac_err;
logic intr_alert_handler_classa;
logic intr_alert_handler_classb;
@@ -608,9 +608,9 @@
.tl_o (tl_hmac_d_d2h),
// Interrupt
- .intr_hmac_done_o (intr_hmac_hmac_done),
- .intr_fifo_full_o (intr_hmac_fifo_full),
- .intr_hmac_err_o (intr_hmac_hmac_err),
+ .intr_hmac_done_o (intr_hmac_hmac_done),
+ .intr_fifo_empty_o (intr_hmac_fifo_empty),
+ .intr_hmac_err_o (intr_hmac_hmac_err),
// [0]: msg_push_sha_disabled
.alert_tx_o ( alert_tx[0:0] ),
@@ -767,7 +767,7 @@
intr_alert_handler_classb,
intr_alert_handler_classa,
intr_hmac_hmac_err,
- intr_hmac_fifo_full,
+ intr_hmac_fifo_empty,
intr_hmac_hmac_done,
intr_flash_ctrl_op_error,
intr_flash_ctrl_op_done,
