| commit | d8929edef7e4339f9433c39f2a885d438c747e6f | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Fri Nov 20 23:30:37 2020 -0800 |
| committer | Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> | Fri Nov 27 10:13:01 2020 -0800 |
| tree | 1b5b71f44f09d4cef9f3eb1c036ee434a188e8ae | |
| parent | 250a399da5f055914ae9d70f10c69da595d33277 [diff] |
[dv, meson] Integrate DV SW build steps into meson This change is part 3/4 commit series that updates the way SW tests are build for chip level. For the chip level SW tests to pass, all 4 commits are needed. This integrates the step that extracts the logs and rodata sections from the embedded SW elf into meson. This change is only enabled for 'sim_dv' device, so others should remain unaffected. Previously, this was done in DV simulation flow `hw/dv/tools/dvsim/sim.mk`. Signed-off-by: Srikrishna Iyer <sriyer@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).