[flash_ctrl] Cosmetic updates enum literals
- Updated enum literals for type `foo_bar_e` to `FooBarLiteral1` format
- Associated updates to all relevant sources
- No functional change
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index c1a5591..9a09939 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -108,9 +108,9 @@
logic [AllPagesW-1:0] err_page;
logic [BankW-1:0] err_bank;
- assign rd_op = reg2hw.control.op.q == FlashRead;
- assign prog_op = reg2hw.control.op.q == FlashProg;
- assign erase_op = reg2hw.control.op.q == FlashErase;
+ assign rd_op = reg2hw.control.op.q == FlashOpRead;
+ assign prog_op = reg2hw.control.op.q == FlashOpProgram;
+ assign erase_op = reg2hw.control.op.q == FlashOpErase;
// Program FIFO
// Since the program and read FIFOs are never used at the same time, it should really be one
@@ -289,15 +289,15 @@
// Final muxing to flash macro module
always_comb begin
unique case (reg2hw.control.op.q)
- FlashRead: begin
+ FlashOpRead: begin
flash_req = rd_flash_req;
flash_addr = rd_flash_addr;
end
- FlashProg: begin
+ FlashOpProgram: begin
flash_req = prog_flash_req;
flash_addr = prog_flash_addr;
end
- FlashErase: begin
+ FlashOpErase: begin
flash_req = erase_flash_req;
flash_addr = erase_flash_addr;
end
@@ -322,7 +322,7 @@
assign region_cfgs[MpRegions].erase_en.q = reg2hw.default_region.erase_en.q;
// we are allowed to set default accessibility of data partitions
// however info partitions default to inaccessible
- assign region_cfgs[MpRegions].partition.q = DataPart;
+ assign region_cfgs[MpRegions].partition.q = FlashPartData;
flash_part_e flash_part_sel;
assign flash_part_sel = flash_part_e'(reg2hw.control.partition_sel.q);
@@ -350,8 +350,8 @@
.req_bk_i(flash_addr[BusAddrW-1 -: BankW]),
.rd_i(rd_op),
.prog_i(prog_op),
- .pg_erase_i(erase_op & (erase_flash_type == PageErase)),
- .bk_erase_i(erase_op & (erase_flash_type == BankErase)),
+ .pg_erase_i(erase_op & (erase_flash_type == FlashErasePage)),
+ .bk_erase_i(erase_op & (erase_flash_type == FlashEraseBank)),
.rd_done_o(flash_rd_done),
.prog_done_o(flash_prog_done),
.erase_done_o(flash_erase_done),
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
index f8351f6..bef591e 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
@@ -7,13 +7,18 @@
package flash_ctrl_pkg;
- // flash phy parameters
+ // design constants
parameter int DataWidth = top_pkg::FLASH_DATA_WIDTH;
- parameter int DataByteWidth = $clog2(DataWidth / 8);
parameter int NumBanks = top_pkg::FLASH_BANKS;
- parameter int InfosPerBank = top_pkg::FLASH_INFO_PER_BANK; //Info pages per bank
- parameter int PagesPerBank = top_pkg::FLASH_PAGES_PER_BANK; //Data pages per bank
- parameter int WordsPerPage = top_pkg::FLASH_WORDS_PER_PAGE; //Number of bus words per page
+ parameter int InfosPerBank = top_pkg::FLASH_INFO_PER_BANK; // Info pages per bank
+ parameter int PagesPerBank = top_pkg::FLASH_PAGES_PER_BANK; // Data pages per bank
+ parameter int WordsPerPage = top_pkg::FLASH_WORDS_PER_PAGE; // Number of bus words per page
+ parameter int BusWidth = top_pkg::TL_DW;
+ parameter int MpRegions = 8; // flash controller protection regions
+ parameter int FifoDepth = 16; // rd / prog fifos
+
+ // flash phy parameters
+ parameter int DataByteWidth = $clog2(DataWidth / 8);
parameter int BankW = $clog2(NumBanks);
parameter int PageW = $clog2(PagesPerBank);
parameter int WordW = $clog2(WordsPerPage);
@@ -23,7 +28,6 @@
// flash ctrl / bus parameters
// flash / bus width may be different from actual flash word width
- parameter int BusWidth = top_pkg::TL_DW;
parameter int BusByteWidth = $clog2(BusWidth / 8);
parameter int WidthMultiple = DataWidth / BusWidth;
parameter int BusWordsPerPage = WordsPerPage * WidthMultiple;
@@ -32,27 +36,24 @@
parameter int BusBankAddrW = PageW + BusWordW;
parameter int PhyAddrStart = BusWordW - WordW;
- // flash controller protection regions
- parameter int MpRegions = 8;
-
// fifo parameters
- parameter int FifoDepth = 16;
parameter int FifoDepthW = $clog2(FifoDepth+1);
// Flash Operations Supported
typedef enum logic [1:0] {
- FlashRead = 2'h0,
- FlashProg = 2'h1,
- FlashErase = 2'h2
+ FlashOpRead = 2'h0,
+ FlashOpProgram = 2'h1,
+ FlashOpErase = 2'h2,
+ FlashOpInvalid = 2'h3
} flash_op_e;
// Flash Erase Operations Supported
typedef enum logic {
- PageErase = 0,
- BankErase = 1
- } flash_erase_op_e;
+ FlashErasePage = 0,
+ FlashEraseBank = 1
+ } flash_erase_e;
- parameter int EraseBitWidth = $bits(flash_erase_op_e);
+ parameter int EraseBitWidth = $bits(flash_erase_e);
// Flash tlul to fifo direction
typedef enum logic {
@@ -62,8 +63,8 @@
// Flash partition type
typedef enum logic {
- DataPart = 1'b0,
- InfoPart = 1'b1
+ FlashPartData = 1'b0,
+ FlashPartInfo = 1'b1
} flash_part_e;
// Flash controller to memory
@@ -89,7 +90,7 @@
prog: 1'b0,
pg_erase: 1'b0,
bk_erase: 1'b0,
- part: DataPart,
+ part: FlashPartData,
addr: '0,
prog_data: '0,
prog_last: '0,
diff --git a/hw/ip/flash_ctrl/rtl/flash_erase_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_erase_ctrl.sv
index 86b1901..4c12b0a 100644
--- a/hw/ip/flash_ctrl/rtl/flash_erase_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_erase_ctrl.sv
@@ -48,7 +48,7 @@
// Flash Interface assignments
assign flash_req_o = op_start_i;
assign flash_op_o = op_type_i;
- assign flash_addr_o = (op_type_i == PageErase) ?
+ assign flash_addr_o = (op_type_i == FlashErasePage) ?
op_addr_i & PageAddrMask :
op_addr_i & BankAddrMask;
diff --git a/hw/ip/flash_ctrl/rtl/flash_mp.sv b/hw/ip/flash_ctrl/rtl/flash_mp.sv
index 31e7fae..2ea1fbb 100644
--- a/hw/ip/flash_ctrl/rtl/flash_mp.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_mp.sv
@@ -97,7 +97,7 @@
always_comb begin
for (int unsigned i = 0; i < NumBanks; i++) begin: bank_comps
bk_erase_en[i] = (req_bk_i == i) & bank_cfgs_i[i].q &
- (req_part_i == DataPart);
+ (req_part_i == FlashPartData);
end
end
@@ -105,13 +105,13 @@
// invalid info page access
assign invalid_info_access = req_i &
- (req_part_i == InfoPart) &
+ (req_part_i == FlashPartInfo) &
(rd_i | prog_i | pg_erase_i) &
(req_addr_i[0 +: PageW] > LastValidInfoPage);
// invalid info page erase
assign invalid_info_erase = req_i & bk_erase_i &
- (req_part_i == InfoPart);
+ (req_part_i == FlashPartInfo);
assign invalid_info_txn = invalid_info_access | invalid_info_erase;
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
index ddc0518..4204b13 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
@@ -208,7 +208,7 @@
end // always_comb
assign muxed_addr = host_sel ? host_addr_i : addr_i;
- assign muxed_part = host_sel ? flash_ctrl_pkg::DataPart : part_i;
+ assign muxed_part = host_sel ? flash_ctrl_pkg::FlashPartData : part_i;
assign rd_done_o = ctrl_rsp_vld & rd_i;
assign prog_done_o = ctrl_rsp_vld & prog_i;
assign erase_done_o = ctrl_rsp_vld & (pg_erase_i | bk_erase_i);
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_rd_buffers.sv b/hw/ip/flash_ctrl/rtl/flash_phy_rd_buffers.sv
index abf4b02..c44cd12 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_rd_buffers.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_rd_buffers.sv
@@ -35,7 +35,7 @@
if (!rst_ni) begin
out_o.data <= '0;
out_o.addr <= '0;
- out_o.part <= flash_ctrl_pkg::DataPart;
+ out_o.part <= flash_ctrl_pkg::FlashPartData;
out_o.attr <= Invalid;
end else if (wipe_i) begin
out_o.attr <= Invalid;
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash.sv b/hw/ip/prim_generic/rtl/prim_generic_flash.sv
index 1f0ec3c..3c4d016 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_flash.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_flash.sv
@@ -102,7 +102,7 @@
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
held_addr <= '0;
- held_part <= flash_ctrl_pkg::DataPart;
+ held_part <= flash_ctrl_pkg::FlashPartData;
held_wdata <= '0;
end else if (hold_cmd) begin
held_addr <= rd_q ? addr_q : addr_i;
@@ -155,7 +155,7 @@
mem_req = 'h0;
mem_wr = 'h0;
mem_addr = 'h0;
- mem_part = flash_ctrl_pkg::DataPart;
+ mem_part = flash_ctrl_pkg::FlashPartData;
mem_wdata = 'h0;
time_cnt_inc = 1'h0;
time_cnt_clr = 1'h0;
@@ -291,7 +291,7 @@
.DataBitsPerMask(DataWidth)
) u_mem (
.clk_i,
- .req_i (mem_req & (mem_part == flash_ctrl_pkg::DataPart)),
+ .req_i (mem_req & (mem_part == flash_ctrl_pkg::FlashPartData)),
.write_i (mem_wr),
.addr_i (mem_addr),
.wdata_i (mem_wdata),
@@ -305,7 +305,7 @@
.DataBitsPerMask(DataWidth)
) u_info_mem (
.clk_i,
- .req_i (mem_req & (mem_part == flash_ctrl_pkg::InfoPart)),
+ .req_i (mem_req & (mem_part == flash_ctrl_pkg::FlashPartInfo)),
.write_i (mem_wr),
.addr_i (mem_addr[0 +: InfoAddrW]),
.wdata_i (mem_wdata),
@@ -313,6 +313,6 @@
.rdata_o (rd_data_info)
);
- assign rd_data_o = held_part == flash_ctrl_pkg::DataPart ? rd_data_main : rd_data_info;
+ assign rd_data_o = held_part == flash_ctrl_pkg::FlashPartData ? rd_data_main : rd_data_info;
endmodule // prim_generic_flash
