tree: c0000c5bc7bb3331031316463d6d789e70794b27 [path history] [tgz]
  1. doc/
  2. dv/
  3. fpv/
  4. rtl/
  5. sw/
  6. Makefile
  7. README.md
  8. rv_plic.core
  9. rv_plic_component.core
hw/ip/rv_plic/README.md

RISC-V Platform-Level Interrupt Controller

RV_PLIC module is to manage multiple interrupt events generated from the peripherals. It implements Platform-Level Interrupt Controller in RISC-V Privileges specification Section 7.

reg_rv_plic.py

The tool is to create register hjson and top module rv_plic.sv files given values of number of sources, number of targets, and max value of priority. By default target is 1 and priority is 7 (8 level of priorities supported)

To change the value and to re-create hjson,

$ reg_rv_plic.py -s 64 -t 2 -p 15 rv_plic.hjson.tpl > rv_plic.hjson
$ reg_rv_plic.py -s 64 -t 2 -p 15 rv_plic.sv.tpl > ../rtl/rv_plic.sv