[util, topgen] Autogened top_earlgrey_pkg updates
- Updated `topgen` to use C specific py rendering helper functions to
generate base addr and sizes of IPs and memories
- Split top_earlgrey_pkg into its own fusesoc core file since DV depends
only in it
- Associated updates to top specific core files
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/top_earlgrey/data/top_earlgrey_pkg.sv.tpl b/hw/top_earlgrey/data/top_earlgrey_pkg.sv.tpl
index 7af8a85..054d42b 100644
--- a/hw/top_earlgrey/data/top_earlgrey_pkg.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey_pkg.sv.tpl
@@ -21,14 +21,30 @@
top["name"], sig["name"], start_idx))
%>\
package top_${top["name"]}_pkg;
+% for name, region in helper.modules():
+ /**
+ * Peripheral base address for ${name} in top ${top["name"]}.
+ */
+ parameter int unsigned ${region.base_addr_name().as_c_define()} = 32'h${region.base_addr[2:]};
- // Base addresses of all peripherals.
- % for m in top["module"]:
- ${"parameter logic [31:0] TOP_{}_{}_BASE_ADDR = 32'h{}".format(top["name"].upper(),
- m["name"].upper(),
- m["base_addr"][2:])};
- % endfor
+ /**
+ * Peripheral size in bytes for ${name} in top ${top["name"]}.
+ */
+ parameter int unsigned ${region.size_bytes_name().as_c_define()} = 32'h${region.size_bytes[2:]};
+% endfor
+% for name, region in helper.memories():
+ /**
+ * Memory base address for ${name} in top ${top["name"]}.
+ */
+ parameter int unsigned ${region.base_addr_name().as_c_define()} = 32'h${region.base_addr[2:]};
+
+ /**
+ * Memory size for ${name} in top ${top["name"]}.
+ */
+ parameter int unsigned ${region.size_bytes_name().as_c_define()} = 32'h${region.size_bytes[2:]};
+
+% endfor
// Enumeration for DIO pins.
typedef enum {
<% pin_cnt = 0 %>\
