| commit | d7bed87216e67530bbb51f10a401682b1f988e68 | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Wed Oct 14 11:51:10 2020 -0700 |
| committer | sriyerg <46467186+sriyerg@users.noreply.github.com> | Fri Oct 16 10:36:33 2020 -0700 |
| tree | 10663f8ed75311cf69716da052c66600fa884a7a | |
| parent | 2e6b627912075c15ecd5144abc5f3466b22186a5 [diff] |
[util, topgen] Autogened top_earlgrey_pkg updates - Updated `topgen` to use C specific py rendering helper functions to generate base addr and sizes of IPs and memories - Split top_earlgrey_pkg into its own fusesoc core file since DV depends only in it - Associated updates to top specific core files Signed-off-by: Srikrishna Iyer <sriyer@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).