Initial hjson + reg commit for I2C
- Definition of registers and interrupts
- Creation of register hardware
- Support For override mode
- Emulation of "Virtual Open Drain" outputs on SCL/SDA (i.e. "1" maps to "Z" at output)
diff --git a/hw/ip/i2c/doc/i2c.hjson b/hw/ip/i2c/doc/i2c.hjson
new file mode 100644
index 0000000..7fc713d
--- /dev/null
+++ b/hw/ip/i2c/doc/i2c.hjson
@@ -0,0 +1,381 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+{ name: "i2c"
+ clock_primary: "clk_fixed"
+ bus_device: "tlul"
+ bus_host: "none"
+ // INPUT pins
+ available_input_list: [
+ { name: "sda_rx", desc: "Serial input data bit" }
+ { name: "scl_rx", desc: "Serial input clock bit" }
+ ]
+ // OUTPUT pins
+ available_output_list: [
+ { name: "sda_tx", desc: "Serial output data bit" }
+ { name: "scl_tx", desc: "Serial output clock bit" }
+ ]
+ // INTERRUPT pins
+ interrupt_list: [
+ { name: "fmt_watermark"
+ desc: "raised when the FMT FIFO depth falls below the lowwater mark."
+ }
+ { name: "rx_watermark"
+ desc: "raised if the RX FIFO is past the highwater mark."
+ }
+ { name: "fmt_overflow"
+ desc: "raised if the FMT FIFO has overflowed."
+ }
+ { name: "rx_overflow"
+ desc: "raised if the RX FIFO has overflowed."
+ }
+ { name: "nak"
+ desc: "raised if there is no ACK in response to an address or data write"
+ }
+ { name: "scl_interference"
+ desc: "raised if the SCL line drops early (not supported without clock synchronization)."
+ }
+ { name: "sda_interference"
+ desc: "raised if the SDA line goes low when master is trying to assert high"
+ }
+ { name: "stretch_timeout"
+ desc: "raised if target stretches the clock beyond the allowed timeout period"
+ }
+ { name: "sda_unstable"
+ desc: "raised if the target does not assert a constant value of SDA during transmission."
+ }
+ ]
+
+ // REGISTER definition
+ regwidth: "32"
+ registers: [
+ // CTRL register
+ { name: "CTRL"
+ desc: "I2C control register (Functions TBD)"
+ swaccess: "rw"
+ hwaccess: "hro"
+ fields: [
+ { bits: "0"
+ resval: "0"
+ name: "ENABLEHOST"
+ desc: '''
+ Enable Host I2C functionality
+ '''
+ }
+ ]
+ }
+ { name: "STATUS"
+ desc: "I2C live status register"
+ swaccess: "ro"
+ hwaccess: "hrw"
+ hwext: "true"
+ hwre: "true"
+ fields: [
+ { bits: "0"
+ name: "FMTFULL"
+ desc: "TX buffer is full"
+ }
+ { bits: "1"
+ name: "RXFULL"
+ desc: "RX buffer is full"
+ }
+ { bits: "2"
+ name: "FMTEMPTY"
+ desc: "FMT FIFO is empty"
+ resval: "1"
+ }
+ { bits: "5"
+ name: "RXEMPTY"
+ desc: "RX FIFO is empty"
+ resval: "1"
+ }
+ { bits: "3"
+ name: "HOSTIDLE"
+ desc: "Host functionality is idle. No Host transaction is in progress"
+ resval: "1"
+ }
+ { bits: "4"
+ name: "TARGETIDLE"
+ desc: "Target functionality is idle No Target transaction is in progress"
+ resval: "1"
+ }
+ ]
+ }
+ { name: "RDATA"
+ desc: "I2C read data"
+ swaccess: "ro"
+ hwext: "true"
+ hwre: "true"
+ fields: [
+ {bits: "7:0"}
+ ]
+ }
+ { name: "FDATA"
+ desc: "I2C Format Data"
+ swaccess: "wo"
+ hwaccess: "hro"
+ hwqe: "true"
+ fields: [
+ { bits: "7:0"
+ name: "FBYTE"
+ desc: "Format Byte. Directly transmitted if no flags are set."
+ }
+ { bits: "8"
+ name: "START"
+ desc: "Issue a START condition before transmitting BYTE."
+ }
+ { bits: "9"
+ name: "STOP"
+ desc: "Issue a STOP condition after this operation"
+ }
+ { bits: "10"
+ name: "READ"
+ desc: "Read BYTE bytes from I2C. (256 if BYTE==0)"
+ }
+ { bits: "11"
+ name: "RCONT"
+ desc: "Do not NAK the last byte read, let the read operation continue"
+ }
+ { bits: "12"
+ name: "NAKOK"
+ desc: "Do not signal an exception if the current byte is not ACK'd"
+ }
+ ]
+ }
+ { name: "FIFO_CTRL"
+ desc: "I2C FIFO control register"
+ swaccess: "rw"
+ hwaccess: "hro"
+ hwqe: "true"
+ fields: [
+ { bits: "0"
+ swaccess: "wo"
+ name: "RXRST"
+ desc: "RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0"
+ }
+ { bits: "1"
+ swaccess: "wo"
+ name: "FMTRST"
+ desc: "FMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0"
+ }
+ { bits: "4:2"
+ name: "RXILVL"
+ desc: '''Trigger level for RX interrupts. If the FIFO depth exceeds
+ this setting, it raises rx_watermark interrupt.
+ '''
+ enum: [
+ { value: "0",
+ name: "rxlvl1",
+ desc: "1 character"
+ },
+ { value: "1",
+ name: "rxlvl4",
+ desc: "4 characters"
+ },
+ { value: "2",
+ name: "rxlvl8",
+ desc: "8 characters"
+ },
+ { value: "3",
+ name: "rxlvl16",
+ desc: "16 characters"
+ },
+ { value: "4",
+ name: "rxlvl30",
+ desc: "30 characters"
+ },
+ ]
+ }
+ { bits: "6:5"
+ name: "FMTILVL"
+ desc: '''Trigger level for FMT interrupts. If the FIFO depth falls below
+ this setting, it raises fmt_watermark interrupt.
+ '''
+ enum: [
+ { value: "0",
+ name: "fmtlvl1"
+ desc: "1 character"
+ },
+ { value: "1",
+ name: "fmtlvl4",
+ desc: "4 characters"
+ },
+ { value: "2",
+ name: "fmtlvl8",
+ desc: "8 characters"
+ },
+ { value: "3",
+ name: "fmtlvl16",
+ desc: "16 characters"
+ }
+ ]
+ }
+ ]
+ }
+ { name: "FIFO_STATUS"
+ desc: "I2C FIFO status register"
+ swaccess: "ro"
+ hwaccess: "hwo"
+ hwext: "true"
+ fields: [
+ { bits: "5:0"
+ name: "FMTLVL"
+ desc: "Current fill level of FMT fifo"
+ }
+ { bits: "21:16"
+ name: "RXLVL"
+ desc: "Current fill level of RX fifo"
+ }
+ ]
+ }
+ { name: "OVRD"
+ desc: "I2C override control register"
+ swaccess: "rw"
+ hwaccess: "hro"
+ fields: [
+ { bits: "0",
+ name: "TXOVRDEN",
+ desc: "Override the SDA and SCL TX signals."
+ }
+ { bits: "1",
+ name: "SCLVAL",
+ desc: "Value for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z"
+ }
+ { bits: "2",
+ name: "SDAVAL",
+ desc: "Value for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z"
+ }
+ ]
+ }
+ { name: "VAL"
+ desc: "Oversampled RX values"
+ swaccess: "ro"
+ hwaccess: "hwo"
+ hwext: "true"
+ fields: [
+ { bits: "15:0"
+ name: "SCL_RX"
+ desc: '''
+ Last 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.
+ '''
+ }
+ { bits: "31:16"
+ name: "SDA_RX"
+ desc: '''
+ Last 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31.
+ '''
+ }
+ ]
+ }
+
+ { name: "TIMING0"
+ desc: '''
+ Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+ All values are expressed in units of the input clock period.
+ '''
+ swaccess: "rw"
+ hwaccess: "hro"
+ fields: [
+ { bits: "15:0"
+ name: "THIGH"
+ desc: "The minimum time to hold SCL high in a given pulse"
+ }
+ { bits: "31:16"
+ name: "TLOW"
+ desc: "The minimum time to hold SCL low between any two SCL pulses"
+ }
+ ]
+ }
+ { name: "TIMING1",
+ desc: '''
+ Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+ All values are expressed in units of the input clock period.
+ '''
+ swaccess: "rw"
+ hwaccess: "hro"
+ fields: [
+ { bits: "15:0"
+ name: "T_R"
+ desc: "The nominal rise time to anticipate for the bus (depends on capacitance)"
+ }
+ { bits: "31:16"
+ name: "T_F"
+ desc: "The nominal fall time to anticipate for the bus (influences SDA hold times)"
+ }
+ ]
+ }
+ { name: "TIMING2"
+ desc: '''
+ Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+ All values are expressed in units of the input clock period.
+ '''
+ swaccess: "rw"
+ hwaccess: "hro"
+ fields: [
+ { bits: "15:0"
+ name: "TSU_STA"
+ desc: "Minimum setup time for repeated start signals"
+ }
+ { bits: "31:16"
+ name: "THD_ST"
+ desc: "Minimum hold time for start signals"
+ }
+ ]
+ }
+ { name: "TIMING3"
+ desc: '''
+ Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+ All values are expressed in units of the input clock period.
+ '''
+ swaccess: "rw"
+ hwaccess: "hro"
+ fields: [
+ { bits: "15:0"
+ name: "TSU_DAT"
+ desc: "Minimum setup time for data (or ack) bits"
+ }
+ { bits: "31:16"
+ name: "THD_DAT"
+ desc: '''
+ Minimum hold time for data (or ack) bits
+ (Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)
+ '''
+ }
+ ]
+ }
+ { name: "TIMING4"
+ desc: '''
+ Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+ All values are expressed in units of the input clock period.
+ '''
+ swaccess: "rw"
+ hwaccess: "hro"
+ fields: [
+ { bits: "15:0"
+ name: "TSU_STO"
+ desc: "Minimum setup time for stop signals"
+ }
+ { bits: "31:16"
+ name: "T_BUF"
+ desc: "Minimum time between each STOP signal and the following START signal"
+ }
+ ]
+ }
+ { name: "TIMEOUT_CTRL"
+ desc: "I2C clock stretching timeout control"
+ swaccess: "rw"
+ hwaccess: "hro"
+ fields: [
+ { bits: "30:0"
+ name: "VAL"
+ desc: "Clock stretching timeout value (in units of input clock frequency)"
+ }
+ { bits: "31"
+ name: "EN"
+ desc: "Enable timeout feature"
+ }
+ ]
+ }
+ ]
+}
diff --git a/hw/ip/i2c/i2c.core b/hw/ip/i2c/i2c.core
new file mode 100644
index 0000000..8c6d05c
--- /dev/null
+++ b/hw/ip/i2c/i2c.core
@@ -0,0 +1,24 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:i2c:0.1"
+description: "i2c"
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:constants:top_pkg
+ - lowrisc:prim:all
+ - lowrisc:ip:tlul
+ files:
+ - rtl/i2c_reg_pkg.sv
+ - rtl/i2c_reg_top.sv
+ - rtl/i2c_core.sv
+ - rtl/i2c.sv
+ file_type: systemVerilogSource
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: i2c
diff --git a/hw/ip/i2c/rtl/i2c.sv b/hw/ip/i2c/rtl/i2c.sv
new file mode 100644
index 0000000..4dca14c
--- /dev/null
+++ b/hw/ip/i2c/rtl/i2c.sv
@@ -0,0 +1,87 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: I2C top level wrapper file
+
+module i2c (
+ input clk_i,
+ input rst_ni,
+
+ // Bus Interface
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Generic IO
+ input cio_scl_i,
+ output logic cio_scl_o,
+ output logic cio_scl_en_o,
+ input cio_sda_i,
+ output logic cio_sda_o,
+ output logic cio_sda_en_o,
+
+ // Interrupts
+ output logic intr_fmt_watermark_o,
+ output logic intr_rx_watermark_o,
+ output logic intr_fmt_overflow_o,
+ output logic intr_rx_overflow_o,
+ output logic intr_nak_o,
+ output logic intr_scl_interference_o,
+ output logic intr_sda_interference_o,
+ output logic intr_stretch_timeout_o,
+ output logic intr_sda_unstable_o
+);
+
+ import i2c_reg_pkg::*;
+
+ i2c_reg2hw_t reg2hw;
+ i2c_hw2reg_t hw2reg;
+
+ logic devmode;
+
+ i2c_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+ .tl_i,
+ .tl_o,
+ .reg2hw,
+ .hw2reg,
+ .devmode_i(1'b1)
+ );
+
+ logic scl_int;
+ logic sda_int;
+
+ i2c_core i2c_core (
+ .clk_i,
+ .rst_ni,
+ .reg2hw,
+ .hw2reg,
+
+ .scl_i(cio_scl_i),
+ .scl_o(scl_int),
+ .sda_i(cio_sda_i),
+ .sda_o(sda_int),
+
+ .intr_fmt_watermark_o,
+ .intr_rx_watermark_o,
+ .intr_fmt_overflow_o,
+ .intr_rx_overflow_o,
+ .intr_nak_o,
+ .intr_scl_interference_o,
+ .intr_sda_interference_o,
+ .intr_stretch_timeout_o,
+ .intr_sda_unstable_o
+ );
+
+ // For I2C, in standard, fast and fast-plus modes, outputs simulated as open-drain outputs.
+ // Asserting scl or sda high should be equivalent to a tri-state output.
+ // The output, when enabled, should only assert low.
+
+ assign cio_scl_o = 1'b0;
+ assign cio_sda_o = 1'b0;
+
+ assign cio_scl_en_o = ~scl_int;
+ assign cio_sda_en_o = ~sda_int;
+
+endmodule
diff --git a/hw/ip/i2c/rtl/i2c_core.sv b/hw/ip/i2c/rtl/i2c_core.sv
new file mode 100644
index 0000000..b7dad63
--- /dev/null
+++ b/hw/ip/i2c/rtl/i2c_core.sv
@@ -0,0 +1,213 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: UART core module
+
+module i2c_core (
+ input clk_i,
+ input rst_ni,
+
+ input i2c_reg_pkg::i2c_reg2hw_t reg2hw,
+ output i2c_reg_pkg::i2c_hw2reg_t hw2reg,
+
+ input scl_i,
+ output logic scl_o,
+ input sda_i,
+ output logic sda_o,
+
+ output logic intr_fmt_watermark_o,
+ output logic intr_rx_watermark_o,
+ output logic intr_fmt_overflow_o,
+ output logic intr_rx_overflow_o,
+ output logic intr_nak_o,
+ output logic intr_scl_interference_o,
+ output logic intr_sda_interference_o,
+ output logic intr_stretch_timeout_o,
+ output logic intr_sda_unstable_o
+);
+
+ logic [15:0] thigh;
+ logic [15:0] tlow;
+ logic [15:0] t_r;
+ logic [15:0] t_f;
+ logic [15:0] tsu_sta;
+ logic [15:0] tsu_sto;
+ logic [15:0] thd_st;
+ logic [15:0] tsu_dat;
+ logic [15:0] thd_dat;
+ logic [15:0] t_buf;
+
+ logic scl_out_fsm;
+ logic sda_out_fsm;
+
+ logic event_fmt_watermark;
+ logic event_rx_watermark;
+ logic event_fmt_overflow;
+ logic event_rx_overflow;
+ logic event_nak;
+ logic event_scl_interference;
+ logic event_sda_interference;
+ logic event_stretch_timeout;
+ logic event_sda_unstable;
+
+ logic [15:0] scl_rx_val;
+ logic [15:0] sda_rx_val;
+
+ logic override;
+
+ assign override = reg2hw.ovrd.txovrden;
+
+ // placeholder until FSM in place
+ assign sclout_fsm = 1'b0;
+ assign sdaout_fsm = 1'b0;
+
+ // placeholders for unused output registers
+ assign hw2reg.status.fmtfull.d = 1'b0;
+ assign hw2reg.status.rxfull.d = 1'b0;
+ assign hw2reg.status.fmtempty.d = 1'b0;
+ assign hw2reg.status.hostidle.d = 1'b1;
+ assign hw2reg.status.targetidle.d = 1'b1;
+ assign hw2reg.status.rxempty.d = 1'b0;
+ assign hw2reg.fifo_status.fmtlvl.d = 5'b0;
+ assign hw2reg.fifo_status.rxlvl.d = 5'b0;
+
+
+ assign scl_o = override ? reg2hw.ovrd.sclval : scl_out_fsm;
+ assign sda_o = override ? reg2hw.ovrd.sdaval : sda_out_fsm;
+
+ // TODO: Establish a sample clock period for scl and sda
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if(!rst_ni) begin
+ scl_rx_val <= 16'h0;
+ sda_rx_val <= 16'h0;
+ end else begin
+ scl_rx_val <= {scl_rx_val[14:0], scl_i};
+ sda_rx_val <= {sda_rx_val[14:0], sda_i};
+ end
+ end
+
+ assign hw2reg.val.scl_rx.d = scl_rx_val;
+ assign hw2reg.val.sda_rx.d = sda_rx_val;
+
+ assign thigh = reg2hw.timing0.thigh.q;
+ assign tlow = reg2hw.timing0.tlow.q;
+ assign t_r = reg2hw.timing1.t_r.q;
+ assign t_f = reg2hw.timing1.t_f.q;
+ assign tsu_sta = reg2hw.timing2.tsu_sta.q;
+ assign thd_st = reg2hw.timing2.thd_st.q;
+ assign tsu_dat = reg2hw.timing3.tsu_dat.q;
+ assign thd_dat = reg2hw.timing3.thd_dat.q;
+ assign tsu_sto = reg2hw.timing4.tsu_sto.q;
+ assign t_buf = reg2hw.timing4.t_buf.q;
+
+ assign event_fmt_watermark = 1'b0;
+ assign event_rx_watermark = 1'b0;
+ assign event_fmt_overflow = 1'b0;
+ assign event_rx_overflow = 1'b0;
+ assign event_nak = 1'b0;
+ assign event_scl_interference = 1'b0;
+ assign event_sda_interference = 1'b0;
+ assign event_stretch_timeout = 1'b0;
+ assign event_sda_unstable = 1'b0;
+
+ prim_intr_hw #(.Width(1)) intr_hw_fmt_watermark (
+ .event_intr_i (event_fmt_watermark),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fmt_watermark.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.fmt_watermark.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.fmt_watermark.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.fmt_watermark.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.fmt_watermark.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.fmt_watermark.d),
+ .intr_o (intr_fmt_watermark_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_rx_watermark (
+ .event_intr_i (event_rx_watermark),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_watermark.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_watermark.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_watermark.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_watermark.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_watermark.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_watermark.d),
+ .intr_o (intr_rx_watermark_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_fmt_overflow (
+ .event_intr_i (event_fmt_overflow),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fmt_overflow.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.fmt_overflow.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.fmt_overflow.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.fmt_overflow.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.fmt_overflow.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.fmt_overflow.d),
+ .intr_o (intr_fmt_overflow_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_rx_overflow (
+ .event_intr_i (event_rx_overflow),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_overflow.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_overflow.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_overflow.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_overflow.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_overflow.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_overflow.d),
+ .intr_o (intr_rx_overflow_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_nak (
+ .event_intr_i (event_nak),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.nak.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.nak.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.nak.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.nak.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.nak.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.nak.d),
+ .intr_o (intr_nak_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_scl_interference (
+ .event_intr_i (event_scl_interference),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.scl_interference.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.scl_interference.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.scl_interference.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.scl_interference.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.scl_interference.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.scl_interference.d),
+ .intr_o (intr_scl_interference_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_sda_interference (
+ .event_intr_i (event_sda_interference),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.sda_interference.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.sda_interference.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.sda_interference.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.sda_interference.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.sda_interference.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.sda_interference.d),
+ .intr_o (intr_sda_interference_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_stretch_timeout (
+ .event_intr_i (event_stretch_timeout),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.stretch_timeout.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.stretch_timeout.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.stretch_timeout.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.stretch_timeout.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.stretch_timeout.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.stretch_timeout.d),
+ .intr_o (intr_stretch_timeout_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_sda_unstable (
+ .event_intr_i (event_sda_unstable),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.sda_unstable.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.sda_unstable.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.sda_unstable.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.sda_unstable.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.sda_unstable.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.sda_unstable.d),
+ .intr_o (intr_sda_unstable_o)
+ );
+
+endmodule
diff --git a/hw/ip/i2c/rtl/i2c_reg_pkg.sv b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
new file mode 100644
index 0000000..bb0a305
--- /dev/null
+++ b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
@@ -0,0 +1,387 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package i2c_reg_pkg;
+
+// Register to internal design logic
+typedef struct packed {
+
+ struct packed {
+ struct packed {
+ logic q; // [282]
+ } fmt_watermark;
+ struct packed {
+ logic q; // [281]
+ } rx_watermark;
+ struct packed {
+ logic q; // [280]
+ } fmt_overflow;
+ struct packed {
+ logic q; // [279]
+ } rx_overflow;
+ struct packed {
+ logic q; // [278]
+ } nak;
+ struct packed {
+ logic q; // [277]
+ } scl_interference;
+ struct packed {
+ logic q; // [276]
+ } sda_interference;
+ struct packed {
+ logic q; // [275]
+ } stretch_timeout;
+ struct packed {
+ logic q; // [274]
+ } sda_unstable;
+ } intr_state;
+ struct packed {
+ struct packed {
+ logic q; // [273]
+ } fmt_watermark;
+ struct packed {
+ logic q; // [272]
+ } rx_watermark;
+ struct packed {
+ logic q; // [271]
+ } fmt_overflow;
+ struct packed {
+ logic q; // [270]
+ } rx_overflow;
+ struct packed {
+ logic q; // [269]
+ } nak;
+ struct packed {
+ logic q; // [268]
+ } scl_interference;
+ struct packed {
+ logic q; // [267]
+ } sda_interference;
+ struct packed {
+ logic q; // [266]
+ } stretch_timeout;
+ struct packed {
+ logic q; // [265]
+ } sda_unstable;
+ } intr_enable;
+ struct packed {
+ struct packed {
+ logic q; // [264]
+ logic qe; // [263]
+ } fmt_watermark;
+ struct packed {
+ logic q; // [262]
+ logic qe; // [261]
+ } rx_watermark;
+ struct packed {
+ logic q; // [260]
+ logic qe; // [259]
+ } fmt_overflow;
+ struct packed {
+ logic q; // [258]
+ logic qe; // [257]
+ } rx_overflow;
+ struct packed {
+ logic q; // [256]
+ logic qe; // [255]
+ } nak;
+ struct packed {
+ logic q; // [254]
+ logic qe; // [253]
+ } scl_interference;
+ struct packed {
+ logic q; // [252]
+ logic qe; // [251]
+ } sda_interference;
+ struct packed {
+ logic q; // [250]
+ logic qe; // [249]
+ } stretch_timeout;
+ struct packed {
+ logic q; // [248]
+ logic qe; // [247]
+ } sda_unstable;
+ } intr_test;
+ struct packed {
+ logic [0:0] q; // [246:246]
+ } ctrl;
+ struct packed {
+ struct packed {
+ logic q; // [245]
+ logic re; // [244]
+ } fmtfull;
+ struct packed {
+ logic q; // [243]
+ logic re; // [242]
+ } rxfull;
+ struct packed {
+ logic q; // [241]
+ logic re; // [240]
+ } fmtempty;
+ struct packed {
+ logic q; // [239]
+ logic re; // [238]
+ } hostidle;
+ struct packed {
+ logic q; // [237]
+ logic re; // [236]
+ } targetidle;
+ struct packed {
+ logic q; // [235]
+ logic re; // [234]
+ } rxempty;
+ } status;
+ struct packed {
+ logic [7:0] q; // [233:226]
+ logic re; // [225]
+ } rdata;
+ struct packed {
+ struct packed {
+ logic [7:0] q; // [224:217]
+ logic qe; // [216]
+ } fbyte;
+ struct packed {
+ logic q; // [215]
+ logic qe; // [214]
+ } start;
+ struct packed {
+ logic q; // [213]
+ logic qe; // [212]
+ } stop;
+ struct packed {
+ logic q; // [211]
+ logic qe; // [210]
+ } read;
+ struct packed {
+ logic q; // [209]
+ logic qe; // [208]
+ } rcont;
+ struct packed {
+ logic q; // [207]
+ logic qe; // [206]
+ } nakok;
+ } fdata;
+ struct packed {
+ struct packed {
+ logic q; // [205]
+ logic qe; // [204]
+ } rxrst;
+ struct packed {
+ logic q; // [203]
+ logic qe; // [202]
+ } fmtrst;
+ struct packed {
+ logic [2:0] q; // [201:199]
+ logic qe; // [198]
+ } rxilvl;
+ struct packed {
+ logic [1:0] q; // [197:196]
+ logic qe; // [195]
+ } fmtilvl;
+ } fifo_ctrl;
+ struct packed {
+ struct packed {
+ logic q; // [194]
+ } txovrden;
+ struct packed {
+ logic q; // [193]
+ } sclval;
+ struct packed {
+ logic q; // [192]
+ } sdaval;
+ } ovrd;
+ struct packed {
+ struct packed {
+ logic [15:0] q; // [191:176]
+ } thigh;
+ struct packed {
+ logic [15:0] q; // [175:160]
+ } tlow;
+ } timing0;
+ struct packed {
+ struct packed {
+ logic [15:0] q; // [159:144]
+ } t_r;
+ struct packed {
+ logic [15:0] q; // [143:128]
+ } t_f;
+ } timing1;
+ struct packed {
+ struct packed {
+ logic [15:0] q; // [127:112]
+ } tsu_sta;
+ struct packed {
+ logic [15:0] q; // [111:96]
+ } thd_st;
+ } timing2;
+ struct packed {
+ struct packed {
+ logic [15:0] q; // [95:80]
+ } tsu_dat;
+ struct packed {
+ logic [15:0] q; // [79:64]
+ } thd_dat;
+ } timing3;
+ struct packed {
+ struct packed {
+ logic [15:0] q; // [63:48]
+ } tsu_sto;
+ struct packed {
+ logic [15:0] q; // [47:32]
+ } t_buf;
+ } timing4;
+ struct packed {
+ struct packed {
+ logic [30:0] q; // [31:1]
+ } val;
+ struct packed {
+ logic q; // [0]
+ } en;
+ } timeout_ctrl;
+} i2c_reg2hw_t;
+
+// Internal design logic to register
+typedef struct packed {
+
+ struct packed {
+ struct packed {
+ logic d; // [67]
+ logic de; // [66]
+ } fmt_watermark;
+ struct packed {
+ logic d; // [65]
+ logic de; // [64]
+ } rx_watermark;
+ struct packed {
+ logic d; // [63]
+ logic de; // [62]
+ } fmt_overflow;
+ struct packed {
+ logic d; // [61]
+ logic de; // [60]
+ } rx_overflow;
+ struct packed {
+ logic d; // [59]
+ logic de; // [58]
+ } nak;
+ struct packed {
+ logic d; // [57]
+ logic de; // [56]
+ } scl_interference;
+ struct packed {
+ logic d; // [55]
+ logic de; // [54]
+ } sda_interference;
+ struct packed {
+ logic d; // [53]
+ logic de; // [52]
+ } stretch_timeout;
+ struct packed {
+ logic d; // [51]
+ logic de; // [50]
+ } sda_unstable;
+ } intr_state;
+ struct packed {
+ struct packed {
+ logic d; // [49]
+ } fmtfull;
+ struct packed {
+ logic d; // [48]
+ } rxfull;
+ struct packed {
+ logic d; // [47]
+ } fmtempty;
+ struct packed {
+ logic d; // [46]
+ } hostidle;
+ struct packed {
+ logic d; // [45]
+ } targetidle;
+ struct packed {
+ logic d; // [44]
+ } rxempty;
+ } status;
+ struct packed {
+ struct packed {
+ logic [5:0] d; // [43:38]
+ } fmtlvl;
+ struct packed {
+ logic [5:0] d; // [37:32]
+ } rxlvl;
+ } fifo_status;
+ struct packed {
+ struct packed {
+ logic [15:0] d; // [31:16]
+ } scl_rx;
+ struct packed {
+ logic [15:0] d; // [15:0]
+ } sda_rx;
+ } val;
+} i2c_hw2reg_t;
+
+ // Register Address
+ parameter I2C_INTR_STATE_OFFSET = 7'h 0;
+ parameter I2C_INTR_ENABLE_OFFSET = 7'h 4;
+ parameter I2C_INTR_TEST_OFFSET = 7'h 8;
+ parameter I2C_CTRL_OFFSET = 7'h c;
+ parameter I2C_STATUS_OFFSET = 7'h 10;
+ parameter I2C_RDATA_OFFSET = 7'h 14;
+ parameter I2C_FDATA_OFFSET = 7'h 18;
+ parameter I2C_FIFO_CTRL_OFFSET = 7'h 1c;
+ parameter I2C_FIFO_STATUS_OFFSET = 7'h 20;
+ parameter I2C_OVRD_OFFSET = 7'h 24;
+ parameter I2C_VAL_OFFSET = 7'h 28;
+ parameter I2C_TIMING0_OFFSET = 7'h 2c;
+ parameter I2C_TIMING1_OFFSET = 7'h 30;
+ parameter I2C_TIMING2_OFFSET = 7'h 34;
+ parameter I2C_TIMING3_OFFSET = 7'h 38;
+ parameter I2C_TIMING4_OFFSET = 7'h 3c;
+ parameter I2C_TIMEOUT_CTRL_OFFSET = 7'h 40;
+
+
+ // Register Index
+ typedef enum int {
+ I2C_INTR_STATE,
+ I2C_INTR_ENABLE,
+ I2C_INTR_TEST,
+ I2C_CTRL,
+ I2C_STATUS,
+ I2C_RDATA,
+ I2C_FDATA,
+ I2C_FIFO_CTRL,
+ I2C_FIFO_STATUS,
+ I2C_OVRD,
+ I2C_VAL,
+ I2C_TIMING0,
+ I2C_TIMING1,
+ I2C_TIMING2,
+ I2C_TIMING3,
+ I2C_TIMING4,
+ I2C_TIMEOUT_CTRL
+ } i2c_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] I2C_PERMIT [17] = '{
+ 4'b 0011, // index[ 0] I2C_INTR_STATE
+ 4'b 0011, // index[ 1] I2C_INTR_ENABLE
+ 4'b 0011, // index[ 2] I2C_INTR_TEST
+ 4'b 0001, // index[ 3] I2C_CTRL
+ 4'b 0001, // index[ 4] I2C_STATUS
+ 4'b 0001, // index[ 5] I2C_RDATA
+ 4'b 0011, // index[ 6] I2C_FDATA
+ 4'b 0001, // index[ 7] I2C_FIFO_CTRL
+ 4'b 1111, // index[ 8] I2C_FIFO_STATUS
+ 4'b 0001, // index[ 9] I2C_OVRD
+ 4'b 1111, // index[10] I2C_VAL
+ 4'b 1111, // index[11] I2C_TIMING0
+ 4'b 1111, // index[12] I2C_TIMING1
+ 4'b 1111, // index[13] I2C_TIMING2
+ 4'b 1111, // index[14] I2C_TIMING3
+ 4'b 1111, // index[15] I2C_TIMING4
+ 4'b 1111 // index[16] I2C_TIMEOUT_CTRL
+ };
+endpackage
+
diff --git a/hw/ip/i2c/rtl/i2c_reg_top.sv b/hw/ip/i2c/rtl/i2c_reg_top.sv
new file mode 100644
index 0000000..e53f879
--- /dev/null
+++ b/hw/ip/i2c/rtl/i2c_reg_top.sv
@@ -0,0 +1,2095 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+
+module i2c_reg_top #(
+ parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
+) (
+ input clk_i,
+ input rst_ni,
+
+ // Below Regster interface can be changed
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output i2c_reg_pkg::i2c_reg2hw_t reg2hw, // Write
+ input i2c_reg_pkg::i2c_hw2reg_t hw2reg, // Read
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import i2c_reg_pkg::* ;
+
+ localparam AW = 7;
+ localparam DW = 32;
+ localparam DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW)
+ ) u_reg_if (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ assign reg_rdata = reg_rdata_next ;
+
+ // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
+ // And mandate to return error for address miss
+
+ logic devmode ;
+ assign devmode = LifeCycle ? devmode_i : 1'b1;
+
+ assign reg_error = (devmode & addrmiss) | wr_err ;
+
+ // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
+ // TODO(eunchan): Make concrete scenario
+ // 1. Write: No response, so that it can guarantee a request completes a clock after we
+ // It means, bus_reg_ready doesn't have to be lowered.
+ // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
+ // _____ _____
+ // a_valid _____/ \_______/ \______
+ // ___________ _____
+ // a_ready \_______/ \______ <- ERR though no logic malfunction
+ // _____________
+ // d_valid ___________/ \______
+ // _____
+ // d_ready ___________________/ \______
+ //
+ // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic intr_state_fmt_watermark_qs;
+ logic intr_state_fmt_watermark_wd;
+ logic intr_state_fmt_watermark_we;
+ logic intr_state_rx_watermark_qs;
+ logic intr_state_rx_watermark_wd;
+ logic intr_state_rx_watermark_we;
+ logic intr_state_fmt_overflow_qs;
+ logic intr_state_fmt_overflow_wd;
+ logic intr_state_fmt_overflow_we;
+ logic intr_state_rx_overflow_qs;
+ logic intr_state_rx_overflow_wd;
+ logic intr_state_rx_overflow_we;
+ logic intr_state_nak_qs;
+ logic intr_state_nak_wd;
+ logic intr_state_nak_we;
+ logic intr_state_scl_interference_qs;
+ logic intr_state_scl_interference_wd;
+ logic intr_state_scl_interference_we;
+ logic intr_state_sda_interference_qs;
+ logic intr_state_sda_interference_wd;
+ logic intr_state_sda_interference_we;
+ logic intr_state_stretch_timeout_qs;
+ logic intr_state_stretch_timeout_wd;
+ logic intr_state_stretch_timeout_we;
+ logic intr_state_sda_unstable_qs;
+ logic intr_state_sda_unstable_wd;
+ logic intr_state_sda_unstable_we;
+ logic intr_enable_fmt_watermark_qs;
+ logic intr_enable_fmt_watermark_wd;
+ logic intr_enable_fmt_watermark_we;
+ logic intr_enable_rx_watermark_qs;
+ logic intr_enable_rx_watermark_wd;
+ logic intr_enable_rx_watermark_we;
+ logic intr_enable_fmt_overflow_qs;
+ logic intr_enable_fmt_overflow_wd;
+ logic intr_enable_fmt_overflow_we;
+ logic intr_enable_rx_overflow_qs;
+ logic intr_enable_rx_overflow_wd;
+ logic intr_enable_rx_overflow_we;
+ logic intr_enable_nak_qs;
+ logic intr_enable_nak_wd;
+ logic intr_enable_nak_we;
+ logic intr_enable_scl_interference_qs;
+ logic intr_enable_scl_interference_wd;
+ logic intr_enable_scl_interference_we;
+ logic intr_enable_sda_interference_qs;
+ logic intr_enable_sda_interference_wd;
+ logic intr_enable_sda_interference_we;
+ logic intr_enable_stretch_timeout_qs;
+ logic intr_enable_stretch_timeout_wd;
+ logic intr_enable_stretch_timeout_we;
+ logic intr_enable_sda_unstable_qs;
+ logic intr_enable_sda_unstable_wd;
+ logic intr_enable_sda_unstable_we;
+ logic intr_test_fmt_watermark_wd;
+ logic intr_test_fmt_watermark_we;
+ logic intr_test_rx_watermark_wd;
+ logic intr_test_rx_watermark_we;
+ logic intr_test_fmt_overflow_wd;
+ logic intr_test_fmt_overflow_we;
+ logic intr_test_rx_overflow_wd;
+ logic intr_test_rx_overflow_we;
+ logic intr_test_nak_wd;
+ logic intr_test_nak_we;
+ logic intr_test_scl_interference_wd;
+ logic intr_test_scl_interference_we;
+ logic intr_test_sda_interference_wd;
+ logic intr_test_sda_interference_we;
+ logic intr_test_stretch_timeout_wd;
+ logic intr_test_stretch_timeout_we;
+ logic intr_test_sda_unstable_wd;
+ logic intr_test_sda_unstable_we;
+ logic ctrl_qs;
+ logic ctrl_wd;
+ logic ctrl_we;
+ logic status_fmtfull_qs;
+ logic status_fmtfull_re;
+ logic status_rxfull_qs;
+ logic status_rxfull_re;
+ logic status_fmtempty_qs;
+ logic status_fmtempty_re;
+ logic status_hostidle_qs;
+ logic status_hostidle_re;
+ logic status_targetidle_qs;
+ logic status_targetidle_re;
+ logic status_rxempty_qs;
+ logic status_rxempty_re;
+ logic [7:0] rdata_qs;
+ logic rdata_re;
+ logic [7:0] fdata_fbyte_wd;
+ logic fdata_fbyte_we;
+ logic fdata_start_wd;
+ logic fdata_start_we;
+ logic fdata_stop_wd;
+ logic fdata_stop_we;
+ logic fdata_read_wd;
+ logic fdata_read_we;
+ logic fdata_rcont_wd;
+ logic fdata_rcont_we;
+ logic fdata_nakok_wd;
+ logic fdata_nakok_we;
+ logic fifo_ctrl_rxrst_wd;
+ logic fifo_ctrl_rxrst_we;
+ logic fifo_ctrl_fmtrst_wd;
+ logic fifo_ctrl_fmtrst_we;
+ logic [2:0] fifo_ctrl_rxilvl_qs;
+ logic [2:0] fifo_ctrl_rxilvl_wd;
+ logic fifo_ctrl_rxilvl_we;
+ logic [1:0] fifo_ctrl_fmtilvl_qs;
+ logic [1:0] fifo_ctrl_fmtilvl_wd;
+ logic fifo_ctrl_fmtilvl_we;
+ logic [5:0] fifo_status_fmtlvl_qs;
+ logic fifo_status_fmtlvl_re;
+ logic [5:0] fifo_status_rxlvl_qs;
+ logic fifo_status_rxlvl_re;
+ logic ovrd_txovrden_qs;
+ logic ovrd_txovrden_wd;
+ logic ovrd_txovrden_we;
+ logic ovrd_sclval_qs;
+ logic ovrd_sclval_wd;
+ logic ovrd_sclval_we;
+ logic ovrd_sdaval_qs;
+ logic ovrd_sdaval_wd;
+ logic ovrd_sdaval_we;
+ logic [15:0] val_scl_rx_qs;
+ logic val_scl_rx_re;
+ logic [15:0] val_sda_rx_qs;
+ logic val_sda_rx_re;
+ logic [15:0] timing0_thigh_qs;
+ logic [15:0] timing0_thigh_wd;
+ logic timing0_thigh_we;
+ logic [15:0] timing0_tlow_qs;
+ logic [15:0] timing0_tlow_wd;
+ logic timing0_tlow_we;
+ logic [15:0] timing1_t_r_qs;
+ logic [15:0] timing1_t_r_wd;
+ logic timing1_t_r_we;
+ logic [15:0] timing1_t_f_qs;
+ logic [15:0] timing1_t_f_wd;
+ logic timing1_t_f_we;
+ logic [15:0] timing2_tsu_sta_qs;
+ logic [15:0] timing2_tsu_sta_wd;
+ logic timing2_tsu_sta_we;
+ logic [15:0] timing2_thd_st_qs;
+ logic [15:0] timing2_thd_st_wd;
+ logic timing2_thd_st_we;
+ logic [15:0] timing3_tsu_dat_qs;
+ logic [15:0] timing3_tsu_dat_wd;
+ logic timing3_tsu_dat_we;
+ logic [15:0] timing3_thd_dat_qs;
+ logic [15:0] timing3_thd_dat_wd;
+ logic timing3_thd_dat_we;
+ logic [15:0] timing4_tsu_sto_qs;
+ logic [15:0] timing4_tsu_sto_wd;
+ logic timing4_tsu_sto_we;
+ logic [15:0] timing4_t_buf_qs;
+ logic [15:0] timing4_t_buf_wd;
+ logic timing4_t_buf_we;
+ logic [30:0] timeout_ctrl_val_qs;
+ logic [30:0] timeout_ctrl_val_wd;
+ logic timeout_ctrl_val_we;
+ logic timeout_ctrl_en_qs;
+ logic timeout_ctrl_en_wd;
+ logic timeout_ctrl_en_we;
+
+ // Register instances
+ // R[intr_state]: V(False)
+
+ // F[fmt_watermark]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_fmt_watermark (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_fmt_watermark_we),
+ .wd (intr_state_fmt_watermark_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.fmt_watermark.de),
+ .d (hw2reg.intr_state.fmt_watermark.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.fmt_watermark.q ),
+
+ // to register interface (read)
+ .qs (intr_state_fmt_watermark_qs)
+ );
+
+
+ // F[rx_watermark]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_rx_watermark (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_rx_watermark_we),
+ .wd (intr_state_rx_watermark_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.rx_watermark.de),
+ .d (hw2reg.intr_state.rx_watermark.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.rx_watermark.q ),
+
+ // to register interface (read)
+ .qs (intr_state_rx_watermark_qs)
+ );
+
+
+ // F[fmt_overflow]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_fmt_overflow (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_fmt_overflow_we),
+ .wd (intr_state_fmt_overflow_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.fmt_overflow.de),
+ .d (hw2reg.intr_state.fmt_overflow.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.fmt_overflow.q ),
+
+ // to register interface (read)
+ .qs (intr_state_fmt_overflow_qs)
+ );
+
+
+ // F[rx_overflow]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_rx_overflow (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_rx_overflow_we),
+ .wd (intr_state_rx_overflow_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.rx_overflow.de),
+ .d (hw2reg.intr_state.rx_overflow.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.rx_overflow.q ),
+
+ // to register interface (read)
+ .qs (intr_state_rx_overflow_qs)
+ );
+
+
+ // F[nak]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_nak (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_nak_we),
+ .wd (intr_state_nak_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.nak.de),
+ .d (hw2reg.intr_state.nak.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.nak.q ),
+
+ // to register interface (read)
+ .qs (intr_state_nak_qs)
+ );
+
+
+ // F[scl_interference]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_scl_interference (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_scl_interference_we),
+ .wd (intr_state_scl_interference_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.scl_interference.de),
+ .d (hw2reg.intr_state.scl_interference.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.scl_interference.q ),
+
+ // to register interface (read)
+ .qs (intr_state_scl_interference_qs)
+ );
+
+
+ // F[sda_interference]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_sda_interference (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_sda_interference_we),
+ .wd (intr_state_sda_interference_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.sda_interference.de),
+ .d (hw2reg.intr_state.sda_interference.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.sda_interference.q ),
+
+ // to register interface (read)
+ .qs (intr_state_sda_interference_qs)
+ );
+
+
+ // F[stretch_timeout]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_stretch_timeout (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_stretch_timeout_we),
+ .wd (intr_state_stretch_timeout_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.stretch_timeout.de),
+ .d (hw2reg.intr_state.stretch_timeout.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.stretch_timeout.q ),
+
+ // to register interface (read)
+ .qs (intr_state_stretch_timeout_qs)
+ );
+
+
+ // F[sda_unstable]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_sda_unstable (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_sda_unstable_we),
+ .wd (intr_state_sda_unstable_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.sda_unstable.de),
+ .d (hw2reg.intr_state.sda_unstable.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.sda_unstable.q ),
+
+ // to register interface (read)
+ .qs (intr_state_sda_unstable_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+
+ // F[fmt_watermark]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_fmt_watermark (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_fmt_watermark_we),
+ .wd (intr_enable_fmt_watermark_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.fmt_watermark.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_fmt_watermark_qs)
+ );
+
+
+ // F[rx_watermark]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_rx_watermark (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_rx_watermark_we),
+ .wd (intr_enable_rx_watermark_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.rx_watermark.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_rx_watermark_qs)
+ );
+
+
+ // F[fmt_overflow]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_fmt_overflow (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_fmt_overflow_we),
+ .wd (intr_enable_fmt_overflow_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.fmt_overflow.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_fmt_overflow_qs)
+ );
+
+
+ // F[rx_overflow]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_rx_overflow (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_rx_overflow_we),
+ .wd (intr_enable_rx_overflow_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.rx_overflow.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_rx_overflow_qs)
+ );
+
+
+ // F[nak]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_nak (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_nak_we),
+ .wd (intr_enable_nak_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.nak.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_nak_qs)
+ );
+
+
+ // F[scl_interference]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_scl_interference (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_scl_interference_we),
+ .wd (intr_enable_scl_interference_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.scl_interference.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_scl_interference_qs)
+ );
+
+
+ // F[sda_interference]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_sda_interference (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_sda_interference_we),
+ .wd (intr_enable_sda_interference_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.sda_interference.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_sda_interference_qs)
+ );
+
+
+ // F[stretch_timeout]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_stretch_timeout (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_stretch_timeout_we),
+ .wd (intr_enable_stretch_timeout_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.stretch_timeout.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_stretch_timeout_qs)
+ );
+
+
+ // F[sda_unstable]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_sda_unstable (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_sda_unstable_we),
+ .wd (intr_enable_sda_unstable_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.sda_unstable.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_sda_unstable_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+
+ // F[fmt_watermark]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_fmt_watermark (
+ .re (1'b0),
+ .we (intr_test_fmt_watermark_we),
+ .wd (intr_test_fmt_watermark_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.fmt_watermark.qe),
+ .q (reg2hw.intr_test.fmt_watermark.q ),
+ .qs ()
+ );
+
+
+ // F[rx_watermark]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_rx_watermark (
+ .re (1'b0),
+ .we (intr_test_rx_watermark_we),
+ .wd (intr_test_rx_watermark_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.rx_watermark.qe),
+ .q (reg2hw.intr_test.rx_watermark.q ),
+ .qs ()
+ );
+
+
+ // F[fmt_overflow]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_fmt_overflow (
+ .re (1'b0),
+ .we (intr_test_fmt_overflow_we),
+ .wd (intr_test_fmt_overflow_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.fmt_overflow.qe),
+ .q (reg2hw.intr_test.fmt_overflow.q ),
+ .qs ()
+ );
+
+
+ // F[rx_overflow]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_rx_overflow (
+ .re (1'b0),
+ .we (intr_test_rx_overflow_we),
+ .wd (intr_test_rx_overflow_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.rx_overflow.qe),
+ .q (reg2hw.intr_test.rx_overflow.q ),
+ .qs ()
+ );
+
+
+ // F[nak]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_nak (
+ .re (1'b0),
+ .we (intr_test_nak_we),
+ .wd (intr_test_nak_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.nak.qe),
+ .q (reg2hw.intr_test.nak.q ),
+ .qs ()
+ );
+
+
+ // F[scl_interference]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_scl_interference (
+ .re (1'b0),
+ .we (intr_test_scl_interference_we),
+ .wd (intr_test_scl_interference_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.scl_interference.qe),
+ .q (reg2hw.intr_test.scl_interference.q ),
+ .qs ()
+ );
+
+
+ // F[sda_interference]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_sda_interference (
+ .re (1'b0),
+ .we (intr_test_sda_interference_we),
+ .wd (intr_test_sda_interference_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.sda_interference.qe),
+ .q (reg2hw.intr_test.sda_interference.q ),
+ .qs ()
+ );
+
+
+ // F[stretch_timeout]: 7:7
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_stretch_timeout (
+ .re (1'b0),
+ .we (intr_test_stretch_timeout_we),
+ .wd (intr_test_stretch_timeout_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.stretch_timeout.qe),
+ .q (reg2hw.intr_test.stretch_timeout.q ),
+ .qs ()
+ );
+
+
+ // F[sda_unstable]: 8:8
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_sda_unstable (
+ .re (1'b0),
+ .we (intr_test_sda_unstable_we),
+ .wd (intr_test_sda_unstable_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.sda_unstable.qe),
+ .q (reg2hw.intr_test.sda_unstable.q ),
+ .qs ()
+ );
+
+
+ // R[ctrl]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ctrl (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ctrl_we),
+ .wd (ctrl_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ctrl.q ),
+
+ // to register interface (read)
+ .qs (ctrl_qs)
+ );
+
+
+ // R[status]: V(True)
+
+ // F[fmtfull]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_fmtfull (
+ .re (status_fmtfull_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fmtfull.d),
+ .qre (reg2hw.status.fmtfull.re),
+ .qe (),
+ .q (reg2hw.status.fmtfull.q ),
+ .qs (status_fmtfull_qs)
+ );
+
+
+ // F[rxfull]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_rxfull (
+ .re (status_rxfull_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.rxfull.d),
+ .qre (reg2hw.status.rxfull.re),
+ .qe (),
+ .q (reg2hw.status.rxfull.q ),
+ .qs (status_rxfull_qs)
+ );
+
+
+ // F[fmtempty]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_fmtempty (
+ .re (status_fmtempty_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fmtempty.d),
+ .qre (reg2hw.status.fmtempty.re),
+ .qe (),
+ .q (reg2hw.status.fmtempty.q ),
+ .qs (status_fmtempty_qs)
+ );
+
+
+ // F[hostidle]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_hostidle (
+ .re (status_hostidle_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.hostidle.d),
+ .qre (reg2hw.status.hostidle.re),
+ .qe (),
+ .q (reg2hw.status.hostidle.q ),
+ .qs (status_hostidle_qs)
+ );
+
+
+ // F[targetidle]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_targetidle (
+ .re (status_targetidle_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.targetidle.d),
+ .qre (reg2hw.status.targetidle.re),
+ .qe (),
+ .q (reg2hw.status.targetidle.q ),
+ .qs (status_targetidle_qs)
+ );
+
+
+ // F[rxempty]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_rxempty (
+ .re (status_rxempty_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.rxempty.d),
+ .qre (reg2hw.status.rxempty.re),
+ .qe (),
+ .q (reg2hw.status.rxempty.q ),
+ .qs (status_rxempty_qs)
+ );
+
+
+ // R[rdata]: V(True)
+
+ prim_subreg_ext #(
+ .DW (8)
+ ) u_rdata (
+ .re (rdata_re),
+ .we (1'b0),
+ .wd ('0),
+ .d ('0),
+ .qre (reg2hw.rdata.re),
+ .qe (),
+ .q (reg2hw.rdata.q ),
+ .qs (rdata_qs)
+ );
+
+
+ // R[fdata]: V(False)
+
+ // F[fbyte]: 7:0
+ prim_subreg #(
+ .DW (8),
+ .SWACCESS("WO"),
+ .RESVAL (8'h0)
+ ) u_fdata_fbyte (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fdata_fbyte_we),
+ .wd (fdata_fbyte_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fdata.fbyte.qe),
+ .q (reg2hw.fdata.fbyte.q ),
+
+ .qs ()
+ );
+
+
+ // F[start]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_fdata_start (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fdata_start_we),
+ .wd (fdata_start_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fdata.start.qe),
+ .q (reg2hw.fdata.start.q ),
+
+ .qs ()
+ );
+
+
+ // F[stop]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_fdata_stop (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fdata_stop_we),
+ .wd (fdata_stop_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fdata.stop.qe),
+ .q (reg2hw.fdata.stop.q ),
+
+ .qs ()
+ );
+
+
+ // F[read]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_fdata_read (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fdata_read_we),
+ .wd (fdata_read_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fdata.read.qe),
+ .q (reg2hw.fdata.read.q ),
+
+ .qs ()
+ );
+
+
+ // F[rcont]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_fdata_rcont (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fdata_rcont_we),
+ .wd (fdata_rcont_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fdata.rcont.qe),
+ .q (reg2hw.fdata.rcont.q ),
+
+ .qs ()
+ );
+
+
+ // F[nakok]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_fdata_nakok (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fdata_nakok_we),
+ .wd (fdata_nakok_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fdata.nakok.qe),
+ .q (reg2hw.fdata.nakok.q ),
+
+ .qs ()
+ );
+
+
+ // R[fifo_ctrl]: V(False)
+
+ // F[rxrst]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_fifo_ctrl_rxrst (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fifo_ctrl_rxrst_we),
+ .wd (fifo_ctrl_rxrst_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fifo_ctrl.rxrst.qe),
+ .q (reg2hw.fifo_ctrl.rxrst.q ),
+
+ .qs ()
+ );
+
+
+ // F[fmtrst]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_fifo_ctrl_fmtrst (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fifo_ctrl_fmtrst_we),
+ .wd (fifo_ctrl_fmtrst_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fifo_ctrl.fmtrst.qe),
+ .q (reg2hw.fifo_ctrl.fmtrst.q ),
+
+ .qs ()
+ );
+
+
+ // F[rxilvl]: 4:2
+ prim_subreg #(
+ .DW (3),
+ .SWACCESS("RW"),
+ .RESVAL (3'h0)
+ ) u_fifo_ctrl_rxilvl (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fifo_ctrl_rxilvl_we),
+ .wd (fifo_ctrl_rxilvl_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fifo_ctrl.rxilvl.qe),
+ .q (reg2hw.fifo_ctrl.rxilvl.q ),
+
+ // to register interface (read)
+ .qs (fifo_ctrl_rxilvl_qs)
+ );
+
+
+ // F[fmtilvl]: 6:5
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_fifo_ctrl_fmtilvl (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fifo_ctrl_fmtilvl_we),
+ .wd (fifo_ctrl_fmtilvl_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fifo_ctrl.fmtilvl.qe),
+ .q (reg2hw.fifo_ctrl.fmtilvl.q ),
+
+ // to register interface (read)
+ .qs (fifo_ctrl_fmtilvl_qs)
+ );
+
+
+ // R[fifo_status]: V(True)
+
+ // F[fmtlvl]: 5:0
+ prim_subreg_ext #(
+ .DW (6)
+ ) u_fifo_status_fmtlvl (
+ .re (fifo_status_fmtlvl_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.fifo_status.fmtlvl.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (fifo_status_fmtlvl_qs)
+ );
+
+
+ // F[rxlvl]: 21:16
+ prim_subreg_ext #(
+ .DW (6)
+ ) u_fifo_status_rxlvl (
+ .re (fifo_status_rxlvl_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.fifo_status.rxlvl.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (fifo_status_rxlvl_qs)
+ );
+
+
+ // R[ovrd]: V(False)
+
+ // F[txovrden]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ovrd_txovrden (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ovrd_txovrden_we),
+ .wd (ovrd_txovrden_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ovrd.txovrden.q ),
+
+ // to register interface (read)
+ .qs (ovrd_txovrden_qs)
+ );
+
+
+ // F[sclval]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ovrd_sclval (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ovrd_sclval_we),
+ .wd (ovrd_sclval_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ovrd.sclval.q ),
+
+ // to register interface (read)
+ .qs (ovrd_sclval_qs)
+ );
+
+
+ // F[sdaval]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ovrd_sdaval (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ovrd_sdaval_we),
+ .wd (ovrd_sdaval_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ovrd.sdaval.q ),
+
+ // to register interface (read)
+ .qs (ovrd_sdaval_qs)
+ );
+
+
+ // R[val]: V(True)
+
+ // F[scl_rx]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_val_scl_rx (
+ .re (val_scl_rx_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.val.scl_rx.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (val_scl_rx_qs)
+ );
+
+
+ // F[sda_rx]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_val_sda_rx (
+ .re (val_sda_rx_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.val.sda_rx.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (val_sda_rx_qs)
+ );
+
+
+ // R[timing0]: V(False)
+
+ // F[thigh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing0_thigh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing0_thigh_we),
+ .wd (timing0_thigh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing0.thigh.q ),
+
+ // to register interface (read)
+ .qs (timing0_thigh_qs)
+ );
+
+
+ // F[tlow]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing0_tlow (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing0_tlow_we),
+ .wd (timing0_tlow_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing0.tlow.q ),
+
+ // to register interface (read)
+ .qs (timing0_tlow_qs)
+ );
+
+
+ // R[timing1]: V(False)
+
+ // F[t_r]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing1_t_r (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing1_t_r_we),
+ .wd (timing1_t_r_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing1.t_r.q ),
+
+ // to register interface (read)
+ .qs (timing1_t_r_qs)
+ );
+
+
+ // F[t_f]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing1_t_f (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing1_t_f_we),
+ .wd (timing1_t_f_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing1.t_f.q ),
+
+ // to register interface (read)
+ .qs (timing1_t_f_qs)
+ );
+
+
+ // R[timing2]: V(False)
+
+ // F[tsu_sta]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing2_tsu_sta (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing2_tsu_sta_we),
+ .wd (timing2_tsu_sta_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing2.tsu_sta.q ),
+
+ // to register interface (read)
+ .qs (timing2_tsu_sta_qs)
+ );
+
+
+ // F[thd_st]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing2_thd_st (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing2_thd_st_we),
+ .wd (timing2_thd_st_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing2.thd_st.q ),
+
+ // to register interface (read)
+ .qs (timing2_thd_st_qs)
+ );
+
+
+ // R[timing3]: V(False)
+
+ // F[tsu_dat]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing3_tsu_dat (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing3_tsu_dat_we),
+ .wd (timing3_tsu_dat_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing3.tsu_dat.q ),
+
+ // to register interface (read)
+ .qs (timing3_tsu_dat_qs)
+ );
+
+
+ // F[thd_dat]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing3_thd_dat (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing3_thd_dat_we),
+ .wd (timing3_thd_dat_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing3.thd_dat.q ),
+
+ // to register interface (read)
+ .qs (timing3_thd_dat_qs)
+ );
+
+
+ // R[timing4]: V(False)
+
+ // F[tsu_sto]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing4_tsu_sto (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing4_tsu_sto_we),
+ .wd (timing4_tsu_sto_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing4.tsu_sto.q ),
+
+ // to register interface (read)
+ .qs (timing4_tsu_sto_qs)
+ );
+
+
+ // F[t_buf]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_timing4_t_buf (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timing4_t_buf_we),
+ .wd (timing4_t_buf_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timing4.t_buf.q ),
+
+ // to register interface (read)
+ .qs (timing4_t_buf_qs)
+ );
+
+
+ // R[timeout_ctrl]: V(False)
+
+ // F[val]: 30:0
+ prim_subreg #(
+ .DW (31),
+ .SWACCESS("RW"),
+ .RESVAL (31'h0)
+ ) u_timeout_ctrl_val (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timeout_ctrl_val_we),
+ .wd (timeout_ctrl_val_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timeout_ctrl.val.q ),
+
+ // to register interface (read)
+ .qs (timeout_ctrl_val_qs)
+ );
+
+
+ // F[en]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_timeout_ctrl_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (timeout_ctrl_en_we),
+ .wd (timeout_ctrl_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.timeout_ctrl.en.q ),
+
+ // to register interface (read)
+ .qs (timeout_ctrl_en_qs)
+ );
+
+
+
+ logic [16:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == I2C_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == I2C_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == I2C_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == I2C_CTRL_OFFSET);
+ addr_hit[ 4] = (reg_addr == I2C_STATUS_OFFSET);
+ addr_hit[ 5] = (reg_addr == I2C_RDATA_OFFSET);
+ addr_hit[ 6] = (reg_addr == I2C_FDATA_OFFSET);
+ addr_hit[ 7] = (reg_addr == I2C_FIFO_CTRL_OFFSET);
+ addr_hit[ 8] = (reg_addr == I2C_FIFO_STATUS_OFFSET);
+ addr_hit[ 9] = (reg_addr == I2C_OVRD_OFFSET);
+ addr_hit[10] = (reg_addr == I2C_VAL_OFFSET);
+ addr_hit[11] = (reg_addr == I2C_TIMING0_OFFSET);
+ addr_hit[12] = (reg_addr == I2C_TIMING1_OFFSET);
+ addr_hit[13] = (reg_addr == I2C_TIMING2_OFFSET);
+ addr_hit[14] = (reg_addr == I2C_TIMING3_OFFSET);
+ addr_hit[15] = (reg_addr == I2C_TIMING4_OFFSET);
+ addr_hit[16] = (reg_addr == I2C_TIMEOUT_CTRL_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (I2C_PERMIT[ 0] != (I2C_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (I2C_PERMIT[ 1] != (I2C_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (I2C_PERMIT[ 2] != (I2C_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (I2C_PERMIT[ 3] != (I2C_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (I2C_PERMIT[ 4] != (I2C_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (I2C_PERMIT[ 5] != (I2C_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (I2C_PERMIT[ 6] != (I2C_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (I2C_PERMIT[ 7] != (I2C_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (I2C_PERMIT[ 8] != (I2C_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (I2C_PERMIT[ 9] != (I2C_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (I2C_PERMIT[10] != (I2C_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (I2C_PERMIT[11] != (I2C_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[12] && reg_we && (I2C_PERMIT[12] != (I2C_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[13] && reg_we && (I2C_PERMIT[13] != (I2C_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (I2C_PERMIT[14] != (I2C_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[15] && reg_we && (I2C_PERMIT[15] != (I2C_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[16] && reg_we && (I2C_PERMIT[16] != (I2C_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+ end
+
+ assign intr_state_fmt_watermark_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_fmt_watermark_wd = reg_wdata[0];
+
+ assign intr_state_rx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_rx_watermark_wd = reg_wdata[1];
+
+ assign intr_state_fmt_overflow_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_fmt_overflow_wd = reg_wdata[2];
+
+ assign intr_state_rx_overflow_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_rx_overflow_wd = reg_wdata[3];
+
+ assign intr_state_nak_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_nak_wd = reg_wdata[4];
+
+ assign intr_state_scl_interference_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_scl_interference_wd = reg_wdata[5];
+
+ assign intr_state_sda_interference_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_sda_interference_wd = reg_wdata[6];
+
+ assign intr_state_stretch_timeout_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_stretch_timeout_wd = reg_wdata[7];
+
+ assign intr_state_sda_unstable_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_sda_unstable_wd = reg_wdata[8];
+
+ assign intr_enable_fmt_watermark_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_fmt_watermark_wd = reg_wdata[0];
+
+ assign intr_enable_rx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_rx_watermark_wd = reg_wdata[1];
+
+ assign intr_enable_fmt_overflow_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_fmt_overflow_wd = reg_wdata[2];
+
+ assign intr_enable_rx_overflow_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_rx_overflow_wd = reg_wdata[3];
+
+ assign intr_enable_nak_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_nak_wd = reg_wdata[4];
+
+ assign intr_enable_scl_interference_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_scl_interference_wd = reg_wdata[5];
+
+ assign intr_enable_sda_interference_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_sda_interference_wd = reg_wdata[6];
+
+ assign intr_enable_stretch_timeout_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_stretch_timeout_wd = reg_wdata[7];
+
+ assign intr_enable_sda_unstable_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_sda_unstable_wd = reg_wdata[8];
+
+ assign intr_test_fmt_watermark_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_fmt_watermark_wd = reg_wdata[0];
+
+ assign intr_test_rx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_rx_watermark_wd = reg_wdata[1];
+
+ assign intr_test_fmt_overflow_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_fmt_overflow_wd = reg_wdata[2];
+
+ assign intr_test_rx_overflow_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_rx_overflow_wd = reg_wdata[3];
+
+ assign intr_test_nak_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_nak_wd = reg_wdata[4];
+
+ assign intr_test_scl_interference_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_scl_interference_wd = reg_wdata[5];
+
+ assign intr_test_sda_interference_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_sda_interference_wd = reg_wdata[6];
+
+ assign intr_test_stretch_timeout_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_stretch_timeout_wd = reg_wdata[7];
+
+ assign intr_test_sda_unstable_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_sda_unstable_wd = reg_wdata[8];
+
+ assign ctrl_we = addr_hit[3] & reg_we & ~wr_err;
+ assign ctrl_wd = reg_wdata[0];
+
+ assign status_fmtfull_re = addr_hit[4] && reg_re;
+
+ assign status_rxfull_re = addr_hit[4] && reg_re;
+
+ assign status_fmtempty_re = addr_hit[4] && reg_re;
+
+ assign status_hostidle_re = addr_hit[4] && reg_re;
+
+ assign status_targetidle_re = addr_hit[4] && reg_re;
+
+ assign status_rxempty_re = addr_hit[4] && reg_re;
+
+ assign rdata_re = addr_hit[5] && reg_re;
+
+ assign fdata_fbyte_we = addr_hit[6] & reg_we & ~wr_err;
+ assign fdata_fbyte_wd = reg_wdata[7:0];
+
+ assign fdata_start_we = addr_hit[6] & reg_we & ~wr_err;
+ assign fdata_start_wd = reg_wdata[8];
+
+ assign fdata_stop_we = addr_hit[6] & reg_we & ~wr_err;
+ assign fdata_stop_wd = reg_wdata[9];
+
+ assign fdata_read_we = addr_hit[6] & reg_we & ~wr_err;
+ assign fdata_read_wd = reg_wdata[10];
+
+ assign fdata_rcont_we = addr_hit[6] & reg_we & ~wr_err;
+ assign fdata_rcont_wd = reg_wdata[11];
+
+ assign fdata_nakok_we = addr_hit[6] & reg_we & ~wr_err;
+ assign fdata_nakok_wd = reg_wdata[12];
+
+ assign fifo_ctrl_rxrst_we = addr_hit[7] & reg_we & ~wr_err;
+ assign fifo_ctrl_rxrst_wd = reg_wdata[0];
+
+ assign fifo_ctrl_fmtrst_we = addr_hit[7] & reg_we & ~wr_err;
+ assign fifo_ctrl_fmtrst_wd = reg_wdata[1];
+
+ assign fifo_ctrl_rxilvl_we = addr_hit[7] & reg_we & ~wr_err;
+ assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
+
+ assign fifo_ctrl_fmtilvl_we = addr_hit[7] & reg_we & ~wr_err;
+ assign fifo_ctrl_fmtilvl_wd = reg_wdata[6:5];
+
+ assign fifo_status_fmtlvl_re = addr_hit[8] && reg_re;
+
+ assign fifo_status_rxlvl_re = addr_hit[8] && reg_re;
+
+ assign ovrd_txovrden_we = addr_hit[9] & reg_we & ~wr_err;
+ assign ovrd_txovrden_wd = reg_wdata[0];
+
+ assign ovrd_sclval_we = addr_hit[9] & reg_we & ~wr_err;
+ assign ovrd_sclval_wd = reg_wdata[1];
+
+ assign ovrd_sdaval_we = addr_hit[9] & reg_we & ~wr_err;
+ assign ovrd_sdaval_wd = reg_wdata[2];
+
+ assign val_scl_rx_re = addr_hit[10] && reg_re;
+
+ assign val_sda_rx_re = addr_hit[10] && reg_re;
+
+ assign timing0_thigh_we = addr_hit[11] & reg_we & ~wr_err;
+ assign timing0_thigh_wd = reg_wdata[15:0];
+
+ assign timing0_tlow_we = addr_hit[11] & reg_we & ~wr_err;
+ assign timing0_tlow_wd = reg_wdata[31:16];
+
+ assign timing1_t_r_we = addr_hit[12] & reg_we & ~wr_err;
+ assign timing1_t_r_wd = reg_wdata[15:0];
+
+ assign timing1_t_f_we = addr_hit[12] & reg_we & ~wr_err;
+ assign timing1_t_f_wd = reg_wdata[31:16];
+
+ assign timing2_tsu_sta_we = addr_hit[13] & reg_we & ~wr_err;
+ assign timing2_tsu_sta_wd = reg_wdata[15:0];
+
+ assign timing2_thd_st_we = addr_hit[13] & reg_we & ~wr_err;
+ assign timing2_thd_st_wd = reg_wdata[31:16];
+
+ assign timing3_tsu_dat_we = addr_hit[14] & reg_we & ~wr_err;
+ assign timing3_tsu_dat_wd = reg_wdata[15:0];
+
+ assign timing3_thd_dat_we = addr_hit[14] & reg_we & ~wr_err;
+ assign timing3_thd_dat_wd = reg_wdata[31:16];
+
+ assign timing4_tsu_sto_we = addr_hit[15] & reg_we & ~wr_err;
+ assign timing4_tsu_sto_wd = reg_wdata[15:0];
+
+ assign timing4_t_buf_we = addr_hit[15] & reg_we & ~wr_err;
+ assign timing4_t_buf_wd = reg_wdata[31:16];
+
+ assign timeout_ctrl_val_we = addr_hit[16] & reg_we & ~wr_err;
+ assign timeout_ctrl_val_wd = reg_wdata[30:0];
+
+ assign timeout_ctrl_en_we = addr_hit[16] & reg_we & ~wr_err;
+ assign timeout_ctrl_en_wd = reg_wdata[31];
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_fmt_watermark_qs;
+ reg_rdata_next[1] = intr_state_rx_watermark_qs;
+ reg_rdata_next[2] = intr_state_fmt_overflow_qs;
+ reg_rdata_next[3] = intr_state_rx_overflow_qs;
+ reg_rdata_next[4] = intr_state_nak_qs;
+ reg_rdata_next[5] = intr_state_scl_interference_qs;
+ reg_rdata_next[6] = intr_state_sda_interference_qs;
+ reg_rdata_next[7] = intr_state_stretch_timeout_qs;
+ reg_rdata_next[8] = intr_state_sda_unstable_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_fmt_watermark_qs;
+ reg_rdata_next[1] = intr_enable_rx_watermark_qs;
+ reg_rdata_next[2] = intr_enable_fmt_overflow_qs;
+ reg_rdata_next[3] = intr_enable_rx_overflow_qs;
+ reg_rdata_next[4] = intr_enable_nak_qs;
+ reg_rdata_next[5] = intr_enable_scl_interference_qs;
+ reg_rdata_next[6] = intr_enable_sda_interference_qs;
+ reg_rdata_next[7] = intr_enable_stretch_timeout_qs;
+ reg_rdata_next[8] = intr_enable_sda_unstable_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
+ reg_rdata_next[3] = '0;
+ reg_rdata_next[4] = '0;
+ reg_rdata_next[5] = '0;
+ reg_rdata_next[6] = '0;
+ reg_rdata_next[7] = '0;
+ reg_rdata_next[8] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = ctrl_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = status_fmtfull_qs;
+ reg_rdata_next[1] = status_rxfull_qs;
+ reg_rdata_next[2] = status_fmtempty_qs;
+ reg_rdata_next[3] = status_hostidle_qs;
+ reg_rdata_next[4] = status_targetidle_qs;
+ reg_rdata_next[5] = status_rxempty_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[7:0] = rdata_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[7:0] = '0;
+ reg_rdata_next[8] = '0;
+ reg_rdata_next[9] = '0;
+ reg_rdata_next[10] = '0;
+ reg_rdata_next[11] = '0;
+ reg_rdata_next[12] = '0;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs;
+ reg_rdata_next[6:5] = fifo_ctrl_fmtilvl_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[5:0] = fifo_status_fmtlvl_qs;
+ reg_rdata_next[21:16] = fifo_status_rxlvl_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[0] = ovrd_txovrden_qs;
+ reg_rdata_next[1] = ovrd_sclval_qs;
+ reg_rdata_next[2] = ovrd_sdaval_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[15:0] = val_scl_rx_qs;
+ reg_rdata_next[31:16] = val_sda_rx_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[15:0] = timing0_thigh_qs;
+ reg_rdata_next[31:16] = timing0_tlow_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[15:0] = timing1_t_r_qs;
+ reg_rdata_next[31:16] = timing1_t_f_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[15:0] = timing2_tsu_sta_qs;
+ reg_rdata_next[31:16] = timing2_thd_st_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[15:0] = timing3_tsu_dat_qs;
+ reg_rdata_next[31:16] = timing3_thd_dat_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[15:0] = timing4_tsu_sto_qs;
+ reg_rdata_next[31:16] = timing4_t_buf_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[30:0] = timeout_ctrl_val_qs;
+ reg_rdata_next[31] = timeout_ctrl_en_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ `ASSERT(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
+
+endmodule
