[entropy_src:dv] DV Plan, Testplan, sanity test updates/changes
Signed-off-by: Steve Nelson <steve.nelson@wdc.com>
diff --git a/hw/ip/entropy_src/data/entropy_src_testplan.hjson b/hw/ip/entropy_src/data/entropy_src_testplan.hjson
index 6005777..776f7df 100644
--- a/hw/ip/entropy_src/data/entropy_src_testplan.hjson
+++ b/hw/ip/entropy_src/data/entropy_src_testplan.hjson
@@ -9,24 +9,9 @@
entries: [
{
name: sanity
- desc: '''**Goal**: Basic sanity test acessing a major datapath in ENTROPY_SRC.
-
- **Stimulus**: Describe the stimulus procedure.
-
- **Checks**": Describe the self-check procedure.
- - add bullets as needed
- - second bullet<br>
- describe second bullet
-
- Start a new paragraph.'''
+ desc: '''Enable entropy_src. Verify entropy, status, interrupt bits.'''
milestone: V1
tests: ["entropy_src_sanity"]
}
- {
- name: feature1
- desc: '''Add more test entries here like above.'''
- milestone: V1
- tests: []
- }
]
}
diff --git a/hw/ip/entropy_src/doc/dv_plan/index.md b/hw/ip/entropy_src/doc/dv_plan/index.md
index 58ae965..1fece9e 100644
--- a/hw/ip/entropy_src/doc/dv_plan/index.md
+++ b/hw/ip/entropy_src/doc/dv_plan/index.md
@@ -37,14 +37,14 @@
* [dv_utils_pkg]({{< relref "hw/dv/sv/dv_utils/README.md" >}})
* [csr_utils_pkg]({{< relref "hw/dv/sv/csr_utils/README.md" >}})
-### Compile-time configurations
-[list compile time configurations, if any and what are they used for]
+<!--### Compile-time configurations
+TODO-->
### Global types & methods
All common types and methods defined at the package level can be found in
`entropy_src_env_pkg`. Some of them in use are:
+<!--TODO-->
```systemverilog
-[list a few parameters, types & methods; no need to mention all]
```
### TL_agent
@@ -65,20 +65,17 @@
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
* entropy_src_init: Initialize the ENTROPY_SRC module from the randomized environment variables in the config.
-* TODO, add more
#### Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model.
The following covergroups have been developed to prove that the test intent has been adequately met:
* common covergroup for interrupts `hw/dv/sv/cip_lib/cip_base_env_cov.sv`: Cover interrupt value, interrupt enable, intr_test, interrupt pin
-* TODO, add more
### Self-checking strategy
#### Scoreboard
The `entropy_src_scoreboard` is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
* tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of Tilelink address channel and data channel respectively
-* TODO, maybe entropy/noise
#### Assertions
* TLUL assertions: The `tb/entropy_src_bind.sv` binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}}) to the IP to ensure TileLink interface protocol compliance.
@@ -94,5 +91,4 @@
```
## Testplan
-<!-- TODO: uncomment the line below after adding the testplan
-{{</* testplan "hw/ip/entropy_src/data/entropy_src_testplan.hjson" */>}} -->
+{{< testplan "hw/ip/entropy_src/data/entropy_src_testplan.hjson" >}}
diff --git a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
index fbbdad7..18c3167 100644
--- a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
+++ b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
@@ -33,6 +33,7 @@
virtual task process_tl_access(tl_seq_item item, tl_channels_e channel = DataChannel);
uvm_reg csr;
+ // TODO Turned off do_read_check for polling, add prediction
bit do_read_check = 1'b1;
bit write = item.is_write();
uvm_reg_addr_t csr_addr = get_normalized_addr(item.a_addr);
@@ -58,26 +59,34 @@
// for read, update predication at address phase and compare at data phase
case (csr.get_name())
// add individual case item for each csr
+ "intr_state": begin
+ do_read_check = 1'b0;
+ end
+ "intr_enable": begin
+ end
+ "intr_test": begin
+ end
+ "es_regen": begin
+ end
"es_conf": begin
- if (write) begin
- `uvm_info(`gfn, $sformatf("Write to ES_CONF register"), UVM_DEBUG)
- end
- else begin
- `uvm_info(`gfn, $sformatf("Read from ES_CONF register"), UVM_DEBUG)
- end
end
"es_rev": begin
- if (!write) begin
- `uvm_info(`gfn, $sformatf("Read from ES_REV register"), UVM_DEBUG)
- end
end
- "intr_state": begin
- if (write) begin
- `uvm_info(`gfn, $sformatf("Write to INTR_STATE register"), UVM_DEBUG)
- end
- else begin
- `uvm_info(`gfn, $sformatf("Read from INTR_STATE register"), UVM_DEBUG)
- end
+ "es_entropy": begin
+ do_read_check = 1'b0;
+ end
+ "es_ctrl": begin
+ end
+ "es_status": begin
+ do_read_check = 1'b0;
+ end
+ "es_fdepthst": begin
+ end
+ "es_thresh": begin
+ end
+ "es_rate": begin
+ end
+ "es_seed": begin
end
default: begin
`uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name()))
diff --git a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_sanity_vseq.sv b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_sanity_vseq.sv
index e66fa81..5d65f9b 100644
--- a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_sanity_vseq.sv
+++ b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_sanity_vseq.sv
@@ -9,14 +9,32 @@
`uvm_object_new
task body();
- bit [TL_DW-1:0] rdata, es_conf;
+ bit [TL_DW-1:0] es_seed, rd_data;
- // initialize config register
- es_conf[0] = 1; // set master enable
+ // Get es_seed
+ csr_rd(.ptr(ral.es_seed), .value(es_seed));
-// csr_wr(.csr(ral.es_conf), .value(es_conf));
- csr_rd(.ptr(ral.es_rev), .value(rdata));
- `uvm_info(`gfn, $sformatf("chip_type = %0d, hw_rev = %0d, abi_rev = %0d", rdata[23:16], rdata[15:8], rdata[7:0]), UVM_NONE)
+ // Enable entropy_src
+ csr_wr(.csr(ral.es_conf), .value(1'b1));
+
+ // Wait for entropy_rdy
+ csr_spinwait(.ptr(ral.es_status.entropy_rdy), .exp_data(1));
+
+ // Wait for entropy_valid interrupt
+ csr_spinwait(.ptr(ral.intr_state.es_entropy_valid), .exp_data(1));
+
+ // Expect 1st entropy to be es_seed
+ csr_rd_check(.ptr(ral.es_entropy), .compare_value(es_seed));
+
+ // Disable entropy_src
+ csr_wr(.csr(ral.es_conf), .value(1'b0));
+
+ // Clear/Validate entropy_valid interrupt bit
+ csr_wr(.csr(ral.intr_state), .value(1'b1));
+
+ // Ensure entropy_valid interrupt bit cleared
+ csr_rd_check(.ptr(ral.intr_state), .compare_value(0));
+
endtask : body
endclass : entropy_src_sanity_vseq
diff --git a/util/build_docs.py b/util/build_docs.py
index 2b485ca..f24519e 100755
--- a/util/build_docs.py
+++ b/util/build_docs.py
@@ -75,6 +75,7 @@
"testplan_definitions": [
"hw/ip/aes/data/aes_testplan.hjson",
"hw/ip/alert_handler/data/alert_handler_testplan.hjson",
+ "hw/ip/entropy_src/data/entropy_src_testplan.hjson",
"hw/ip/gpio/data/gpio_testplan.hjson",
"hw/ip/hmac/data/hmac_testplan.hjson",
"hw/ip/i2c/data/i2c_testplan.hjson",
