[sdc] Correct the clock group constraint
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/syn/tools/dc/run-syn.tcl b/hw/syn/tools/dc/run-syn.tcl
index 26d8e60..fd02e47 100644
--- a/hw/syn/tools/dc/run-syn.tcl
+++ b/hw/syn/tools/dc/run-syn.tcl
@@ -142,10 +142,6 @@
## MAP DESIGN ##
######################
-# TODO: we may have to disable a couple of optimizations in order
-# to prevent the tool from optimizing away dummy logic or logic from blocks
-# that are only half-finished
-
# preserve hierarchy for reports
compile_ultra -gate_clock -scan -no_autoungroup > "${REPDIR}/compile.rpt"
diff --git a/hw/top_earlgrey/syn/asic.constraints.sdc b/hw/top_earlgrey/syn/asic.constraints.sdc
index f71d943..3f3a817 100644
--- a/hw/top_earlgrey/syn/asic.constraints.sdc
+++ b/hw/top_earlgrey/syn/asic.constraints.sdc
@@ -138,18 +138,6 @@
set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks JTAG_TCK]
#####################
-# RNG clock #
-#####################
-set RNG_CLK_PIN u_ast/u_rng/u_rng_osc/rng_clk_o
-# target is 100MHz, overconstrain by factor
-set RNG_TCK_TARGET_PERIOD 10
-set RNG_TCK_PERIOD [expr $RNG_TCK_TARGET_PERIOD*$CLK_PERIOD_FACTOR]
-
-create_clock -name RNG_CLK -period $RNG_TCK_PERIOD [get_pins $RNG_CLK_PIN]
-#set_ideal_network [get_ports $RNG_CLK_PIN]
-set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks RNG_CLK]
-
-#####################
# SPI DEV clock #
#####################
# strawman constraints. Device target freq is 48MHz. Using 62.5MHz to over-constraint
@@ -265,7 +253,6 @@
-group [get_clocks IO_CLK ] \
-group [get_clocks IO_DIV2_CLK ] \
-group [get_clocks IO_DIV4_CLK ] \
- -group [get_clocks RNG_CLK ] \
-group [get_clocks JTAG_TCK ] \
-group [get_clocks AON_CLK ]
