[ earlgrey ] Updating module memory map to better reflect future plans
Soon to be added modules should be added to the memory map in
their proper places. This update rearranges top_earlgrey to
better align with the plan laid out in the following
spreadsheet:
https://docs.google.com/spreadsheets/d/1ptfdrG5RWiYHKtjYyDO1ubGYPPlN_4YQfzRKO1G1Mls/edit#gid=0
Signed-off-by: Martin Lueker-Boden <martin.lueker-boden@wdc.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index f2fb35c..556e4b6 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -523,7 +523,7 @@
{
rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
- base_addr: 0x40010000
+ base_addr: 0x40040000
clock_reset_export: []
clock_connections:
{
@@ -592,7 +592,7 @@
{
rst_ni: rstmgr_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel]
}
- base_addr: 0x40020000
+ base_addr: 0x40050000
clock_reset_export: []
clock_connections:
{
@@ -727,202 +727,6 @@
]
}
{
- name: flash_ctrl
- type: flash_ctrl
- clock_srcs:
- {
- clk_i: main
- }
- clock_group: infra
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]
- }
- base_addr: 0x40030000
- generated: "true"
- clock_reset_export: []
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_main_infra
- }
- domain: "0"
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list:
- [
- {
- name: prog_empty
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: interrupt
- }
- {
- name: prog_lvl
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: interrupt
- }
- {
- name: rd_full
- width: 1
- bits: "2"
- bitinfo:
- [
- 4
- 1
- 2
- ]
- type: interrupt
- }
- {
- name: rd_lvl
- width: 1
- bits: "3"
- bitinfo:
- [
- 8
- 1
- 3
- ]
- type: interrupt
- }
- {
- name: op_done
- width: 1
- bits: "4"
- bitinfo:
- [
- 16
- 1
- 4
- ]
- type: interrupt
- }
- {
- name: op_error
- width: 1
- bits: "5"
- bitinfo:
- [
- 32
- 1
- 5
- ]
- type: interrupt
- }
- ]
- alert_list: []
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: flash
- type: req_rsp
- name: flash
- act: req
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- width: 1
- default: ""
- top_signame: flash_ctrl_flash
- index: -1
- }
- {
- struct: otp_flash
- type: uni
- name: otp
- act: rcv
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_provision_en
- act: rcv
- package: lc_ctrl_pkg
- inst_name: flash_ctrl
- index: -1
- }
- {
- struct: lc_flash
- type: req_rsp
- name: lc
- act: rsp
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- index: -1
- }
- {
- struct: edn_entropy
- type: uni
- name: edn
- act: rcv
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- index: -1
- }
- {
- struct: pwr_flash
- type: req_rsp
- name: pwrmgr
- act: rsp
- package: pwrmgr_pkg
- inst_name: flash_ctrl
- width: 1
- default: ""
- top_signame: pwrmgr_pwr_flash
- index: -1
- }
- {
- struct: keymgr_flash
- type: uni
- name: keymgr
- act: req
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- width: 1
- default: ""
- top_type: broadcast
- top_signame: flash_ctrl_keymgr
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: flash_ctrl
- width: 1
- default: ""
- top_signame: flash_ctrl_tl
- index: -1
- }
- ]
- }
- {
name: rv_timer
type: rv_timer
clock_srcs:
@@ -934,7 +738,7 @@
{
rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
- base_addr: 0x40080000
+ base_addr: 0x40100000
clock_reset_export: []
clock_connections:
{
@@ -978,139 +782,40 @@
]
}
{
- name: aes
- type: aes
+ name: sensor_ctrl
+ type: sensor_ctrl
clock_srcs:
{
- clk_i: main
+ clk_i: io_div4
}
- clock_group: trans
+ clock_group: secure
+ clock_reset_export:
+ [
+ ast
+ ]
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
}
+ domain: Aon
base_addr: 0x40110000
- clock_reset_export: []
+ top_only: "true"
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_aes
+ clk_i: clkmgr_clocks.clk_io_div4_secure
}
- domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
- param_list:
- [
- {
- name: AES192Enable
- type: bit
- default: 1'b1
- desc: Disable (0) or enable (1) support for 192-bit key lengths (AES-192).
- local: "false"
- expose: "false"
- randcount: "0"
- randtype: none
- name_top: AesAES192Enable
- }
- {
- name: Masking
- type: bit
- default: 1'b1
- desc:
- '''
- Disable (0) or enable (1) first-order masking of the AES cipher core.
- Masking requires the use of a masked S-Box, see SBoxImpl parameter.
- '''
- local: "false"
- expose: "true"
- randcount: "0"
- randtype: none
- name_top: AesMasking
- }
- {
- name: SBoxImpl
- type: aes_pkg::sbox_impl_e
- default: aes_pkg::SBoxImplCanrightMasked
- desc: Selection of the S-Box implementation. See aes_pkg.sv.
- local: "false"
- expose: "true"
- randcount: "0"
- randtype: none
- name_top: AesSBoxImpl
- }
- {
- name: SecStartTriggerDelay
- type: int unsigned
- default: "0"
- desc:
- '''
- Manual start trigger delay, useful for SCA measurements.
- A value of e.g. 40 allows the processor to go into sleep before AES starts operation.
- '''
- local: "false"
- expose: "true"
- randcount: "0"
- randtype: none
- name_top: SecAesStartTriggerDelay
- }
- {
- name: SecAllowForcingMasks
- type: bit
- default: 1'b0
- desc:
- '''
- Forbid (0) or allow (1) forcing the mask to zero via FORCE_ZERO_MASK bit in the Control Register.
- Useful for SCA measurements.
- Meaningful only if masking is enabled.
- '''
- local: "false"
- expose: "true"
- randcount: "0"
- randtype: none
- name_top: SecAesAllowForcingMasks
- }
- {
- name: SeedClearing
- type: logic [aes_pkg::WidthPRDClearing-1:0]
- default: aes_pkg::DefaultSeedClearing
- desc: Default seed of the PRNG used for register clearing.
- local: "false"
- expose: "false"
- randcount: "0"
- randtype: none
- name_top: AesSeedClearing
- }
- {
- name: SeedMasking
- type: logic [aes_pkg::WidthPRDMasking-1:0]
- default: aes_pkg::DefaultSeedMasking
- desc: Default seed of the PRNG used for masking.
- local: "false"
- expose: "false"
- randcount: "0"
- randtype: none
- name_top: AesSeedMasking
- }
- {
- name: AlertAsyncOn
- type: logic [aes_reg_pkg::NumAlerts-1:0]
- default: "{aes_reg_pkg::NumAlerts{1'b1}}"
- desc: One bit per alert specifying whether the corresponding sender in the AES module and the receiver in the alert handler are in the same clock domain (0) or whether there is an asynchronous boundary in between (1).
- local: "false"
- expose: "false"
- randcount: "0"
- randtype: none
- name_top: AesAlertAsyncOn
- }
- ]
+ param_list: []
interrupt_list: []
alert_list:
[
{
- name: ctrl_err_update
+ name: as
width: 1
bits: "0"
bitinfo:
@@ -1120,10 +825,10 @@
0
]
type: alert
- async: 0
+ async: 1
}
{
- name: ctrl_err_storage
+ name: cg
width: 1
bits: "1"
bitinfo:
@@ -1133,95 +838,10 @@
1
]
type: alert
- async: 0
- }
- ]
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- name: idle
- type: uni
- act: req
- package: ""
- struct: logic
- width: 1
- inst_name: aes
- default: ""
- top_signame: clkmgr_idle
- index: 0
+ async: 1
}
{
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: aes
- width: 1
- default: ""
- top_signame: aes_tl
- index: -1
- }
- ]
- }
- {
- name: hmac
- type: hmac
- clock_srcs:
- {
- clk_i: main
- }
- clock_group: trans
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
- }
- base_addr: 0x40120000
- clock_reset_export: []
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_main_hmac
- }
- domain: "0"
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list:
- [
- {
- name: hmac_done
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: interrupt
- }
- {
- name: fifo_empty
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: interrupt
- }
- {
- name: hmac_err
+ name: gd
width: 1
bits: "2"
bitinfo:
@@ -1230,145 +850,62 @@
1
2
]
- type: interrupt
+ type: alert
+ async: 1
}
- ]
- alert_list: []
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
{
- name: idle
- type: uni
- act: req
- package: ""
- struct: logic
+ name: ts_hi
width: 1
- inst_name: hmac
- default: ""
- top_signame: clkmgr_idle
- index: 1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: hmac
- width: 1
- default: ""
- top_signame: hmac_tl
- index: -1
- }
- ]
- }
- {
- name: kmac
- type: kmac
- clock_srcs:
- {
- clk_i: main
- }
- clock_group: trans
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
- }
- base_addr: 0x41120000
- clock_reset_export: []
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_main_kmac
- }
- domain: "0"
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list:
- [
- {
- name: EnMasking
- type: int
- default: "0"
- desc:
- '''
- Disable(0) or enable(1) first-order masking of Keccak round.
-
- If masking is enabled, ReuseShare parameter will impact the design.
- '''
- local: "false"
- expose: "true"
- randcount: "0"
- randtype: none
- name_top: KmacEnMasking
- }
- {
- name: ReuseShare
- type: int
- default: "0"
- desc:
- '''
- If enabled (1), the internal Keccak round logic will re-use the
- adjacent shares as entropy in Domain-Oriented Masking AND logic.
- It improves the throughput of Keccak, as it only requires small
- amount of entropy rather than 1600 bit per round.
-
- This feature is not implemented yet.
- '''
- local: "false"
- expose: "true"
- randcount: "0"
- randtype: none
- name_top: KmacReuseShare
- }
- ]
- interrupt_list:
- [
- {
- name: kmac_done
- width: 1
- bits: "0"
+ bits: "3"
bitinfo:
[
+ 8
1
- 1
- 0
+ 3
]
- type: interrupt
+ type: alert
+ async: 1
}
{
- name: fifo_empty
+ name: ts_lo
width: 1
- bits: "1"
+ bits: "4"
bitinfo:
[
- 2
+ 16
1
- 1
- ]
- type: interrupt
- }
- {
- name: kmac_err
- width: 1
- bits: "2"
- bitinfo:
- [
4
- 1
- 2
]
- type: interrupt
+ type: alert
+ async: 1
+ }
+ {
+ name: ls
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: alert
+ async: 1
+ }
+ {
+ name: ot
+ width: 1
+ bits: "6"
+ bitinfo:
+ [
+ 64
+ 1
+ 6
+ ]
+ type: alert
+ async: 1
}
]
- alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
@@ -1376,40 +913,30 @@
inter_signal_list:
[
{
- struct: hw_key_req
- type: uni
- name: keymgr_key
- act: rcv
- package: keymgr_pkg
- inst_name: kmac
- width: 1
- default: ""
- top_signame: keymgr_kmac_key
- index: -1
- }
- {
- struct: kmac_data
+ struct: ast_alert
type: req_rsp
- name: keymgr_kdf
+ name: ast_alert
act: rsp
- package: keymgr_pkg
- inst_name: kmac
+ package: ast_wrapper_pkg
+ inst_name: sensor_ctrl
width: 1
default: ""
- top_signame: keymgr_kmac_data
+ external: true
+ top_signame: sensor_ctrl_ast_alert
index: -1
}
{
- name: idle
+ struct: ast_status
type: uni
- act: req
- package: ""
- struct: logic
+ name: ast_status
+ act: rcv
+ package: ast_wrapper_pkg
+ inst_name: sensor_ctrl
width: 1
- inst_name: kmac
default: ""
- top_signame: clkmgr_idle
- index: 2
+ external: true
+ top_signame: sensor_ctrl_ast_status
+ index: -1
}
{
struct: tl
@@ -1417,251 +944,34 @@
type: req_rsp
act: rsp
name: tl
- inst_name: kmac
+ inst_name: sensor_ctrl
width: 1
default: ""
- top_signame: kmac_tl
+ top_signame: sensor_ctrl_tl
index: -1
}
]
}
{
- name: rv_plic
- type: rv_plic
+ name: otp_ctrl
+ type: otp_ctrl
clock_srcs:
{
- clk_i: main
+ clk_i: io_div4
}
- clock_group: secure
+ clock_group: timers
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
- base_addr: 0x40090000
- generated: "true"
+ base_addr: 0x40130000
clock_reset_export: []
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_secure
+ clk_i: clkmgr_clocks.clk_io_div4_timers
}
domain: "0"
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list: []
- alert_list: []
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: rv_plic
- width: 1
- default: ""
- top_signame: rv_plic_tl
- index: -1
- }
- ]
- }
- {
- name: pinmux
- type: pinmux
- clock: main
- clock_srcs:
- {
- clk_i: main
- clk_aon_i: aon
- }
- clock_group: secure
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]
- rst_aon_ni: rstmgr_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel]
- }
- domain: Aon
- base_addr: 0x40070000
- generated: "true"
- clock_reset_export: []
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_main_secure
- clk_aon_i: clkmgr_clocks.clk_aon_secure
- }
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list: []
- alert_list: []
- wakeup_list:
- [
- {
- name: aon_wkup_req
- width: "1"
- }
- ]
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: lc_strap
- type: req_rsp
- name: lc_pinmux_strap
- act: rsp
- package: pinmux_pkg
- default: "'0"
- inst_name: pinmux
- index: -1
- }
- {
- struct: dft_strap_test
- type: uni
- name: dft_strap_test
- act: req
- package: pinmux_pkg
- default: "'0"
- inst_name: pinmux
- index: -1
- }
- {
- struct: io_pok
- type: uni
- name: io_pok
- act: rcv
- package: pinmux_pkg
- default: "{pinmux_pkg::NIOPokSignals{1'b1}}"
- inst_name: pinmux
- index: -1
- }
- {
- struct: logic
- type: uni
- name: sleep_en
- act: rcv
- package: ""
- default: 1'b0
- inst_name: pinmux
- index: -1
- }
- {
- struct: logic
- type: uni
- name: aon_wkup_req
- act: req
- package: ""
- default: 1'b0
- inst_name: pinmux
- width: 1
- top_signame: pwrmgr_wakeups
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: pinmux
- width: 1
- default: ""
- top_signame: pinmux_tl
- index: -1
- }
- ]
- }
- {
- name: padctrl
- type: padctrl
- clock: main
- clock_srcs:
- {
- clk_i: main
- }
- clock_group: secure
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]
- }
- domain: Aon
- base_addr: 0x40160000
- generated: "true"
- clock_reset_export: []
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_main_secure
- }
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list: []
- alert_list: []
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: padctrl
- width: 1
- default: ""
- top_signame: padctrl_tl
- index: -1
- }
- ]
- }
- {
- name: alert_handler
- type: alert_handler
- clock_srcs:
- {
- clk_i: main
- }
- clock_group: secure
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
- }
- base_addr: 0x411b0000
- generated: "true"
- localparam:
- {
- EscCntDw: 32
- AccuCntDw: 16
- LfsrSeed: 0x7FFFFFFF
- }
- clock_reset_export: []
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_main_secure
- }
- domain: "0"
- size: 0x1000
+ size: 0x4000
bus_device: tlul
bus_host: none
available_input_list: []
@@ -1672,32 +982,68 @@
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
- type: alert_pkg::lfsr_seed_t
- randcount: "32"
+ type: otp_ctrl_pkg::lfsr_seed_t
+ randcount: "40"
randtype: data
local: "false"
- default: 0x5def7861
+ default: 0xf45def7861
expose: "false"
- name_top: RndCnstAlertHandlerLfsrSeed
- randwidth: 32
+ name_top: RndCnstOtpCtrlLfsrSeed
+ randwidth: 40
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
- type: alert_pkg::lfsr_perm_t
- randcount: "32"
+ type: otp_ctrl_pkg::lfsr_perm_t
+ randcount: "40"
randtype: perm
local: "false"
- default: 0x5f00c4cafd73fc4ac479a61068375f38956d84b3
+ default: 0x5d294061e29a7c404f4593035a19097666e37072064153623855022d39e0
expose: "false"
- name_top: RndCnstAlertHandlerLfsrPerm
- randwidth: 160
+ name_top: RndCnstOtpCtrlLfsrPerm
+ randwidth: 240
+ }
+ {
+ name: RndCnstKey
+ desc: Compile-time random scrambling keys
+ type: otp_ctrl_pkg::key_array_t
+ randcount: "384"
+ randtype: data
+ local: "false"
+ default: 0x79ee911ce801484ba8373086f9dd4eee6faf88f22bccd612d1c09f5c02b2c8d1fdb92558e2d9c5d24440722325a93144
+ expose: "false"
+ name_top: RndCnstOtpCtrlKey
+ randwidth: 384
+ }
+ {
+ name: RndCnstDigestConst
+ desc: Compile-time random digest constant
+ type: otp_ctrl_pkg::digest_const_array_t
+ randcount: "640"
+ randtype: data
+ local: "false"
+ default: 0xce7d846469a3b8e35a6bd38295bd2fb366b3d62126c75eeaeb93d32f5cbc77463c91917516d51a2fa4400adc2669e2530ee2a465fd4dabcbd877afb6bcfeed7e03a0b091dc41d062dd10ca2d7b93136f
+ expose: "false"
+ name_top: RndCnstOtpCtrlDigestConst
+ randwidth: 640
+ }
+ {
+ name: RndCnstDigestIV
+ desc: Compile-time random digest IV
+ type: otp_ctrl_pkg::digest_iv_array_t
+ randcount: "320"
+ randtype: data
+ local: "false"
+ default: 0xb77f07ff3d7297200d5ab25561af49c696466a983e5346826a43628219e5a91389b9fe0d3b818e46
+ expose: "false"
+ name_top: RndCnstOtpCtrlDigestIV
+ randwidth: 320
}
]
interrupt_list:
[
{
- name: classa
+ name: otp_operation_done
width: 1
bits: "0"
bitinfo:
@@ -1709,7 +1055,7 @@
type: interrupt
}
{
- name: classb
+ name: otp_error
width: 1
bits: "1"
bitinfo:
@@ -1720,32 +1066,36 @@
]
type: interrupt
}
+ ]
+ alert_list:
+ [
{
- name: classc
+ name: otp_macro_failure
width: 1
- bits: "2"
+ bits: "0"
bitinfo:
[
- 4
1
- 2
+ 1
+ 0
]
- type: interrupt
+ type: alert
+ async: 1
}
{
- name: classd
+ name: otp_check_failure
width: 1
- bits: "3"
+ bits: "1"
bitinfo:
[
- 8
+ 2
1
- 3
+ 1
]
- type: interrupt
+ type: alert
+ async: 1
}
]
- alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
@@ -1753,16 +1103,162 @@
inter_signal_list:
[
{
- struct: alert_crashdump
+ struct: otp_ast_req
type: uni
- name: crashdump
+ name: otp_ast_pwr_seq
act: req
- package: alert_pkg
- inst_name: alert_handler
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
width: 1
- default: ""
- top_type: broadcast
- top_signame: alert_handler_crashdump
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq
+ index: -1
+ }
+ {
+ struct: otp_ast_rsp
+ type: uni
+ name: otp_ast_pwr_seq_h
+ act: rcv
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq_h
+ index: -1
+ }
+ {
+ struct: otp_edn
+ type: req_rsp
+ name: otp_edn
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: pwr_otp
+ type: req_rsp
+ name: pwr_otp
+ act: rsp
+ default: "'0"
+ package: pwrmgr_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: pwrmgr_pwr_otp
+ index: -1
+ }
+ {
+ struct: lc_otp_program
+ type: req_rsp
+ name: lc_otp_program
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_otp_token
+ type: req_rsp
+ name: lc_otp_token
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otp_lc_data
+ type: uni
+ name: otp_lc_data
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_escalate_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_provision_wr_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_dft_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otp_keymgr_key
+ type: uni
+ name: otp_keymgr_key
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: flash_otp_key
+ type: req_rsp
+ name: flash_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: sram_otp_key
+ width: "2"
+ type: req_rsp
+ name: sram_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otbn_otp_key
+ type: req_rsp
+ name: otbn_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: hw_cfg
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
index: -1
}
{
@@ -1771,10 +1267,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: alert_handler
+ inst_name: otp_ctrl
width: 1
default: ""
- top_signame: alert_handler_tl
+ top_signame: otp_ctrl_tl
index: -1
}
]
@@ -1794,7 +1290,7 @@
rst_slow_ni: rstmgr_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
- base_addr: 0x400A0000
+ base_addr: 0x40400000
generated: "true"
clock_reset_export: []
clock_connections:
@@ -1972,7 +1468,7 @@
rst_ni: rst_ni
}
domain: Aon
- base_addr: 0x400B0000
+ base_addr: 0x40410000
generated: "true"
clock_reset_export: []
clock_connections:
@@ -2106,7 +1602,7 @@
rst_io_div4_ni: rstmgr_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
- base_addr: 0x400C0000
+ base_addr: 0x40420000
generated: "true"
clock_reset_export: []
clock_connections:
@@ -2245,24 +1741,29 @@
]
}
{
- name: nmi_gen
- type: nmi_gen
+ name: pinmux
+ type: pinmux
+ clock: main
clock_srcs:
{
clk_i: main
+ clk_aon_i: aon
}
clock_group: secure
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]
+ rst_aon_ni: rstmgr_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel]
}
- base_addr: 0x411c0000
+ domain: Aon
+ base_addr: 0x40460000
+ generated: "true"
clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
+ clk_aon_i: clkmgr_clocks.clk_aon_secure
}
- domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
@@ -2270,67 +1771,70 @@
available_output_list: []
available_inout_list: []
param_list: []
- interrupt_list:
- [
- {
- name: esc0
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: interrupt
- }
- {
- name: esc1
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: interrupt
- }
- {
- name: esc2
- width: 1
- bits: "2"
- bitinfo:
- [
- 4
- 1
- 2
- ]
- type: interrupt
- }
- ]
+ interrupt_list: []
alert_list: []
- wakeup_list: []
- reset_request_list:
+ wakeup_list:
[
{
- name: nmi_rst_req
+ name: aon_wkup_req
+ width: "1"
}
]
+ reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
+ struct: lc_strap
+ type: req_rsp
+ name: lc_pinmux_strap
+ act: rsp
+ package: pinmux_pkg
+ default: "'0"
+ inst_name: pinmux
+ index: -1
+ }
+ {
+ struct: dft_strap_test
+ type: uni
+ name: dft_strap_test
+ act: req
+ package: pinmux_pkg
+ default: "'0"
+ inst_name: pinmux
+ index: -1
+ }
+ {
+ struct: io_pok
+ type: uni
+ name: io_pok
+ act: rcv
+ package: pinmux_pkg
+ default: "{pinmux_pkg::NIOPokSignals{1'b1}}"
+ inst_name: pinmux
+ index: -1
+ }
+ {
struct: logic
type: uni
- name: nmi_rst_req
+ name: sleep_en
+ act: rcv
+ package: ""
+ default: 1'b0
+ inst_name: pinmux
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: aon_wkup_req
act: req
package: ""
default: 1'b0
- inst_name: nmi_gen
+ inst_name: pinmux
width: 1
- top_signame: pwrmgr_rstreqs
+ top_signame: pwrmgr_wakeups
index: -1
}
{
@@ -2339,10 +1843,60 @@
type: req_rsp
act: rsp
name: tl
- inst_name: nmi_gen
+ inst_name: pinmux
width: 1
default: ""
- top_signame: nmi_gen_tl
+ top_signame: pinmux_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: padctrl
+ type: padctrl
+ clock: main
+ clock_srcs:
+ {
+ clk_i: main
+ }
+ clock_group: secure
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]
+ }
+ domain: Aon
+ base_addr: 0x40470000
+ generated: "true"
+ clock_reset_export: []
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_main_secure
+ }
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list: []
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: padctrl
+ width: 1
+ default: ""
+ top_signame: padctrl_tl
index: -1
}
]
@@ -2366,7 +1920,7 @@
rst_usb_48mhz_ni: rstmgr_resets.rst_usb_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
- base_addr: 0x40150000
+ base_addr: 0x40500000
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_peri
@@ -2685,28 +2239,221 @@
]
}
{
- name: sensor_ctrl
- type: sensor_ctrl
+ name: flash_ctrl
+ type: flash_ctrl
clock_srcs:
{
- clk_i: io_div4
+ clk_i: main
}
- clock_group: secure
- clock_reset_export:
- [
- ast
- ]
+ clock_group: infra
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
+ rst_ni: rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]
}
- domain: Aon
- base_addr: 0x40170000
- top_only: "true"
+ base_addr: 0x41000000
+ generated: "true"
+ clock_reset_export: []
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_secure
+ clk_i: clkmgr_clocks.clk_main_infra
}
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list:
+ [
+ {
+ name: prog_empty
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: prog_lvl
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: rd_full
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ {
+ name: rd_lvl
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ }
+ {
+ name: op_done
+ width: 1
+ bits: "4"
+ bitinfo:
+ [
+ 16
+ 1
+ 4
+ ]
+ type: interrupt
+ }
+ {
+ name: op_error
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: flash
+ type: req_rsp
+ name: flash
+ act: req
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ width: 1
+ default: ""
+ top_signame: flash_ctrl_flash
+ index: -1
+ }
+ {
+ struct: otp_flash
+ type: uni
+ name: otp
+ act: rcv
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_provision_en
+ act: rcv
+ package: lc_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: lc_flash
+ type: req_rsp
+ name: lc
+ act: rsp
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: edn_entropy
+ type: uni
+ name: edn
+ act: rcv
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: pwr_flash
+ type: req_rsp
+ name: pwrmgr
+ act: rsp
+ package: pwrmgr_pkg
+ inst_name: flash_ctrl
+ width: 1
+ default: ""
+ top_signame: pwrmgr_pwr_flash
+ index: -1
+ }
+ {
+ struct: keymgr_flash
+ type: uni
+ name: keymgr
+ act: req
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: flash_ctrl_keymgr
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: flash_ctrl
+ width: 1
+ default: ""
+ top_signame: flash_ctrl_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: rv_plic
+ type: rv_plic
+ clock_srcs:
+ {
+ clk_i: main
+ }
+ clock_group: secure
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x41010000
+ generated: "true"
+ clock_reset_export: []
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_main_secure
+ }
+ domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
@@ -2715,10 +2462,161 @@
available_inout_list: []
param_list: []
interrupt_list: []
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: rv_plic
+ width: 1
+ default: ""
+ top_signame: rv_plic_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: aes
+ type: aes
+ clock_srcs:
+ {
+ clk_i: main
+ }
+ clock_group: trans
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x41100000
+ clock_reset_export: []
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_main_aes
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list:
+ [
+ {
+ name: AES192Enable
+ type: bit
+ default: 1'b1
+ desc: Disable (0) or enable (1) support for 192-bit key lengths (AES-192).
+ local: "false"
+ expose: "false"
+ randcount: "0"
+ randtype: none
+ name_top: AesAES192Enable
+ }
+ {
+ name: Masking
+ type: bit
+ default: 1'b1
+ desc:
+ '''
+ Disable (0) or enable (1) first-order masking of the AES cipher core.
+ Masking requires the use of a masked S-Box, see SBoxImpl parameter.
+ '''
+ local: "false"
+ expose: "true"
+ randcount: "0"
+ randtype: none
+ name_top: AesMasking
+ }
+ {
+ name: SBoxImpl
+ type: aes_pkg::sbox_impl_e
+ default: aes_pkg::SBoxImplCanrightMasked
+ desc: Selection of the S-Box implementation. See aes_pkg.sv.
+ local: "false"
+ expose: "true"
+ randcount: "0"
+ randtype: none
+ name_top: AesSBoxImpl
+ }
+ {
+ name: SecStartTriggerDelay
+ type: int unsigned
+ default: "0"
+ desc:
+ '''
+ Manual start trigger delay, useful for SCA measurements.
+ A value of e.g. 40 allows the processor to go into sleep before AES starts operation.
+ '''
+ local: "false"
+ expose: "true"
+ randcount: "0"
+ randtype: none
+ name_top: SecAesStartTriggerDelay
+ }
+ {
+ name: SecAllowForcingMasks
+ type: bit
+ default: 1'b0
+ desc:
+ '''
+ Forbid (0) or allow (1) forcing the mask to zero via FORCE_ZERO_MASK bit in the Control Register.
+ Useful for SCA measurements.
+ Meaningful only if masking is enabled.
+ '''
+ local: "false"
+ expose: "true"
+ randcount: "0"
+ randtype: none
+ name_top: SecAesAllowForcingMasks
+ }
+ {
+ name: SeedClearing
+ type: logic [aes_pkg::WidthPRDClearing-1:0]
+ default: aes_pkg::DefaultSeedClearing
+ desc: Default seed of the PRNG used for register clearing.
+ local: "false"
+ expose: "false"
+ randcount: "0"
+ randtype: none
+ name_top: AesSeedClearing
+ }
+ {
+ name: SeedMasking
+ type: logic [aes_pkg::WidthPRDMasking-1:0]
+ default: aes_pkg::DefaultSeedMasking
+ desc: Default seed of the PRNG used for masking.
+ local: "false"
+ expose: "false"
+ randcount: "0"
+ randtype: none
+ name_top: AesSeedMasking
+ }
+ {
+ name: AlertAsyncOn
+ type: logic [aes_reg_pkg::NumAlerts-1:0]
+ default: "{aes_reg_pkg::NumAlerts{1'b1}}"
+ desc: One bit per alert specifying whether the corresponding sender in the AES module and the receiver in the alert handler are in the same clock domain (0) or whether there is an asynchronous boundary in between (1).
+ local: "false"
+ expose: "false"
+ randcount: "0"
+ randtype: none
+ name_top: AesAlertAsyncOn
+ }
+ ]
+ interrupt_list: []
alert_list:
[
{
- name: as
+ name: ctrl_err_update
width: 1
bits: "0"
bitinfo:
@@ -2728,10 +2626,10 @@
0
]
type: alert
- async: 1
+ async: 0
}
{
- name: cg
+ name: ctrl_err_storage
width: 1
bits: "1"
bitinfo:
@@ -2741,72 +2639,7 @@
1
]
type: alert
- async: 1
- }
- {
- name: gd
- width: 1
- bits: "2"
- bitinfo:
- [
- 4
- 1
- 2
- ]
- type: alert
- async: 1
- }
- {
- name: ts_hi
- width: 1
- bits: "3"
- bitinfo:
- [
- 8
- 1
- 3
- ]
- type: alert
- async: 1
- }
- {
- name: ts_lo
- width: 1
- bits: "4"
- bitinfo:
- [
- 16
- 1
- 4
- ]
- type: alert
- async: 1
- }
- {
- name: ls
- width: 1
- bits: "5"
- bitinfo:
- [
- 32
- 1
- 5
- ]
- type: alert
- async: 1
- }
- {
- name: ot
- width: 1
- bits: "6"
- bitinfo:
- [
- 64
- 1
- 6
- ]
- type: alert
- async: 1
+ async: 0
}
]
wakeup_list: []
@@ -2816,30 +2649,16 @@
inter_signal_list:
[
{
- struct: ast_alert
- type: req_rsp
- name: ast_alert
- act: rsp
- package: ast_wrapper_pkg
- inst_name: sensor_ctrl
- width: 1
- default: ""
- external: true
- top_signame: sensor_ctrl_ast_alert
- index: -1
- }
- {
- struct: ast_status
+ name: idle
type: uni
- name: ast_status
- act: rcv
- package: ast_wrapper_pkg
- inst_name: sensor_ctrl
+ act: req
+ package: ""
+ struct: logic
width: 1
+ inst_name: aes
default: ""
- external: true
- top_signame: sensor_ctrl_ast_status
- index: -1
+ top_signame: clkmgr_idle
+ index: 0
}
{
struct: tl
@@ -2847,10 +2666,267 @@
type: req_rsp
act: rsp
name: tl
- inst_name: sensor_ctrl
+ inst_name: aes
width: 1
default: ""
- top_signame: sensor_ctrl_tl
+ top_signame: aes_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: hmac
+ type: hmac
+ clock_srcs:
+ {
+ clk_i: main
+ }
+ clock_group: trans
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x41110000
+ clock_reset_export: []
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_main_hmac
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list:
+ [
+ {
+ name: hmac_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: fifo_empty
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: hmac_err
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ name: idle
+ type: uni
+ act: req
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: hmac
+ default: ""
+ top_signame: clkmgr_idle
+ index: 1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: hmac
+ width: 1
+ default: ""
+ top_signame: hmac_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: kmac
+ type: kmac
+ clock_srcs:
+ {
+ clk_i: main
+ }
+ clock_group: trans
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x41120000
+ clock_reset_export: []
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_main_kmac
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list:
+ [
+ {
+ name: EnMasking
+ type: int
+ default: "0"
+ desc:
+ '''
+ Disable(0) or enable(1) first-order masking of Keccak round.
+
+ If masking is enabled, ReuseShare parameter will impact the design.
+ '''
+ local: "false"
+ expose: "true"
+ randcount: "0"
+ randtype: none
+ name_top: KmacEnMasking
+ }
+ {
+ name: ReuseShare
+ type: int
+ default: "0"
+ desc:
+ '''
+ If enabled (1), the internal Keccak round logic will re-use the
+ adjacent shares as entropy in Domain-Oriented Masking AND logic.
+ It improves the throughput of Keccak, as it only requires small
+ amount of entropy rather than 1600 bit per round.
+
+ This feature is not implemented yet.
+ '''
+ local: "false"
+ expose: "true"
+ randcount: "0"
+ randtype: none
+ name_top: KmacReuseShare
+ }
+ ]
+ interrupt_list:
+ [
+ {
+ name: kmac_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: fifo_empty
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: kmac_err
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: hw_key_req
+ type: uni
+ name: keymgr_key
+ act: rcv
+ package: keymgr_pkg
+ inst_name: kmac
+ width: 1
+ default: ""
+ top_signame: keymgr_kmac_key
+ index: -1
+ }
+ {
+ struct: kmac_data
+ type: req_rsp
+ name: keymgr_kdf
+ act: rsp
+ package: keymgr_pkg
+ inst_name: kmac
+ width: 1
+ default: ""
+ top_signame: keymgr_kmac_data
+ index: -1
+ }
+ {
+ name: idle
+ type: uni
+ act: req
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: kmac
+ default: ""
+ top_signame: clkmgr_idle
+ index: 2
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: kmac
+ width: 1
+ default: ""
+ top_signame: kmac_tl
index: -1
}
]
@@ -2867,7 +2943,7 @@
{
rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
- base_addr: 0x401a0000
+ base_addr: 0x41130000
clock_reset_export: []
clock_connections:
{
@@ -3031,329 +3107,6 @@
]
}
{
- name: otp_ctrl
- type: otp_ctrl
- clock_srcs:
- {
- clk_i: io_div4
- }
- clock_group: timers
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
- }
- base_addr: 0x401b0000
- clock_reset_export: []
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_io_div4_timers
- }
- domain: "0"
- size: 0x4000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list:
- [
- {
- name: RndCnstLfsrSeed
- desc: Compile-time random bits for initial LFSR seed
- type: otp_ctrl_pkg::lfsr_seed_t
- randcount: "40"
- randtype: data
- local: "false"
- default: 0xf45def7861
- expose: "false"
- name_top: RndCnstOtpCtrlLfsrSeed
- randwidth: 40
- }
- {
- name: RndCnstLfsrPerm
- desc: Compile-time random permutation for LFSR output
- type: otp_ctrl_pkg::lfsr_perm_t
- randcount: "40"
- randtype: perm
- local: "false"
- default: 0x5d294061e29a7c404f4593035a19097666e37072064153623855022d39e0
- expose: "false"
- name_top: RndCnstOtpCtrlLfsrPerm
- randwidth: 240
- }
- {
- name: RndCnstKey
- desc: Compile-time random scrambling keys
- type: otp_ctrl_pkg::key_array_t
- randcount: "384"
- randtype: data
- local: "false"
- default: 0x79ee911ce801484ba8373086f9dd4eee6faf88f22bccd612d1c09f5c02b2c8d1fdb92558e2d9c5d24440722325a93144
- expose: "false"
- name_top: RndCnstOtpCtrlKey
- randwidth: 384
- }
- {
- name: RndCnstDigestConst
- desc: Compile-time random digest constant
- type: otp_ctrl_pkg::digest_const_array_t
- randcount: "640"
- randtype: data
- local: "false"
- default: 0xce7d846469a3b8e35a6bd38295bd2fb366b3d62126c75eeaeb93d32f5cbc77463c91917516d51a2fa4400adc2669e2530ee2a465fd4dabcbd877afb6bcfeed7e03a0b091dc41d062dd10ca2d7b93136f
- expose: "false"
- name_top: RndCnstOtpCtrlDigestConst
- randwidth: 640
- }
- {
- name: RndCnstDigestIV
- desc: Compile-time random digest IV
- type: otp_ctrl_pkg::digest_iv_array_t
- randcount: "320"
- randtype: data
- local: "false"
- default: 0xb77f07ff3d7297200d5ab25561af49c696466a983e5346826a43628219e5a91389b9fe0d3b818e46
- expose: "false"
- name_top: RndCnstOtpCtrlDigestIV
- randwidth: 320
- }
- ]
- interrupt_list:
- [
- {
- name: otp_operation_done
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: interrupt
- }
- {
- name: otp_error
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: interrupt
- }
- ]
- alert_list:
- [
- {
- name: otp_macro_failure
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: alert
- async: 1
- }
- {
- name: otp_check_failure
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: alert
- async: 1
- }
- ]
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: otp_ast_req
- type: uni
- name: otp_ast_pwr_seq
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- external: true
- top_signame: otp_ctrl_otp_ast_pwr_seq
- index: -1
- }
- {
- struct: otp_ast_rsp
- type: uni
- name: otp_ast_pwr_seq_h
- act: rcv
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- external: true
- top_signame: otp_ctrl_otp_ast_pwr_seq_h
- index: -1
- }
- {
- struct: otp_edn
- type: req_rsp
- name: otp_edn
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: pwr_otp
- type: req_rsp
- name: pwr_otp
- act: rsp
- default: "'0"
- package: pwrmgr_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: pwrmgr_pwr_otp
- index: -1
- }
- {
- struct: lc_otp_program
- type: req_rsp
- name: lc_otp_program
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: lc_otp_token
- type: req_rsp
- name: lc_otp_token
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: otp_lc_data
- type: uni
- name: otp_lc_data
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_escalate_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_provision_wr_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_dft_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: otp_keymgr_key
- type: uni
- name: otp_keymgr_key
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: flash_otp_key
- type: req_rsp
- name: flash_otp_key
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: sram_otp_key
- width: "2"
- type: req_rsp
- name: sram_otp_key
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: otbn_otp_key
- type: req_rsp
- name: otbn_otp_key
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: logic
- type: uni
- name: hw_cfg
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: otp_ctrl
- width: 1
- default: ""
- top_signame: otp_ctrl_tl
- index: -1
- }
- ]
- }
- {
name: csrng
type: csrng
clock_srcs:
@@ -3860,6 +3613,253 @@
]
}
{
+ name: alert_handler
+ type: alert_handler
+ clock_srcs:
+ {
+ clk_i: main
+ }
+ clock_group: secure
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x411b0000
+ generated: "true"
+ localparam:
+ {
+ EscCntDw: 32
+ AccuCntDw: 16
+ LfsrSeed: 0x7FFFFFFF
+ }
+ clock_reset_export: []
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_main_secure
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list:
+ [
+ {
+ name: RndCnstLfsrSeed
+ desc: Compile-time random bits for initial LFSR seed
+ type: alert_pkg::lfsr_seed_t
+ randcount: "32"
+ randtype: data
+ local: "false"
+ default: 0x5def7861
+ expose: "false"
+ name_top: RndCnstAlertHandlerLfsrSeed
+ randwidth: 32
+ }
+ {
+ name: RndCnstLfsrPerm
+ desc: Compile-time random permutation for LFSR output
+ type: alert_pkg::lfsr_perm_t
+ randcount: "32"
+ randtype: perm
+ local: "false"
+ default: 0x5f00c4cafd73fc4ac479a61068375f38956d84b3
+ expose: "false"
+ name_top: RndCnstAlertHandlerLfsrPerm
+ randwidth: 160
+ }
+ ]
+ interrupt_list:
+ [
+ {
+ name: classa
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: classb
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: classc
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ {
+ name: classd
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: alert_crashdump
+ type: uni
+ name: crashdump
+ act: req
+ package: alert_pkg
+ inst_name: alert_handler
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: alert_handler_crashdump
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: alert_handler
+ width: 1
+ default: ""
+ top_signame: alert_handler_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: nmi_gen
+ type: nmi_gen
+ clock_srcs:
+ {
+ clk_i: main
+ }
+ clock_group: secure
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x411c0000
+ clock_reset_export: []
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_main_secure
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list:
+ [
+ {
+ name: esc0
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: esc1
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: esc2
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list:
+ [
+ {
+ name: nmi_rst_req
+ }
+ ]
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: logic
+ type: uni
+ name: nmi_rst_req
+ act: req
+ package: ""
+ default: 1'b0
+ inst_name: nmi_gen
+ width: 1
+ top_signame: pwrmgr_rstreqs
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: nmi_gen
+ width: 1
+ default: ""
+ top_signame: nmi_gen_tl
+ index: -1
+ }
+ ]
+ }
+ {
name: otbn
type: otbn
clock_srcs:
@@ -3871,7 +3871,7 @@
{
rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
- base_addr: 0x50000000
+ base_addr: 0x411d0000
clock_reset_export: []
clock_connections:
{
@@ -4634,28 +4634,12 @@
}
{
base_addr: 0x40000000
- size_byte: 0x21000
+ size_byte: 0x421000
}
{
- base_addr: 0x40080000
+ base_addr: 0x40500000
size_byte: 0x1000
}
- {
- base_addr: 0x400A0000
- size_byte: 0x21000
- }
- {
- base_addr: 0x40150000
- size_byte: 0x1000
- }
- {
- base_addr: 0x40170000
- size_byte: 0x11000
- }
- {
- base_addr: 0x401b0000
- size_byte: 0x4000
- }
]
}
{
@@ -4668,7 +4652,7 @@
addr_range:
[
{
- base_addr: 0x40030000
+ base_addr: 0x41000000
size_byte: 0x1000
}
]
@@ -4686,7 +4670,7 @@
addr_range:
[
{
- base_addr: 0x40120000
+ base_addr: 0x41110000
size_byte: 0x1000
}
]
@@ -4722,7 +4706,7 @@
addr_range:
[
{
- base_addr: 0x40110000
+ base_addr: 0x41100000
size_byte: 0x1000
}
]
@@ -4811,7 +4795,7 @@
addr_range:
[
{
- base_addr: 0x40090000
+ base_addr: 0x41010000
size_byte: 0x1000
}
]
@@ -4829,7 +4813,7 @@
addr_range:
[
{
- base_addr: 0x40070000
+ base_addr: 0x40460000
size_byte: 0x1000
}
]
@@ -4847,7 +4831,7 @@
addr_range:
[
{
- base_addr: 0x40160000
+ base_addr: 0x40470000
size_byte: 0x1000
}
]
@@ -4900,7 +4884,7 @@
addr_range:
[
{
- base_addr: 0x50000000
+ base_addr: 0x411d0000
size_byte: 0x10000
}
]
@@ -4918,7 +4902,7 @@
addr_range:
[
{
- base_addr: 0x401a0000
+ base_addr: 0x41130000
size_byte: 0x1000
}
]
@@ -5286,7 +5270,7 @@
addr_range:
[
{
- base_addr: 0x40010000
+ base_addr: 0x40040000
size_byte: 0x1000
}
]
@@ -5304,7 +5288,7 @@
addr_range:
[
{
- base_addr: 0x40020000
+ base_addr: 0x40050000
size_byte: 0x1000
}
]
@@ -5322,7 +5306,7 @@
addr_range:
[
{
- base_addr: 0x40080000
+ base_addr: 0x40100000
size_byte: 0x1000
}
]
@@ -5340,7 +5324,7 @@
addr_range:
[
{
- base_addr: 0x40150000
+ base_addr: 0x40500000
size_byte: 0x1000
}
]
@@ -5358,7 +5342,7 @@
addr_range:
[
{
- base_addr: 0x400A0000
+ base_addr: 0x40400000
size_byte: 0x1000
}
]
@@ -5376,7 +5360,7 @@
addr_range:
[
{
- base_addr: 0x400B0000
+ base_addr: 0x40410000
size_byte: 0x1000
}
]
@@ -5394,7 +5378,7 @@
addr_range:
[
{
- base_addr: 0x400C0000
+ base_addr: 0x40420000
size_byte: 0x1000
}
]
@@ -5430,7 +5414,7 @@
addr_range:
[
{
- base_addr: 0x401b0000
+ base_addr: 0x40130000
size_byte: 0x4000
}
]
@@ -5448,7 +5432,7 @@
addr_range:
[
{
- base_addr: 0x40170000
+ base_addr: 0x40110000
size_byte: 0x1000
}
]
@@ -6909,15 +6893,15 @@
{
ast:
{
+ sensor_ctrl:
+ [
+ io_div4_secure
+ ]
usbdev:
[
io_div4_peri
usb_peri
]
- sensor_ctrl:
- [
- io_div4_secure
- ]
}
}
wakeups:
@@ -6939,15 +6923,15 @@
{
ast:
{
+ sensor_ctrl:
+ [
+ sys_io_div4
+ ]
usbdev:
[
sys_io_div4
usb
]
- sensor_ctrl:
- [
- sys_io_div4
- ]
}
}
reset_paths:
@@ -7008,91 +6992,6 @@
index: -1
}
{
- struct: flash
- type: req_rsp
- name: flash
- act: req
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- width: 1
- default: ""
- top_signame: flash_ctrl_flash
- index: -1
- }
- {
- struct: otp_flash
- type: uni
- name: otp
- act: rcv
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_provision_en
- act: rcv
- package: lc_ctrl_pkg
- inst_name: flash_ctrl
- index: -1
- }
- {
- struct: lc_flash
- type: req_rsp
- name: lc
- act: rsp
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- index: -1
- }
- {
- struct: edn_entropy
- type: uni
- name: edn
- act: rcv
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- index: -1
- }
- {
- struct: pwr_flash
- type: req_rsp
- name: pwrmgr
- act: rsp
- package: pwrmgr_pkg
- inst_name: flash_ctrl
- width: 1
- default: ""
- top_signame: pwrmgr_pwr_flash
- index: -1
- }
- {
- struct: keymgr_flash
- type: uni
- name: keymgr
- act: req
- package: flash_ctrl_pkg
- inst_name: flash_ctrl
- width: 1
- default: ""
- top_type: broadcast
- top_signame: flash_ctrl_keymgr
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: flash_ctrl
- width: 1
- default: ""
- top_signame: flash_ctrl_tl
- index: -1
- }
- {
struct: tl
package: tlul_pkg
type: req_rsp
@@ -7105,163 +7004,200 @@
index: -1
}
{
- name: idle
- type: uni
- act: req
- package: ""
- struct: logic
- width: 1
- inst_name: aes
- default: ""
- top_signame: clkmgr_idle
- index: 0
- }
- {
- struct: tl
- package: tlul_pkg
+ struct: ast_alert
type: req_rsp
+ name: ast_alert
act: rsp
- name: tl
- inst_name: aes
+ package: ast_wrapper_pkg
+ inst_name: sensor_ctrl
width: 1
default: ""
- top_signame: aes_tl
+ external: true
+ top_signame: sensor_ctrl_ast_alert
index: -1
}
{
- name: idle
+ struct: ast_status
type: uni
- act: req
- package: ""
- struct: logic
- width: 1
- inst_name: hmac
- default: ""
- top_signame: clkmgr_idle
- index: 1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: hmac
- width: 1
- default: ""
- top_signame: hmac_tl
- index: -1
- }
- {
- struct: hw_key_req
- type: uni
- name: keymgr_key
+ name: ast_status
act: rcv
- package: keymgr_pkg
- inst_name: kmac
+ package: ast_wrapper_pkg
+ inst_name: sensor_ctrl
width: 1
default: ""
- top_signame: keymgr_kmac_key
+ external: true
+ top_signame: sensor_ctrl_ast_status
index: -1
}
{
- struct: kmac_data
+ struct: tl
+ package: tlul_pkg
type: req_rsp
- name: keymgr_kdf
act: rsp
- package: keymgr_pkg
- inst_name: kmac
+ name: tl
+ inst_name: sensor_ctrl
width: 1
default: ""
- top_signame: keymgr_kmac_data
+ top_signame: sensor_ctrl_tl
index: -1
}
{
- name: idle
+ struct: otp_ast_req
type: uni
+ name: otp_ast_pwr_seq
act: req
- package: ""
- struct: logic
- width: 1
- inst_name: kmac
- default: ""
- top_signame: clkmgr_idle
- index: 2
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: kmac
- width: 1
- default: ""
- top_signame: kmac_tl
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: rv_plic
- width: 1
- default: ""
- top_signame: rv_plic_tl
- index: -1
- }
- {
- struct: lc_strap
- type: req_rsp
- name: lc_pinmux_strap
- act: rsp
- package: pinmux_pkg
default: "'0"
- inst_name: pinmux
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq
index: -1
}
{
- struct: dft_strap_test
+ struct: otp_ast_rsp
type: uni
- name: dft_strap_test
- act: req
- package: pinmux_pkg
+ name: otp_ast_pwr_seq_h
+ act: rcv
default: "'0"
- inst_name: pinmux
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq_h
index: -1
}
{
- struct: io_pok
+ struct: otp_edn
+ type: req_rsp
+ name: otp_edn
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: pwr_otp
+ type: req_rsp
+ name: pwr_otp
+ act: rsp
+ default: "'0"
+ package: pwrmgr_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: pwrmgr_pwr_otp
+ index: -1
+ }
+ {
+ struct: lc_otp_program
+ type: req_rsp
+ name: lc_otp_program
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_otp_token
+ type: req_rsp
+ name: lc_otp_token
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otp_lc_data
type: uni
- name: io_pok
+ name: otp_lc_data
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_escalate_en
act: rcv
- package: pinmux_pkg
- default: "{pinmux_pkg::NIOPokSignals{1'b1}}"
- inst_name: pinmux
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_provision_wr_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_dft_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otp_keymgr_key
+ type: uni
+ name: otp_keymgr_key
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: flash_otp_key
+ type: req_rsp
+ name: flash_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: sram_otp_key
+ width: "2"
+ type: req_rsp
+ name: sram_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otbn_otp_key
+ type: req_rsp
+ name: otbn_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
index: -1
}
{
struct: logic
type: uni
- name: sleep_en
- act: rcv
- package: ""
- default: 1'b0
- inst_name: pinmux
- index: -1
- }
- {
- struct: logic
- type: uni
- name: aon_wkup_req
+ name: hw_cfg
act: req
- package: ""
- default: 1'b0
- inst_name: pinmux
- width: 1
- top_signame: pwrmgr_wakeups
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
index: -1
}
{
@@ -7270,47 +7206,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: pinmux
+ inst_name: otp_ctrl
width: 1
default: ""
- top_signame: pinmux_tl
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: padctrl
- width: 1
- default: ""
- top_signame: padctrl_tl
- index: -1
- }
- {
- struct: alert_crashdump
- type: uni
- name: crashdump
- act: req
- package: alert_pkg
- inst_name: alert_handler
- width: 1
- default: ""
- top_type: broadcast
- top_signame: alert_handler_crashdump
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: alert_handler
- width: 1
- default: ""
- top_signame: alert_handler_tl
+ top_signame: otp_ctrl_tl
index: -1
}
{
@@ -7634,15 +7533,55 @@
index: -1
}
{
+ struct: lc_strap
+ type: req_rsp
+ name: lc_pinmux_strap
+ act: rsp
+ package: pinmux_pkg
+ default: "'0"
+ inst_name: pinmux
+ index: -1
+ }
+ {
+ struct: dft_strap_test
+ type: uni
+ name: dft_strap_test
+ act: req
+ package: pinmux_pkg
+ default: "'0"
+ inst_name: pinmux
+ index: -1
+ }
+ {
+ struct: io_pok
+ type: uni
+ name: io_pok
+ act: rcv
+ package: pinmux_pkg
+ default: "{pinmux_pkg::NIOPokSignals{1'b1}}"
+ inst_name: pinmux
+ index: -1
+ }
+ {
struct: logic
type: uni
- name: nmi_rst_req
+ name: sleep_en
+ act: rcv
+ package: ""
+ default: 1'b0
+ inst_name: pinmux
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: aon_wkup_req
act: req
package: ""
default: 1'b0
- inst_name: nmi_gen
+ inst_name: pinmux
width: 1
- top_signame: pwrmgr_rstreqs
+ top_signame: pwrmgr_wakeups
index: -1
}
{
@@ -7651,10 +7590,22 @@
type: req_rsp
act: rsp
name: tl
- inst_name: nmi_gen
+ inst_name: pinmux
width: 1
default: ""
- top_signame: nmi_gen_tl
+ top_signame: pinmux_tl
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: padctrl
+ width: 1
+ default: ""
+ top_signame: padctrl_tl
index: -1
}
{
@@ -7696,29 +7647,76 @@
index: -1
}
{
- struct: ast_alert
+ struct: flash
type: req_rsp
- name: ast_alert
- act: rsp
- package: ast_wrapper_pkg
- inst_name: sensor_ctrl
+ name: flash
+ act: req
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
width: 1
default: ""
- external: true
- top_signame: sensor_ctrl_ast_alert
+ top_signame: flash_ctrl_flash
index: -1
}
{
- struct: ast_status
+ struct: otp_flash
type: uni
- name: ast_status
+ name: otp
act: rcv
- package: ast_wrapper_pkg
- inst_name: sensor_ctrl
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_provision_en
+ act: rcv
+ package: lc_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: lc_flash
+ type: req_rsp
+ name: lc
+ act: rsp
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: edn_entropy
+ type: uni
+ name: edn
+ act: rcv
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: pwr_flash
+ type: req_rsp
+ name: pwrmgr
+ act: rsp
+ package: pwrmgr_pkg
+ inst_name: flash_ctrl
width: 1
default: ""
- external: true
- top_signame: sensor_ctrl_ast_status
+ top_signame: pwrmgr_pwr_flash
+ index: -1
+ }
+ {
+ struct: keymgr_flash
+ type: uni
+ name: keymgr
+ act: req
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: flash_ctrl_keymgr
index: -1
}
{
@@ -7727,10 +7725,118 @@
type: req_rsp
act: rsp
name: tl
- inst_name: sensor_ctrl
+ inst_name: flash_ctrl
width: 1
default: ""
- top_signame: sensor_ctrl_tl
+ top_signame: flash_ctrl_tl
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: rv_plic
+ width: 1
+ default: ""
+ top_signame: rv_plic_tl
+ index: -1
+ }
+ {
+ name: idle
+ type: uni
+ act: req
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: aes
+ default: ""
+ top_signame: clkmgr_idle
+ index: 0
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: aes
+ width: 1
+ default: ""
+ top_signame: aes_tl
+ index: -1
+ }
+ {
+ name: idle
+ type: uni
+ act: req
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: hmac
+ default: ""
+ top_signame: clkmgr_idle
+ index: 1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: hmac
+ width: 1
+ default: ""
+ top_signame: hmac_tl
+ index: -1
+ }
+ {
+ struct: hw_key_req
+ type: uni
+ name: keymgr_key
+ act: rcv
+ package: keymgr_pkg
+ inst_name: kmac
+ width: 1
+ default: ""
+ top_signame: keymgr_kmac_key
+ index: -1
+ }
+ {
+ struct: kmac_data
+ type: req_rsp
+ name: keymgr_kdf
+ act: rsp
+ package: keymgr_pkg
+ inst_name: kmac
+ width: 1
+ default: ""
+ top_signame: keymgr_kmac_data
+ index: -1
+ }
+ {
+ name: idle
+ type: uni
+ act: req
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: kmac
+ default: ""
+ top_signame: clkmgr_idle
+ index: 2
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: kmac
+ width: 1
+ default: ""
+ top_signame: kmac_tl
index: -1
}
{
@@ -7819,177 +7925,6 @@
index: -1
}
{
- struct: otp_ast_req
- type: uni
- name: otp_ast_pwr_seq
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- external: true
- top_signame: otp_ctrl_otp_ast_pwr_seq
- index: -1
- }
- {
- struct: otp_ast_rsp
- type: uni
- name: otp_ast_pwr_seq_h
- act: rcv
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- external: true
- top_signame: otp_ctrl_otp_ast_pwr_seq_h
- index: -1
- }
- {
- struct: otp_edn
- type: req_rsp
- name: otp_edn
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: pwr_otp
- type: req_rsp
- name: pwr_otp
- act: rsp
- default: "'0"
- package: pwrmgr_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: pwrmgr_pwr_otp
- index: -1
- }
- {
- struct: lc_otp_program
- type: req_rsp
- name: lc_otp_program
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: lc_otp_token
- type: req_rsp
- name: lc_otp_token
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: otp_lc_data
- type: uni
- name: otp_lc_data
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_escalate_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_provision_wr_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_dft_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: otp_keymgr_key
- type: uni
- name: otp_keymgr_key
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: flash_otp_key
- type: req_rsp
- name: flash_otp_key
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: sram_otp_key
- width: "2"
- type: req_rsp
- name: sram_otp_key
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: otbn_otp_key
- type: req_rsp
- name: otbn_otp_key
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: logic
- type: uni
- name: hw_cfg
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: otp_ctrl
- width: 1
- default: ""
- top_signame: otp_ctrl_tl
- index: -1
- }
- {
struct: csrng
type: req_rsp
name: csrng_cmd
@@ -8184,6 +8119,55 @@
index: -1
}
{
+ struct: alert_crashdump
+ type: uni
+ name: crashdump
+ act: req
+ package: alert_pkg
+ inst_name: alert_handler
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: alert_handler_crashdump
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: alert_handler
+ width: 1
+ default: ""
+ top_signame: alert_handler_tl
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: nmi_rst_req
+ act: req
+ package: ""
+ default: 1'b0
+ inst_name: nmi_gen
+ width: 1
+ top_signame: pwrmgr_rstreqs
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: nmi_gen
+ width: 1
+ default: ""
+ top_signame: nmi_gen_tl
+ index: -1
+ }
+ {
name: idle
type: uni
struct: logic
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 28f46ac..dc58252 100755
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -181,7 +181,6 @@
// the ip.hjson will declare the reset port names
// If none are defined at ip.hjson, rst_ni is used by default
reset_connections: {rst_ni: "sys_io_div4"},
-
base_addr: "0x40000000",
},
{ name: "gpio",
@@ -189,103 +188,46 @@
clock_srcs: {clk_i: "io_div4"},
clock_group: "peri",
reset_connections: {rst_ni: "sys_io_div4"},
- base_addr: "0x40010000",
+ base_addr: "0x40040000",
}
-
{ name: "spi_device",
type: "spi_device",
clock_srcs: {clk_i: "io_div4"},
clock_group: "peri",
reset_connections: {rst_ni: "spi_device"},
- base_addr: "0x40020000",
- },
- { name: "flash_ctrl",
- type: "flash_ctrl",
- clock_srcs: {clk_i: "main"},
- clock_group: "infra",
- reset_connections: {rst_ni: "lc"},
- base_addr: "0x40030000",
- generated: "true" // Indicate this module is generated in the topgen
+ base_addr: "0x40050000",
},
{ name: "rv_timer",
type: "rv_timer",
clock_srcs: {clk_i: "io_div4"},
clock_group: "timers",
reset_connections: {rst_ni: "sys_io_div4"},
- base_addr: "0x40080000",
+ base_addr: "0x40100000",
},
- { name: "aes",
- type: "aes",
- clock_srcs: {clk_i: "main"},
- clock_group: "trans",
- reset_connections: {rst_ni: "sys"},
+ { name: "sensor_ctrl",
+ type: "sensor_ctrl",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "secure",
+ clock_reset_export: ["ast"],
+ reset_connections: {rst_ni: "sys_io_div4"},
+ domain: "Aon",
base_addr: "0x40110000",
+ top_only: "true"
},
- { name: "hmac",
- type: "hmac",
- clock_srcs: {clk_i: "main"},
- clock_group: "trans",
- reset_connections: {rst_ni: "sys"},
- base_addr: "0x40120000",
- },
- { name: "kmac"
- type: "kmac"
- clock_srcs: {clk_i: "main"}
- clock_group: "trans"
- reset_connections: {rst_ni: "sys"}
- base_addr: "0x41120000"
- }
- { name: "rv_plic",
- type: "rv_plic",
- clock_srcs: {clk_i: "main"},
- clock_group: "secure",
- reset_connections: {rst_ni: "sys"},
- base_addr: "0x40090000",
- generated: "true" // Indicate this module is generated in the topgen
- }
- // pinmux is currently allocated to main fabric,
- // however this should probably be moved to peri fabric
- { name: "pinmux",
- type: "pinmux",
- clock: "main",
- clock_srcs: {clk_i: "main", clk_aon_i: "aon"},
- clock_group: "secure",
- reset_connections: {rst_ni: "sys", rst_aon_ni: "sys_aon"},
- domain: "Aon",
- base_addr: "0x40070000",
- generated: "true"
- },
- // see comment regarding pinmux above
- { name: "padctrl",
- type: "padctrl",
- clock: "main",
- clock_srcs: {clk_i: "main"},
- clock_group: "secure",
- reset_connections: {rst_ni: "sys"},
- domain: "Aon",
- base_addr: "0x40160000",
- generated: "true"
- },
- { name: "alert_handler",
- type: "alert_handler",
- clock_srcs: {clk_i: "main"},
- clock_group: "secure",
- reset_connections: {rst_ni: "sys"},
- base_addr: "0x411b0000",
- generated: "true" // Indicate this module is generated in the topgen
- localparam: {
- EscCntDw: 32,
- AccuCntDw: 16,
- LfsrSeed: "0x7FFFFFFF"
- }
- }
+ { name: "otp_ctrl",
+ type: "otp_ctrl",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "timers",
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x40130000",
+ },
{ name: "pwrmgr",
type: "pwrmgr",
clock_srcs: {clk_i: "io_div4", clk_slow_i: "aon"},
clock_group: "powerup",
reset_connections: {rst_ni: "por", rst_slow_ni: "por_aon"},
domain: "Aon",
- base_addr: "0x400A0000",
+ base_addr: "0x40400000",
generated: "true" // Indicate this module is generated in the topgen
},
@@ -296,7 +238,7 @@
clock_group: "powerup",
reset_connections: {rst_ni: "rst_ni"},
domain: "Aon",
- base_addr: "0x400B0000",
+ base_addr: "0x40410000",
generated: "true" // Indicate this module is generated in the topgen
},
{ name: "clkmgr",
@@ -306,18 +248,32 @@
reset_connections: {rst_ni: "por_io_div4", rst_main_ni: "por", rst_io_ni: "por_io", rst_usb_ni: "por_usb"
rst_io_div2_ni: "por_io_div2", rst_io_div4_ni: "por_io_div4"},
domain: "Aon",
- base_addr: "0x400C0000",
+ base_addr: "0x40420000",
generated: "true"
},
- // dummy module to capture the alert handler escalation signals
- // and test them by converting them into IRQs
- { name: "nmi_gen",
- type: "nmi_gen",
+ // pinmux is currently allocated to main fabric,
+ // however this should probably be moved to peri fabric
+ { name: "pinmux",
+ type: "pinmux",
+ clock: "main",
+ clock_srcs: {clk_i: "main", clk_aon_i: "aon"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "sys", rst_aon_ni: "sys_aon"},
+ domain: "Aon",
+ base_addr: "0x40460000",
+ generated: "true"
+ },
+ // see comment regarding pinmux above
+ { name: "padctrl",
+ type: "padctrl",
+ clock: "main",
clock_srcs: {clk_i: "main"},
clock_group: "secure",
reset_connections: {rst_ni: "sys"},
- base_addr: "0x411c0000",
- }
+ domain: "Aon",
+ base_addr: "0x40470000",
+ generated: "true"
+ },
{ name: "usbdev",
type: "usbdev",
clock_srcs: {clk_i: "io_div4", clk_usb_48mhz_i: "usb"},
@@ -325,31 +281,51 @@
clock_reset_export: ["ast"],
reset_connections: {rst_ni: "sys_io_div4", rst_usb_48mhz_ni: "usb"},
domain: "Aon",
- base_addr: "0x40150000",
+ base_addr: "0x40500000",
},
- { name: "sensor_ctrl",
- type: "sensor_ctrl",
- clock_srcs: {clk_i: "io_div4"},
+ { name: "flash_ctrl",
+ type: "flash_ctrl",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x41000000",
+ generated: "true" // Indicate this module is generated in the topgen
+ },
+ { name: "rv_plic",
+ type: "rv_plic",
+ clock_srcs: {clk_i: "main"},
clock_group: "secure",
- clock_reset_export: ["ast"],
- reset_connections: {rst_ni: "sys_io_div4"},
- domain: "Aon",
- base_addr: "0x40170000",
- top_only: "true"
+ reset_connections: {rst_ni: "sys"},
+ base_addr: "0x41010000",
+ generated: "true" // Indicate this module is generated in the topgen
+ },
+ { name: "aes",
+ type: "aes",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "trans",
+ reset_connections: {rst_ni: "sys"},
+ base_addr: "0x41100000",
+ },
+ { name: "hmac",
+ type: "hmac",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "trans",
+ reset_connections: {rst_ni: "sys"},
+ base_addr: "0x41110000",
+ },
+ { name: "kmac"
+ type: "kmac"
+ clock_srcs: {clk_i: "main"}
+ clock_group: "trans"
+ reset_connections: {rst_ni: "sys"}
+ base_addr: "0x41120000"
},
{ name: "keymgr",
type: "keymgr",
clock_srcs: {clk_i: "main"},
clock_group: "secure",
reset_connections: {rst_ni: "sys"},
- base_addr: "0x401a0000",
- },
- { name: "otp_ctrl",
- type: "otp_ctrl",
- clock_srcs: {clk_i: "io_div4"},
- clock_group: "timers",
- reset_connections: {rst_ni: "lc_io_div4"},
- base_addr: "0x401b0000",
+ base_addr: "0x41130000",
},
{ name: "csrng",
type: "csrng",
@@ -379,12 +355,34 @@
reset_connections: {rst_ni: "sys"},
base_addr: "0x41180000",
},
+ { name: "alert_handler",
+ type: "alert_handler",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "sys"},
+ base_addr: "0x411b0000",
+ generated: "true" // Indicate this module is generated in the topgen
+ localparam: {
+ EscCntDw: 32,
+ AccuCntDw: 16,
+ LfsrSeed: "0x7FFFFFFF"
+ }
+ },
+ // dummy module to capture the alert handler escalation signals
+ // and test them by converting them into IRQs
+ { name: "nmi_gen",
+ type: "nmi_gen",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "sys"},
+ base_addr: "0x411c0000",
+ },
{ name: "otbn",
type: "otbn",
clock_srcs: {clk_i: "main"},
clock_group: "trans",
reset_connections: {rst_ni: "sys"},
- base_addr: "0x50000000",
+ base_addr: "0x411d0000",
},
]
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
index a16d135..31c6801 100644
--- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -20,16 +20,16 @@
'{32'h20000000, 32'h2007ffff}
}},
'{"flash_ctrl", '{
- '{32'h40030000, 32'h40030fff}
+ '{32'h41000000, 32'h41000fff}
}},
'{"hmac", '{
- '{32'h40120000, 32'h40120fff}
+ '{32'h41110000, 32'h41110fff}
}},
'{"kmac", '{
'{32'h41120000, 32'h41120fff}
}},
'{"aes", '{
- '{32'h40110000, 32'h40110fff}
+ '{32'h41100000, 32'h41100fff}
}},
'{"entropy_src", '{
'{32'h41160000, 32'h41160fff}
@@ -44,13 +44,13 @@
'{32'h41180000, 32'h41180fff}
}},
'{"rv_plic", '{
- '{32'h40090000, 32'h40090fff}
+ '{32'h41010000, 32'h41010fff}
}},
'{"pinmux", '{
- '{32'h40070000, 32'h40070fff}
+ '{32'h40460000, 32'h40460fff}
}},
'{"padctrl", '{
- '{32'h40160000, 32'h40160fff}
+ '{32'h40470000, 32'h40470fff}
}},
'{"alert_handler", '{
'{32'h411b0000, 32'h411b0fff}
@@ -59,43 +59,43 @@
'{32'h411c0000, 32'h411c0fff}
}},
'{"otbn", '{
- '{32'h50000000, 32'h5000ffff}
+ '{32'h411d0000, 32'h411dffff}
}},
'{"keymgr", '{
- '{32'h401a0000, 32'h401a0fff}
+ '{32'h41130000, 32'h41130fff}
}},
'{"uart", '{
'{32'h40000000, 32'h40000fff}
}},
'{"gpio", '{
- '{32'h40010000, 32'h40010fff}
+ '{32'h40040000, 32'h40040fff}
}},
'{"spi_device", '{
- '{32'h40020000, 32'h40020fff}
+ '{32'h40050000, 32'h40050fff}
}},
'{"rv_timer", '{
- '{32'h40080000, 32'h40080fff}
+ '{32'h40100000, 32'h40100fff}
}},
'{"usbdev", '{
- '{32'h40150000, 32'h40150fff}
+ '{32'h40500000, 32'h40500fff}
}},
'{"pwrmgr", '{
- '{32'h400a0000, 32'h400a0fff}
+ '{32'h40400000, 32'h40400fff}
}},
'{"rstmgr", '{
- '{32'h400b0000, 32'h400b0fff}
+ '{32'h40410000, 32'h40410fff}
}},
'{"clkmgr", '{
- '{32'h400c0000, 32'h400c0fff}
+ '{32'h40420000, 32'h40420fff}
}},
'{"ram_ret", '{
'{32'h18000000, 32'h18000fff}
}},
'{"otp_ctrl", '{
- '{32'h401b0000, 32'h401b3fff}
+ '{32'h40130000, 32'h40133fff}
}},
'{"sensor_ctrl", '{
- '{32'h40170000, 32'h40170fff}
+ '{32'h40110000, 32'h40110fff}
}},
'{"ast_wrapper", '{
'{32'h40180000, 32'h40180fff}
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index d7d8373..4b4e085 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -416,9 +416,9 @@
// Exported clocks
////////////////////////////////////////////////////
+ assign clocks_ast_o.clk_ast_sensor_ctrl_io_div4_secure = clocks_o.clk_io_div4_secure;
assign clocks_ast_o.clk_ast_usbdev_io_div4_peri = clocks_o.clk_io_div4_peri;
assign clocks_ast_o.clk_ast_usbdev_usb_peri = clocks_o.clk_usb_peri;
- assign clocks_ast_o.clk_ast_sensor_ctrl_io_div4_secure = clocks_o.clk_io_div4_secure;
////////////////////////////////////////////////////
// Assertions
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
index 7edd4ea..eaf0059 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
@@ -43,9 +43,9 @@
} clkmgr_out_t;
typedef struct packed {
+ logic clk_ast_sensor_ctrl_io_div4_secure;
logic clk_ast_usbdev_io_div4_peri;
logic clk_ast_usbdev_usb_peri;
- logic clk_ast_sensor_ctrl_io_div4_secure;
} clkmgr_ast_out_t;
typedef struct packed {
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
index 02cf6e7..a890f3f 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -566,9 +566,9 @@
////////////////////////////////////////////////////
// Exported resets //
////////////////////////////////////////////////////
+ assign resets_ast_o.rst_ast_sensor_ctrl_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
assign resets_ast_o.rst_ast_usbdev_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
assign resets_ast_o.rst_ast_usbdev_usb_n = resets_o.rst_usb_n;
- assign resets_ast_o.rst_ast_sensor_ctrl_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
////////////////////////////////////////////////////
// Crash info capture //
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
index 5487c0b..78d69ab 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
@@ -62,9 +62,9 @@
// exported resets
typedef struct packed {
+ logic [PowerDomains-1:0] rst_ast_sensor_ctrl_sys_io_div4_n;
logic [PowerDomains-1:0] rst_ast_usbdev_sys_io_div4_n;
logic [PowerDomains-1:0] rst_ast_usbdev_usb_n;
- logic [PowerDomains-1:0] rst_ast_sensor_ctrl_sys_io_div4_n;
} rstmgr_ast_out_t;
// default value for rstmgr_ast_rsp_t (for dangling ports)
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index 82f70d6..a432951 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -205,28 +205,12 @@
}
{
base_addr: 0x40000000
- size_byte: 0x21000
+ size_byte: 0x421000
}
{
- base_addr: 0x40080000
+ base_addr: 0x40500000
size_byte: 0x1000
}
- {
- base_addr: 0x400A0000
- size_byte: 0x21000
- }
- {
- base_addr: 0x40150000
- size_byte: 0x1000
- }
- {
- base_addr: 0x40170000
- size_byte: 0x11000
- }
- {
- base_addr: 0x401b0000
- size_byte: 0x4000
- }
]
}
{
@@ -239,7 +223,7 @@
addr_range:
[
{
- base_addr: 0x40030000
+ base_addr: 0x41000000
size_byte: 0x1000
}
]
@@ -257,7 +241,7 @@
addr_range:
[
{
- base_addr: 0x40120000
+ base_addr: 0x41110000
size_byte: 0x1000
}
]
@@ -293,7 +277,7 @@
addr_range:
[
{
- base_addr: 0x40110000
+ base_addr: 0x41100000
size_byte: 0x1000
}
]
@@ -382,7 +366,7 @@
addr_range:
[
{
- base_addr: 0x40090000
+ base_addr: 0x41010000
size_byte: 0x1000
}
]
@@ -400,7 +384,7 @@
addr_range:
[
{
- base_addr: 0x40070000
+ base_addr: 0x40460000
size_byte: 0x1000
}
]
@@ -418,7 +402,7 @@
addr_range:
[
{
- base_addr: 0x40160000
+ base_addr: 0x40470000
size_byte: 0x1000
}
]
@@ -471,7 +455,7 @@
addr_range:
[
{
- base_addr: 0x50000000
+ base_addr: 0x411d0000
size_byte: 0x10000
}
]
@@ -489,7 +473,7 @@
addr_range:
[
{
- base_addr: 0x401a0000
+ base_addr: 0x41130000
size_byte: 0x1000
}
]
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
index 08b9698..f2ba945 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -21,24 +21,20 @@
}},
'{"peri", '{
'{32'h18000000, 32'h18000fff},
- '{32'h40000000, 32'h40020fff},
- '{32'h40080000, 32'h40080fff},
- '{32'h400a0000, 32'h400c0fff},
- '{32'h40150000, 32'h40150fff},
- '{32'h40170000, 32'h40180fff},
- '{32'h401b0000, 32'h401b3fff}
+ '{32'h40000000, 32'h40420fff},
+ '{32'h40500000, 32'h40500fff}
}},
'{"flash_ctrl", '{
- '{32'h40030000, 32'h40030fff}
+ '{32'h41000000, 32'h41000fff}
}},
'{"hmac", '{
- '{32'h40120000, 32'h40120fff}
+ '{32'h41110000, 32'h41110fff}
}},
'{"kmac", '{
'{32'h41120000, 32'h41120fff}
}},
'{"aes", '{
- '{32'h40110000, 32'h40110fff}
+ '{32'h41100000, 32'h41100fff}
}},
'{"entropy_src", '{
'{32'h41160000, 32'h41160fff}
@@ -53,13 +49,13 @@
'{32'h41180000, 32'h41180fff}
}},
'{"rv_plic", '{
- '{32'h40090000, 32'h40090fff}
+ '{32'h41010000, 32'h41010fff}
}},
'{"pinmux", '{
- '{32'h40070000, 32'h40070fff}
+ '{32'h40460000, 32'h40460fff}
}},
'{"padctrl", '{
- '{32'h40160000, 32'h40160fff}
+ '{32'h40470000, 32'h40470fff}
}},
'{"alert_handler", '{
'{32'h411b0000, 32'h411b0fff}
@@ -68,10 +64,10 @@
'{32'h411c0000, 32'h411c0fff}
}},
'{"otbn", '{
- '{32'h50000000, 32'h5000ffff}
+ '{32'h411d0000, 32'h411dffff}
}},
'{"keymgr", '{
- '{32'h401a0000, 32'h401a0fff}
+ '{32'h41130000, 32'h41130fff}
}}};
// List of Xbar hosts
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
index e53e2cb..acb519e 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -10,42 +10,34 @@
localparam logic [31:0] ADDR_SPACE_DEBUG_MEM = 32'h 1a110000;
localparam logic [31:0] ADDR_SPACE_RAM_MAIN = 32'h 10000000;
localparam logic [31:0] ADDR_SPACE_EFLASH = 32'h 20000000;
- localparam logic [6:0][31:0] ADDR_SPACE_PERI = {
- 32'h 401b0000,
- 32'h 40170000,
- 32'h 40150000,
- 32'h 400a0000,
- 32'h 40080000,
+ localparam logic [2:0][31:0] ADDR_SPACE_PERI = {
+ 32'h 40500000,
32'h 40000000,
32'h 18000000
};
- localparam logic [31:0] ADDR_SPACE_FLASH_CTRL = 32'h 40030000;
- localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 40120000;
+ localparam logic [31:0] ADDR_SPACE_FLASH_CTRL = 32'h 41000000;
+ localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 41110000;
localparam logic [31:0] ADDR_SPACE_KMAC = 32'h 41120000;
- localparam logic [31:0] ADDR_SPACE_AES = 32'h 40110000;
+ localparam logic [31:0] ADDR_SPACE_AES = 32'h 41100000;
localparam logic [31:0] ADDR_SPACE_ENTROPY_SRC = 32'h 41160000;
localparam logic [31:0] ADDR_SPACE_CSRNG = 32'h 41150000;
localparam logic [31:0] ADDR_SPACE_EDN0 = 32'h 41170000;
localparam logic [31:0] ADDR_SPACE_EDN1 = 32'h 41180000;
- localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 40090000;
- localparam logic [31:0] ADDR_SPACE_PINMUX = 32'h 40070000;
- localparam logic [31:0] ADDR_SPACE_PADCTRL = 32'h 40160000;
+ localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 41010000;
+ localparam logic [31:0] ADDR_SPACE_PINMUX = 32'h 40460000;
+ localparam logic [31:0] ADDR_SPACE_PADCTRL = 32'h 40470000;
localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 411b0000;
localparam logic [31:0] ADDR_SPACE_NMI_GEN = 32'h 411c0000;
- localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 50000000;
- localparam logic [31:0] ADDR_SPACE_KEYMGR = 32'h 401a0000;
+ localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 411d0000;
+ localparam logic [31:0] ADDR_SPACE_KEYMGR = 32'h 41130000;
localparam logic [31:0] ADDR_MASK_ROM = 32'h 00003fff;
localparam logic [31:0] ADDR_MASK_DEBUG_MEM = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RAM_MAIN = 32'h 0000ffff;
localparam logic [31:0] ADDR_MASK_EFLASH = 32'h 0007ffff;
- localparam logic [6:0][31:0] ADDR_MASK_PERI = {
- 32'h 00003fff,
- 32'h 00010fff,
+ localparam logic [2:0][31:0] ADDR_MASK_PERI = {
32'h 00000fff,
- 32'h 00020fff,
- 32'h 00000fff,
- 32'h 00020fff,
+ 32'h 00420fff,
32'h 00000fff
};
localparam logic [31:0] ADDR_MASK_FLASH_CTRL = 32'h 00000fff;
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
index 4670d59..245c314 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -567,15 +567,7 @@
((tl_s1n_28_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
(tl_s1n_28_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
((tl_s1n_28_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
- (tl_s1n_28_us_h2d.a_address >= ADDR_SPACE_PERI[2])) ||
- ((tl_s1n_28_us_h2d.a_address <= (ADDR_MASK_PERI[3] + ADDR_SPACE_PERI[3])) &&
- (tl_s1n_28_us_h2d.a_address >= ADDR_SPACE_PERI[3])) ||
- ((tl_s1n_28_us_h2d.a_address <= (ADDR_MASK_PERI[4] + ADDR_SPACE_PERI[4])) &&
- (tl_s1n_28_us_h2d.a_address >= ADDR_SPACE_PERI[4])) ||
- ((tl_s1n_28_us_h2d.a_address <= (ADDR_MASK_PERI[5] + ADDR_SPACE_PERI[5])) &&
- (tl_s1n_28_us_h2d.a_address >= ADDR_SPACE_PERI[5])) ||
- ((tl_s1n_28_us_h2d.a_address <= (ADDR_MASK_PERI[6] + ADDR_SPACE_PERI[6])) &&
- (tl_s1n_28_us_h2d.a_address >= ADDR_SPACE_PERI[6]))
+ (tl_s1n_28_us_h2d.a_address >= ADDR_SPACE_PERI[2]))
) begin
dev_sel_s1n_28 = 5'd4;
@@ -643,15 +635,7 @@
((tl_s1n_45_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
(tl_s1n_45_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
((tl_s1n_45_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
- (tl_s1n_45_us_h2d.a_address >= ADDR_SPACE_PERI[2])) ||
- ((tl_s1n_45_us_h2d.a_address <= (ADDR_MASK_PERI[3] + ADDR_SPACE_PERI[3])) &&
- (tl_s1n_45_us_h2d.a_address >= ADDR_SPACE_PERI[3])) ||
- ((tl_s1n_45_us_h2d.a_address <= (ADDR_MASK_PERI[4] + ADDR_SPACE_PERI[4])) &&
- (tl_s1n_45_us_h2d.a_address >= ADDR_SPACE_PERI[4])) ||
- ((tl_s1n_45_us_h2d.a_address <= (ADDR_MASK_PERI[5] + ADDR_SPACE_PERI[5])) &&
- (tl_s1n_45_us_h2d.a_address >= ADDR_SPACE_PERI[5])) ||
- ((tl_s1n_45_us_h2d.a_address <= (ADDR_MASK_PERI[6] + ADDR_SPACE_PERI[6])) &&
- (tl_s1n_45_us_h2d.a_address >= ADDR_SPACE_PERI[6]))
+ (tl_s1n_45_us_h2d.a_address >= ADDR_SPACE_PERI[2]))
) begin
dev_sel_s1n_45 = 5'd3;
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index 28bb941..6e9d155 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -83,7 +83,7 @@
addr_range:
[
{
- base_addr: 0x40010000
+ base_addr: 0x40040000
size_byte: 0x1000
}
]
@@ -101,7 +101,7 @@
addr_range:
[
{
- base_addr: 0x40020000
+ base_addr: 0x40050000
size_byte: 0x1000
}
]
@@ -119,7 +119,7 @@
addr_range:
[
{
- base_addr: 0x40080000
+ base_addr: 0x40100000
size_byte: 0x1000
}
]
@@ -137,7 +137,7 @@
addr_range:
[
{
- base_addr: 0x40150000
+ base_addr: 0x40500000
size_byte: 0x1000
}
]
@@ -155,7 +155,7 @@
addr_range:
[
{
- base_addr: 0x400A0000
+ base_addr: 0x40400000
size_byte: 0x1000
}
]
@@ -173,7 +173,7 @@
addr_range:
[
{
- base_addr: 0x400B0000
+ base_addr: 0x40410000
size_byte: 0x1000
}
]
@@ -191,7 +191,7 @@
addr_range:
[
{
- base_addr: 0x400C0000
+ base_addr: 0x40420000
size_byte: 0x1000
}
]
@@ -227,7 +227,7 @@
addr_range:
[
{
- base_addr: 0x401b0000
+ base_addr: 0x40130000
size_byte: 0x4000
}
]
@@ -245,7 +245,7 @@
addr_range:
[
{
- base_addr: 0x40170000
+ base_addr: 0x40110000
size_byte: 0x1000
}
]
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
index 8e54374..0b29528 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -11,34 +11,34 @@
'{32'h40000000, 32'h40000fff}
}},
'{"gpio", '{
- '{32'h40010000, 32'h40010fff}
+ '{32'h40040000, 32'h40040fff}
}},
'{"spi_device", '{
- '{32'h40020000, 32'h40020fff}
+ '{32'h40050000, 32'h40050fff}
}},
'{"rv_timer", '{
- '{32'h40080000, 32'h40080fff}
+ '{32'h40100000, 32'h40100fff}
}},
'{"usbdev", '{
- '{32'h40150000, 32'h40150fff}
+ '{32'h40500000, 32'h40500fff}
}},
'{"pwrmgr", '{
- '{32'h400a0000, 32'h400a0fff}
+ '{32'h40400000, 32'h40400fff}
}},
'{"rstmgr", '{
- '{32'h400b0000, 32'h400b0fff}
+ '{32'h40410000, 32'h40410fff}
}},
'{"clkmgr", '{
- '{32'h400c0000, 32'h400c0fff}
+ '{32'h40420000, 32'h40420fff}
}},
'{"ram_ret", '{
'{32'h18000000, 32'h18000fff}
}},
'{"otp_ctrl", '{
- '{32'h401b0000, 32'h401b3fff}
+ '{32'h40130000, 32'h40133fff}
}},
'{"sensor_ctrl", '{
- '{32'h40170000, 32'h40170fff}
+ '{32'h40110000, 32'h40110fff}
}},
'{"ast_wrapper", '{
'{32'h40180000, 32'h40180fff}
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
index cf2c712..c74cffc 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -7,16 +7,16 @@
package tl_peri_pkg;
localparam logic [31:0] ADDR_SPACE_UART = 32'h 40000000;
- localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40010000;
- localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40020000;
- localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40080000;
- localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 40150000;
- localparam logic [31:0] ADDR_SPACE_PWRMGR = 32'h 400a0000;
- localparam logic [31:0] ADDR_SPACE_RSTMGR = 32'h 400b0000;
- localparam logic [31:0] ADDR_SPACE_CLKMGR = 32'h 400c0000;
+ localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40040000;
+ localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40050000;
+ localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40100000;
+ localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 40500000;
+ localparam logic [31:0] ADDR_SPACE_PWRMGR = 32'h 40400000;
+ localparam logic [31:0] ADDR_SPACE_RSTMGR = 32'h 40410000;
+ localparam logic [31:0] ADDR_SPACE_CLKMGR = 32'h 40420000;
localparam logic [31:0] ADDR_SPACE_RAM_RET = 32'h 18000000;
- localparam logic [31:0] ADDR_SPACE_OTP_CTRL = 32'h 401b0000;
- localparam logic [31:0] ADDR_SPACE_SENSOR_CTRL = 32'h 40170000;
+ localparam logic [31:0] ADDR_SPACE_OTP_CTRL = 32'h 40130000;
+ localparam logic [31:0] ADDR_SPACE_SENSOR_CTRL = 32'h 40110000;
localparam logic [31:0] ADDR_SPACE_AST_WRAPPER = 32'h 40180000;
localparam logic [31:0] ADDR_MASK_UART = 32'h 00000fff;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 1d31d2d..306dad4 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -119,19 +119,14 @@
logic cio_spi_device_sdi_p2d;
logic cio_spi_device_sdo_d2p;
logic cio_spi_device_sdo_en_d2p;
- // flash_ctrl
// rv_timer
- // aes
- // hmac
- // kmac
- // rv_plic
- // pinmux
- // padctrl
- // alert_handler
+ // sensor_ctrl
+ // otp_ctrl
// pwrmgr
// rstmgr
// clkmgr
- // nmi_gen
+ // pinmux
+ // padctrl
// usbdev
logic cio_usbdev_sense_p2d;
logic cio_usbdev_d_p2d;
@@ -153,13 +148,18 @@
logic cio_usbdev_dp_en_d2p;
logic cio_usbdev_dn_d2p;
logic cio_usbdev_dn_en_d2p;
- // sensor_ctrl
+ // flash_ctrl
+ // rv_plic
+ // aes
+ // hmac
+ // kmac
// keymgr
- // otp_ctrl
// csrng
// entropy_src
// edn0
// edn1
+ // alert_handler
+ // nmi_gen
// otbn
@@ -180,27 +180,10 @@
logic intr_spi_device_rxerr;
logic intr_spi_device_rxoverflow;
logic intr_spi_device_txunderflow;
- logic intr_flash_ctrl_prog_empty;
- logic intr_flash_ctrl_prog_lvl;
- logic intr_flash_ctrl_rd_full;
- logic intr_flash_ctrl_rd_lvl;
- logic intr_flash_ctrl_op_done;
- logic intr_flash_ctrl_op_error;
logic intr_rv_timer_timer_expired_0_0;
- logic intr_hmac_hmac_done;
- logic intr_hmac_fifo_empty;
- logic intr_hmac_hmac_err;
- logic intr_kmac_kmac_done;
- logic intr_kmac_fifo_empty;
- logic intr_kmac_kmac_err;
- logic intr_alert_handler_classa;
- logic intr_alert_handler_classb;
- logic intr_alert_handler_classc;
- logic intr_alert_handler_classd;
+ logic intr_otp_ctrl_otp_operation_done;
+ logic intr_otp_ctrl_otp_error;
logic intr_pwrmgr_wakeup;
- logic intr_nmi_gen_esc0;
- logic intr_nmi_gen_esc1;
- logic intr_nmi_gen_esc2;
logic intr_usbdev_pkt_received;
logic intr_usbdev_pkt_sent;
logic intr_usbdev_disconnected;
@@ -218,10 +201,20 @@
logic intr_usbdev_frame;
logic intr_usbdev_connected;
logic intr_usbdev_link_out_err;
+ logic intr_flash_ctrl_prog_empty;
+ logic intr_flash_ctrl_prog_lvl;
+ logic intr_flash_ctrl_rd_full;
+ logic intr_flash_ctrl_rd_lvl;
+ logic intr_flash_ctrl_op_done;
+ logic intr_flash_ctrl_op_error;
+ logic intr_hmac_hmac_done;
+ logic intr_hmac_fifo_empty;
+ logic intr_hmac_hmac_err;
+ logic intr_kmac_kmac_done;
+ logic intr_kmac_fifo_empty;
+ logic intr_kmac_kmac_err;
logic intr_keymgr_op_done;
logic intr_keymgr_err;
- logic intr_otp_ctrl_otp_operation_done;
- logic intr_otp_ctrl_otp_error;
logic intr_csrng_cs_cmd_req_done;
logic intr_csrng_cs_entropy_req;
logic intr_csrng_cs_hw_inst_exc;
@@ -233,6 +226,13 @@
logic intr_edn0_edn_fifo_err;
logic intr_edn1_edn_cmd_req_done;
logic intr_edn1_edn_fifo_err;
+ logic intr_alert_handler_classa;
+ logic intr_alert_handler_classb;
+ logic intr_alert_handler_classc;
+ logic intr_alert_handler_classd;
+ logic intr_nmi_gen_esc0;
+ logic intr_nmi_gen_esc1;
+ logic intr_nmi_gen_esc2;
logic intr_otbn_done;
@@ -745,33 +745,6 @@
.rst_ni (rstmgr_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel])
);
- flash_ctrl u_flash_ctrl (
-
- // Interrupt
- .intr_prog_empty_o (intr_flash_ctrl_prog_empty),
- .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
- .intr_rd_full_o (intr_flash_ctrl_rd_full),
- .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
- .intr_op_done_o (intr_flash_ctrl_op_done),
- .intr_op_error_o (intr_flash_ctrl_op_error),
-
- // Inter-module signals
- .flash_o(flash_ctrl_flash_req),
- .flash_i(flash_ctrl_flash_rsp),
- .otp_i(flash_ctrl_pkg::OTP_FLASH_DEFAULT),
- .lc_provision_en_i(lc_ctrl_pkg::LC_TX_DEFAULT),
- .lc_i(flash_ctrl_pkg::LC_FLASH_REQ_DEFAULT),
- .lc_o(),
- .edn_i(flash_ctrl_pkg::EDN_ENTROPY_DEFAULT),
- .pwrmgr_i(pwrmgr_pwr_flash_req),
- .pwrmgr_o(pwrmgr_pwr_flash_rsp),
- .keymgr_o(flash_ctrl_keymgr),
- .tl_i(flash_ctrl_tl_req),
- .tl_o(flash_ctrl_tl_rsp),
- .clk_i (clkmgr_clocks.clk_main_infra),
- .rst_ni (rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
- );
-
rv_timer u_rv_timer (
// Interrupt
@@ -784,150 +757,72 @@
.rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
- aes #(
- .AES192Enable(1'b1),
- .Masking(AesMasking),
- .SBoxImpl(AesSBoxImpl),
- .SecStartTriggerDelay(SecAesStartTriggerDelay),
- .SecAllowForcingMasks(SecAesAllowForcingMasks),
- .SeedClearing(aes_pkg::DefaultSeedClearing),
- .SeedMasking(aes_pkg::DefaultSeedMasking),
- .AlertAsyncOn({aes_reg_pkg::NumAlerts{1'b1}})
- ) u_aes (
+ sensor_ctrl u_sensor_ctrl (
- // [0]: ctrl_err_update
- // [1]: ctrl_err_storage
- .alert_tx_o ( alert_tx[1:0] ),
- .alert_rx_i ( alert_rx[1:0] ),
+ // [0]: as
+ // [1]: cg
+ // [2]: gd
+ // [3]: ts_hi
+ // [4]: ts_lo
+ // [5]: ls
+ // [6]: ot
+ .alert_tx_o ( alert_tx[6:0] ),
+ .alert_rx_i ( alert_rx[6:0] ),
// Inter-module signals
- .idle_o(clkmgr_idle[0]),
- .tl_i(aes_tl_req),
- .tl_o(aes_tl_rsp),
- .clk_i (clkmgr_clocks.clk_main_aes),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .ast_alert_i(sensor_ctrl_ast_alert_req_i),
+ .ast_alert_o(sensor_ctrl_ast_alert_rsp_o),
+ .ast_status_i(sensor_ctrl_ast_status_i),
+ .tl_i(sensor_ctrl_tl_req),
+ .tl_o(sensor_ctrl_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel])
);
- hmac u_hmac (
+ otp_ctrl #(
+ .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm),
+ .RndCnstKey(RndCnstOtpCtrlKey),
+ .RndCnstDigestConst(RndCnstOtpCtrlDigestConst),
+ .RndCnstDigestIV(RndCnstOtpCtrlDigestIV)
+ ) u_otp_ctrl (
// Interrupt
- .intr_hmac_done_o (intr_hmac_hmac_done),
- .intr_fifo_empty_o (intr_hmac_fifo_empty),
- .intr_hmac_err_o (intr_hmac_hmac_err),
+ .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
+ .intr_otp_error_o (intr_otp_ctrl_otp_error),
+
+ // [7]: otp_macro_failure
+ // [8]: otp_check_failure
+ .alert_tx_o ( alert_tx[8:7] ),
+ .alert_rx_i ( alert_rx[8:7] ),
// Inter-module signals
- .idle_o(clkmgr_idle[1]),
- .tl_i(hmac_tl_req),
- .tl_o(hmac_tl_rsp),
- .clk_i (clkmgr_clocks.clk_main_hmac),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
- );
-
- kmac #(
- .EnMasking(KmacEnMasking),
- .ReuseShare(KmacReuseShare)
- ) u_kmac (
-
- // Interrupt
- .intr_kmac_done_o (intr_kmac_kmac_done),
- .intr_fifo_empty_o (intr_kmac_fifo_empty),
- .intr_kmac_err_o (intr_kmac_kmac_err),
-
- // Inter-module signals
- .keymgr_key_i(keymgr_kmac_key),
- .keymgr_kdf_i(keymgr_kmac_data_req),
- .keymgr_kdf_o(keymgr_kmac_data_rsp),
- .idle_o(clkmgr_idle[2]),
- .tl_i(kmac_tl_req),
- .tl_o(kmac_tl_rsp),
- .clk_i (clkmgr_clocks.clk_main_kmac),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
- );
-
- rv_plic u_rv_plic (
-
- // Inter-module signals
- .tl_i(rv_plic_tl_req),
- .tl_o(rv_plic_tl_rsp),
-
- .intr_src_i (intr_vector),
- .irq_o (irq_plic),
- .irq_id_o (irq_id),
- .msip_o (msip),
- .clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
- );
-
- pinmux u_pinmux (
-
- // Inter-module signals
- .lc_pinmux_strap_i('0),
- .lc_pinmux_strap_o(),
- .dft_strap_test_o(),
- .io_pok_i({pinmux_pkg::NIOPokSignals{1'b1}}),
- .sleep_en_i(1'b0),
- .aon_wkup_req_o(pwrmgr_wakeups),
- .tl_i(pinmux_tl_req),
- .tl_o(pinmux_tl_rsp),
-
- .periph_to_mio_i (mio_d2p ),
- .periph_to_mio_oe_i (mio_d2p_en ),
- .mio_to_periph_o (mio_p2d ),
-
- .mio_out_o,
- .mio_oe_o,
- .mio_in_i,
-
- .periph_to_dio_i (dio_d2p ),
- .periph_to_dio_oe_i (dio_d2p_en ),
- .dio_to_periph_o (dio_p2d ),
-
- .dio_out_o,
- .dio_oe_o,
- .dio_in_i,
- .clk_i (clkmgr_clocks.clk_main_secure),
- .clk_aon_i (clkmgr_clocks.clk_aon_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]),
- .rst_aon_ni (rstmgr_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel])
- );
-
- padctrl u_padctrl (
-
- // Inter-module signals
- .tl_i(padctrl_tl_req),
- .tl_o(padctrl_tl_rsp),
-
- .mio_attr_o,
- .dio_attr_o,
- .clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel])
- );
-
- alert_handler #(
- .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed),
- .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm)
- ) u_alert_handler (
-
- // Interrupt
- .intr_classa_o (intr_alert_handler_classa),
- .intr_classb_o (intr_alert_handler_classb),
- .intr_classc_o (intr_alert_handler_classc),
- .intr_classd_o (intr_alert_handler_classd),
-
- // Inter-module signals
- .crashdump_o(alert_handler_crashdump),
- .tl_i(alert_handler_tl_req),
- .tl_o(alert_handler_tl_rsp),
- // TODO: wire this to TRNG
- .entropy_i ( 1'b0 ),
- // alert signals
- .alert_rx_o ( alert_rx ),
- .alert_tx_i ( alert_tx ),
- // escalation outputs
- .esc_rx_i ( esc_rx ),
- .esc_tx_o ( esc_tx ),
- .clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
+ .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i),
+ .otp_edn_o(),
+ .otp_edn_i('0),
+ .pwr_otp_i(pwrmgr_pwr_otp_req),
+ .pwr_otp_o(pwrmgr_pwr_otp_rsp),
+ .lc_otp_program_i('0),
+ .lc_otp_program_o(),
+ .lc_otp_token_i('0),
+ .lc_otp_token_o(),
+ .otp_lc_data_o(),
+ .lc_escalate_en_i(lc_ctrl_pkg::Off),
+ .lc_provision_wr_en_i(lc_ctrl_pkg::Off),
+ .lc_dft_en_i(lc_ctrl_pkg::Off),
+ .otp_keymgr_key_o(),
+ .flash_otp_key_i('0),
+ .flash_otp_key_o(),
+ .sram_otp_key_i('0),
+ .sram_otp_key_o(),
+ .otbn_otp_key_i('0),
+ .otbn_otp_key_o(),
+ .hw_cfg_o(),
+ .tl_i(otp_ctrl_tl_req),
+ .tl_o(otp_ctrl_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_io_div4_timers),
+ .rst_ni (rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
);
pwrmgr u_pwrmgr (
@@ -1007,22 +902,49 @@
.rst_io_div4_ni (rstmgr_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel])
);
- nmi_gen u_nmi_gen (
-
- // Interrupt
- .intr_esc0_o (intr_nmi_gen_esc0),
- .intr_esc1_o (intr_nmi_gen_esc1),
- .intr_esc2_o (intr_nmi_gen_esc2),
+ pinmux u_pinmux (
// Inter-module signals
- .nmi_rst_req_o(pwrmgr_rstreqs),
- .tl_i(nmi_gen_tl_req),
- .tl_o(nmi_gen_tl_rsp),
- // escalation signal inputs
- .esc_rx_o ( esc_rx[3:1] ),
- .esc_tx_i ( esc_tx[3:1] ),
+ .lc_pinmux_strap_i('0),
+ .lc_pinmux_strap_o(),
+ .dft_strap_test_o(),
+ .io_pok_i({pinmux_pkg::NIOPokSignals{1'b1}}),
+ .sleep_en_i(1'b0),
+ .aon_wkup_req_o(pwrmgr_wakeups),
+ .tl_i(pinmux_tl_req),
+ .tl_o(pinmux_tl_rsp),
+
+ .periph_to_mio_i (mio_d2p ),
+ .periph_to_mio_oe_i (mio_d2p_en ),
+ .mio_to_periph_o (mio_p2d ),
+
+ .mio_out_o,
+ .mio_oe_o,
+ .mio_in_i,
+
+ .periph_to_dio_i (dio_d2p ),
+ .periph_to_dio_oe_i (dio_d2p_en ),
+ .dio_to_periph_o (dio_p2d ),
+
+ .dio_out_o,
+ .dio_oe_o,
+ .dio_in_i,
.clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_aon_i (clkmgr_clocks.clk_aon_secure),
+ .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]),
+ .rst_aon_ni (rstmgr_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel])
+ );
+
+ padctrl u_padctrl (
+
+ // Inter-module signals
+ .tl_i(padctrl_tl_req),
+ .tl_o(padctrl_tl_rsp),
+
+ .mio_attr_o,
+ .dio_attr_o,
+ .clk_i (clkmgr_clocks.clk_main_secure),
+ .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel])
);
usbdev u_usbdev (
@@ -1081,26 +1003,105 @@
.rst_usb_48mhz_ni (rstmgr_resets.rst_usb_n[rstmgr_pkg::DomainAonSel])
);
- sensor_ctrl u_sensor_ctrl (
+ flash_ctrl u_flash_ctrl (
- // [2]: as
- // [3]: cg
- // [4]: gd
- // [5]: ts_hi
- // [6]: ts_lo
- // [7]: ls
- // [8]: ot
- .alert_tx_o ( alert_tx[8:2] ),
- .alert_rx_i ( alert_rx[8:2] ),
+ // Interrupt
+ .intr_prog_empty_o (intr_flash_ctrl_prog_empty),
+ .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
+ .intr_rd_full_o (intr_flash_ctrl_rd_full),
+ .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
+ .intr_op_done_o (intr_flash_ctrl_op_done),
+ .intr_op_error_o (intr_flash_ctrl_op_error),
// Inter-module signals
- .ast_alert_i(sensor_ctrl_ast_alert_req_i),
- .ast_alert_o(sensor_ctrl_ast_alert_rsp_o),
- .ast_status_i(sensor_ctrl_ast_status_i),
- .tl_i(sensor_ctrl_tl_req),
- .tl_o(sensor_ctrl_tl_rsp),
- .clk_i (clkmgr_clocks.clk_io_div4_secure),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel])
+ .flash_o(flash_ctrl_flash_req),
+ .flash_i(flash_ctrl_flash_rsp),
+ .otp_i(flash_ctrl_pkg::OTP_FLASH_DEFAULT),
+ .lc_provision_en_i(lc_ctrl_pkg::LC_TX_DEFAULT),
+ .lc_i(flash_ctrl_pkg::LC_FLASH_REQ_DEFAULT),
+ .lc_o(),
+ .edn_i(flash_ctrl_pkg::EDN_ENTROPY_DEFAULT),
+ .pwrmgr_i(pwrmgr_pwr_flash_req),
+ .pwrmgr_o(pwrmgr_pwr_flash_rsp),
+ .keymgr_o(flash_ctrl_keymgr),
+ .tl_i(flash_ctrl_tl_req),
+ .tl_o(flash_ctrl_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_main_infra),
+ .rst_ni (rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ rv_plic u_rv_plic (
+
+ // Inter-module signals
+ .tl_i(rv_plic_tl_req),
+ .tl_o(rv_plic_tl_rsp),
+
+ .intr_src_i (intr_vector),
+ .irq_o (irq_plic),
+ .irq_id_o (irq_id),
+ .msip_o (msip),
+ .clk_i (clkmgr_clocks.clk_main_secure),
+ .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ aes #(
+ .AES192Enable(1'b1),
+ .Masking(AesMasking),
+ .SBoxImpl(AesSBoxImpl),
+ .SecStartTriggerDelay(SecAesStartTriggerDelay),
+ .SecAllowForcingMasks(SecAesAllowForcingMasks),
+ .SeedClearing(aes_pkg::DefaultSeedClearing),
+ .SeedMasking(aes_pkg::DefaultSeedMasking),
+ .AlertAsyncOn({aes_reg_pkg::NumAlerts{1'b1}})
+ ) u_aes (
+
+ // [9]: ctrl_err_update
+ // [10]: ctrl_err_storage
+ .alert_tx_o ( alert_tx[10:9] ),
+ .alert_rx_i ( alert_rx[10:9] ),
+
+ // Inter-module signals
+ .idle_o(clkmgr_idle[0]),
+ .tl_i(aes_tl_req),
+ .tl_o(aes_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_main_aes),
+ .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ hmac u_hmac (
+
+ // Interrupt
+ .intr_hmac_done_o (intr_hmac_hmac_done),
+ .intr_fifo_empty_o (intr_hmac_fifo_empty),
+ .intr_hmac_err_o (intr_hmac_hmac_err),
+
+ // Inter-module signals
+ .idle_o(clkmgr_idle[1]),
+ .tl_i(hmac_tl_req),
+ .tl_o(hmac_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_main_hmac),
+ .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ kmac #(
+ .EnMasking(KmacEnMasking),
+ .ReuseShare(KmacReuseShare)
+ ) u_kmac (
+
+ // Interrupt
+ .intr_kmac_done_o (intr_kmac_kmac_done),
+ .intr_fifo_empty_o (intr_kmac_fifo_empty),
+ .intr_kmac_err_o (intr_kmac_kmac_err),
+
+ // Inter-module signals
+ .keymgr_key_i(keymgr_kmac_key),
+ .keymgr_kdf_i(keymgr_kmac_data_req),
+ .keymgr_kdf_o(keymgr_kmac_data_rsp),
+ .idle_o(clkmgr_idle[2]),
+ .tl_i(kmac_tl_req),
+ .tl_o(kmac_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_main_kmac),
+ .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
keymgr u_keymgr (
@@ -1109,10 +1110,10 @@
.intr_op_done_o (intr_keymgr_op_done),
.intr_err_o (intr_keymgr_err),
- // [9]: fault_err
- // [10]: operation_err
- .alert_tx_o ( alert_tx[10:9] ),
- .alert_rx_i ( alert_rx[10:9] ),
+ // [11]: fault_err
+ // [12]: operation_err
+ .alert_tx_o ( alert_tx[12:11] ),
+ .alert_rx_i ( alert_rx[12:11] ),
// Inter-module signals
.aes_key_o(),
@@ -1129,52 +1130,6 @@
.rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
- otp_ctrl #(
- .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
- .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm),
- .RndCnstKey(RndCnstOtpCtrlKey),
- .RndCnstDigestConst(RndCnstOtpCtrlDigestConst),
- .RndCnstDigestIV(RndCnstOtpCtrlDigestIV)
- ) u_otp_ctrl (
-
- // Interrupt
- .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
- .intr_otp_error_o (intr_otp_ctrl_otp_error),
-
- // [11]: otp_macro_failure
- // [12]: otp_check_failure
- .alert_tx_o ( alert_tx[12:11] ),
- .alert_rx_i ( alert_rx[12:11] ),
-
- // Inter-module signals
- .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
- .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i),
- .otp_edn_o(),
- .otp_edn_i('0),
- .pwr_otp_i(pwrmgr_pwr_otp_req),
- .pwr_otp_o(pwrmgr_pwr_otp_rsp),
- .lc_otp_program_i('0),
- .lc_otp_program_o(),
- .lc_otp_token_i('0),
- .lc_otp_token_o(),
- .otp_lc_data_o(),
- .lc_escalate_en_i(lc_ctrl_pkg::Off),
- .lc_provision_wr_en_i(lc_ctrl_pkg::Off),
- .lc_dft_en_i(lc_ctrl_pkg::Off),
- .otp_keymgr_key_o(),
- .flash_otp_key_i('0),
- .flash_otp_key_o(),
- .sram_otp_key_i('0),
- .sram_otp_key_o(),
- .otbn_otp_key_i('0),
- .otbn_otp_key_o(),
- .hw_cfg_o(),
- .tl_i(otp_ctrl_tl_req),
- .tl_o(otp_ctrl_tl_rsp),
- .clk_i (clkmgr_clocks.clk_io_div4_timers),
- .rst_ni (rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
- );
-
csrng #(
.SBoxImpl(CsrngSBoxImpl)
) u_csrng (
@@ -1257,6 +1212,51 @@
.rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
+ alert_handler #(
+ .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm)
+ ) u_alert_handler (
+
+ // Interrupt
+ .intr_classa_o (intr_alert_handler_classa),
+ .intr_classb_o (intr_alert_handler_classb),
+ .intr_classc_o (intr_alert_handler_classc),
+ .intr_classd_o (intr_alert_handler_classd),
+
+ // Inter-module signals
+ .crashdump_o(alert_handler_crashdump),
+ .tl_i(alert_handler_tl_req),
+ .tl_o(alert_handler_tl_rsp),
+ // TODO: wire this to TRNG
+ .entropy_i ( 1'b0 ),
+ // alert signals
+ .alert_rx_o ( alert_rx ),
+ .alert_tx_i ( alert_tx ),
+ // escalation outputs
+ .esc_rx_i ( esc_rx ),
+ .esc_tx_o ( esc_tx ),
+ .clk_i (clkmgr_clocks.clk_main_secure),
+ .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ nmi_gen u_nmi_gen (
+
+ // Interrupt
+ .intr_esc0_o (intr_nmi_gen_esc0),
+ .intr_esc1_o (intr_nmi_gen_esc1),
+ .intr_esc2_o (intr_nmi_gen_esc2),
+
+ // Inter-module signals
+ .nmi_rst_req_o(pwrmgr_rstreqs),
+ .tl_i(nmi_gen_tl_req),
+ .tl_o(nmi_gen_tl_rsp),
+ // escalation signal inputs
+ .esc_rx_o ( esc_rx[3:1] ),
+ .esc_tx_i ( esc_tx[3:1] ),
+ .clk_i (clkmgr_clocks.clk_main_secure),
+ .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ );
+
otbn #(
.RegFile(OtbnRegFile)
) u_otbn (
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index ae13197..3086406 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -24,7 +24,7 @@
/**
* Peripheral base address for gpio in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_GPIO_BASE_ADDR = 32'h40010000;
+ parameter int unsigned TOP_EARLGREY_GPIO_BASE_ADDR = 32'h40040000;
/**
* Peripheral size in bytes for gpio in top earlgrey.
@@ -34,7 +34,7 @@
/**
* Peripheral base address for spi_device in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_SPI_DEVICE_BASE_ADDR = 32'h40020000;
+ parameter int unsigned TOP_EARLGREY_SPI_DEVICE_BASE_ADDR = 32'h40050000;
/**
* Peripheral size in bytes for spi_device in top earlgrey.
@@ -42,19 +42,9 @@
parameter int unsigned TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for flash_ctrl in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_FLASH_CTRL_BASE_ADDR = 32'h40030000;
-
- /**
- * Peripheral size in bytes for flash_ctrl in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_FLASH_CTRL_SIZE_BYTES = 32'h1000;
-
- /**
* Peripheral base address for rv_timer in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_RV_TIMER_BASE_ADDR = 32'h40080000;
+ parameter int unsigned TOP_EARLGREY_RV_TIMER_BASE_ADDR = 32'h40100000;
/**
* Peripheral size in bytes for rv_timer in top earlgrey.
@@ -62,9 +52,109 @@
parameter int unsigned TOP_EARLGREY_RV_TIMER_SIZE_BYTES = 32'h1000;
/**
+ * Peripheral base address for sensor_ctrl in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR = 32'h40110000;
+
+ /**
+ * Peripheral size in bytes for sensor_ctrl in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for otp_ctrl in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_OTP_CTRL_BASE_ADDR = 32'h40130000;
+
+ /**
+ * Peripheral size in bytes for otp_ctrl in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_OTP_CTRL_SIZE_BYTES = 32'h4000;
+
+ /**
+ * Peripheral base address for pwrmgr in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_PWRMGR_BASE_ADDR = 32'h40400000;
+
+ /**
+ * Peripheral size in bytes for pwrmgr in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_PWRMGR_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for rstmgr in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_RSTMGR_BASE_ADDR = 32'h40410000;
+
+ /**
+ * Peripheral size in bytes for rstmgr in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_RSTMGR_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for clkmgr in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_CLKMGR_BASE_ADDR = 32'h40420000;
+
+ /**
+ * Peripheral size in bytes for clkmgr in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_CLKMGR_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for pinmux in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_PINMUX_BASE_ADDR = 32'h40460000;
+
+ /**
+ * Peripheral size in bytes for pinmux in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_PINMUX_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for padctrl in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_PADCTRL_BASE_ADDR = 32'h40470000;
+
+ /**
+ * Peripheral size in bytes for padctrl in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_PADCTRL_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for usbdev in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_USBDEV_BASE_ADDR = 32'h40500000;
+
+ /**
+ * Peripheral size in bytes for usbdev in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_USBDEV_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for flash_ctrl in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_FLASH_CTRL_BASE_ADDR = 32'h41000000;
+
+ /**
+ * Peripheral size in bytes for flash_ctrl in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_FLASH_CTRL_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for rv_plic in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_RV_PLIC_BASE_ADDR = 32'h41010000;
+
+ /**
+ * Peripheral size in bytes for rv_plic in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_RV_PLIC_SIZE_BYTES = 32'h1000;
+
+ /**
* Peripheral base address for aes in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_AES_BASE_ADDR = 32'h40110000;
+ parameter int unsigned TOP_EARLGREY_AES_BASE_ADDR = 32'h41100000;
/**
* Peripheral size in bytes for aes in top earlgrey.
@@ -74,7 +164,7 @@
/**
* Peripheral base address for hmac in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_HMAC_BASE_ADDR = 32'h40120000;
+ parameter int unsigned TOP_EARLGREY_HMAC_BASE_ADDR = 32'h41110000;
/**
* Peripheral size in bytes for hmac in top earlgrey.
@@ -92,109 +182,9 @@
parameter int unsigned TOP_EARLGREY_KMAC_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for rv_plic in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_RV_PLIC_BASE_ADDR = 32'h40090000;
-
- /**
- * Peripheral size in bytes for rv_plic in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_RV_PLIC_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for pinmux in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_PINMUX_BASE_ADDR = 32'h40070000;
-
- /**
- * Peripheral size in bytes for pinmux in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_PINMUX_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for padctrl in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_PADCTRL_BASE_ADDR = 32'h40160000;
-
- /**
- * Peripheral size in bytes for padctrl in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_PADCTRL_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for alert_handler in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR = 32'h411b0000;
-
- /**
- * Peripheral size in bytes for alert_handler in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for pwrmgr in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_PWRMGR_BASE_ADDR = 32'h400A0000;
-
- /**
- * Peripheral size in bytes for pwrmgr in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_PWRMGR_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for rstmgr in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_RSTMGR_BASE_ADDR = 32'h400B0000;
-
- /**
- * Peripheral size in bytes for rstmgr in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_RSTMGR_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for clkmgr in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_CLKMGR_BASE_ADDR = 32'h400C0000;
-
- /**
- * Peripheral size in bytes for clkmgr in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_CLKMGR_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for nmi_gen in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_NMI_GEN_BASE_ADDR = 32'h411c0000;
-
- /**
- * Peripheral size in bytes for nmi_gen in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_NMI_GEN_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for usbdev in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_USBDEV_BASE_ADDR = 32'h40150000;
-
- /**
- * Peripheral size in bytes for usbdev in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_USBDEV_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for sensor_ctrl in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR = 32'h40170000;
-
- /**
- * Peripheral size in bytes for sensor_ctrl in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES = 32'h1000;
-
- /**
* Peripheral base address for keymgr in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_KEYMGR_BASE_ADDR = 32'h401a0000;
+ parameter int unsigned TOP_EARLGREY_KEYMGR_BASE_ADDR = 32'h41130000;
/**
* Peripheral size in bytes for keymgr in top earlgrey.
@@ -202,16 +192,6 @@
parameter int unsigned TOP_EARLGREY_KEYMGR_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for otp_ctrl in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_OTP_CTRL_BASE_ADDR = 32'h401b0000;
-
- /**
- * Peripheral size in bytes for otp_ctrl in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_OTP_CTRL_SIZE_BYTES = 32'h4000;
-
- /**
* Peripheral base address for csrng in top earlgrey.
*/
parameter int unsigned TOP_EARLGREY_CSRNG_BASE_ADDR = 32'h41150000;
@@ -252,9 +232,29 @@
parameter int unsigned TOP_EARLGREY_EDN1_SIZE_BYTES = 32'h1000;
/**
+ * Peripheral base address for alert_handler in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR = 32'h411b0000;
+
+ /**
+ * Peripheral size in bytes for alert_handler in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for nmi_gen in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_NMI_GEN_BASE_ADDR = 32'h411c0000;
+
+ /**
+ * Peripheral size in bytes for nmi_gen in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_NMI_GEN_SIZE_BYTES = 32'h1000;
+
+ /**
* Peripheral base address for otbn in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_OTBN_BASE_ADDR = 32'h50000000;
+ parameter int unsigned TOP_EARLGREY_OTBN_BASE_ADDR = 32'h411d0000;
/**
* Peripheral size in bytes for otbn in top earlgrey.
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
index 573464b..929aec2 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
@@ -14,19 +14,6 @@
package top_earlgrey_rnd_cnst_pkg;
////////////////////////////////////////////
- // alert_handler
- ////////////////////////////////////////////
- // Compile-time random bits for initial LFSR seed
- parameter alert_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = {
- 32'h5DEF7861
- };
-
- // Compile-time random permutation for LFSR output
- parameter alert_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = {
- 160'h5F00C4CAFD73FC4AC479A61068375F38956D84B3
- };
-
- ////////////////////////////////////////////
// otp_ctrl
////////////////////////////////////////////
// Compile-time random bits for initial LFSR seed
@@ -58,4 +45,17 @@
256'h0D5AB25561AF49C696466A983E5346826A43628219E5A91389B9FE0D3B818E46
};
+ ////////////////////////////////////////////
+ // alert_handler
+ ////////////////////////////////////////////
+ // Compile-time random bits for initial LFSR seed
+ parameter alert_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = {
+ 32'h5DEF7861
+ };
+
+ // Compile-time random permutation for LFSR output
+ parameter alert_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = {
+ 160'h5F00C4CAFD73FC4AC479A61068375F38956D84B3
+ };
+
endpackage : top_earlgrey_rnd_cnst_pkg
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index e7b7b2e..e335b22 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -49,7 +49,7 @@
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_GPIO_BASE_ADDR 0x40010000u
+#define TOP_EARLGREY_GPIO_BASE_ADDR 0x40040000u
/**
* Peripheral size for gpio in top earlgrey.
@@ -67,7 +67,7 @@
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40020000u
+#define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40050000u
/**
* Peripheral size for spi_device in top earlgrey.
@@ -80,30 +80,12 @@
#define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for flash_ctrl in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_FLASH_CTRL_BASE_ADDR 0x40030000u
-
-/**
- * Peripheral size for flash_ctrl in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_FLASH_CTRL_BASE_ADDR and
- * `TOP_EARLGREY_FLASH_CTRL_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_FLASH_CTRL_SIZE_BYTES 0x1000u
-
-/**
* Peripheral base address for rv_timer in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_RV_TIMER_BASE_ADDR 0x40080000u
+#define TOP_EARLGREY_RV_TIMER_BASE_ADDR 0x40100000u
/**
* Peripheral size for rv_timer in top earlgrey.
@@ -116,12 +98,192 @@
#define TOP_EARLGREY_RV_TIMER_SIZE_BYTES 0x1000u
/**
+ * Peripheral base address for sensor_ctrl in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR 0x40110000u
+
+/**
+ * Peripheral size for sensor_ctrl in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR and
+ * `TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for otp_ctrl in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_OTP_CTRL_BASE_ADDR 0x40130000u
+
+/**
+ * Peripheral size for otp_ctrl in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_OTP_CTRL_BASE_ADDR and
+ * `TOP_EARLGREY_OTP_CTRL_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_OTP_CTRL_SIZE_BYTES 0x4000u
+
+/**
+ * Peripheral base address for pwrmgr in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_PWRMGR_BASE_ADDR 0x40400000u
+
+/**
+ * Peripheral size for pwrmgr in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_PWRMGR_BASE_ADDR and
+ * `TOP_EARLGREY_PWRMGR_BASE_ADDR + TOP_EARLGREY_PWRMGR_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_PWRMGR_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for rstmgr in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_RSTMGR_BASE_ADDR 0x40410000u
+
+/**
+ * Peripheral size for rstmgr in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_RSTMGR_BASE_ADDR and
+ * `TOP_EARLGREY_RSTMGR_BASE_ADDR + TOP_EARLGREY_RSTMGR_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_RSTMGR_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for clkmgr in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_CLKMGR_BASE_ADDR 0x40420000u
+
+/**
+ * Peripheral size for clkmgr in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_CLKMGR_BASE_ADDR and
+ * `TOP_EARLGREY_CLKMGR_BASE_ADDR + TOP_EARLGREY_CLKMGR_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_CLKMGR_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for pinmux in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_PINMUX_BASE_ADDR 0x40460000u
+
+/**
+ * Peripheral size for pinmux in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_PINMUX_BASE_ADDR and
+ * `TOP_EARLGREY_PINMUX_BASE_ADDR + TOP_EARLGREY_PINMUX_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_PINMUX_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for padctrl in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_PADCTRL_BASE_ADDR 0x40470000u
+
+/**
+ * Peripheral size for padctrl in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_PADCTRL_BASE_ADDR and
+ * `TOP_EARLGREY_PADCTRL_BASE_ADDR + TOP_EARLGREY_PADCTRL_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_PADCTRL_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for usbdev in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40500000u
+
+/**
+ * Peripheral size for usbdev in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_USBDEV_BASE_ADDR and
+ * `TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for flash_ctrl in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_FLASH_CTRL_BASE_ADDR 0x41000000u
+
+/**
+ * Peripheral size for flash_ctrl in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_FLASH_CTRL_BASE_ADDR and
+ * `TOP_EARLGREY_FLASH_CTRL_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_FLASH_CTRL_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for rv_plic in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_RV_PLIC_BASE_ADDR 0x41010000u
+
+/**
+ * Peripheral size for rv_plic in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_RV_PLIC_BASE_ADDR and
+ * `TOP_EARLGREY_RV_PLIC_BASE_ADDR + TOP_EARLGREY_RV_PLIC_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x1000u
+
+/**
* Peripheral base address for aes in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_AES_BASE_ADDR 0x40110000u
+#define TOP_EARLGREY_AES_BASE_ADDR 0x41100000u
/**
* Peripheral size for aes in top earlgrey.
@@ -139,7 +301,7 @@
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_HMAC_BASE_ADDR 0x40120000u
+#define TOP_EARLGREY_HMAC_BASE_ADDR 0x41110000u
/**
* Peripheral size for hmac in top earlgrey.
@@ -170,192 +332,12 @@
#define TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for rv_plic in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_RV_PLIC_BASE_ADDR 0x40090000u
-
-/**
- * Peripheral size for rv_plic in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_RV_PLIC_BASE_ADDR and
- * `TOP_EARLGREY_RV_PLIC_BASE_ADDR + TOP_EARLGREY_RV_PLIC_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for pinmux in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_PINMUX_BASE_ADDR 0x40070000u
-
-/**
- * Peripheral size for pinmux in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_PINMUX_BASE_ADDR and
- * `TOP_EARLGREY_PINMUX_BASE_ADDR + TOP_EARLGREY_PINMUX_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_PINMUX_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for padctrl in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_PADCTRL_BASE_ADDR 0x40160000u
-
-/**
- * Peripheral size for padctrl in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_PADCTRL_BASE_ADDR and
- * `TOP_EARLGREY_PADCTRL_BASE_ADDR + TOP_EARLGREY_PADCTRL_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_PADCTRL_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for alert_handler in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x411b0000u
-
-/**
- * Peripheral size for alert_handler in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR and
- * `TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR + TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for pwrmgr in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_PWRMGR_BASE_ADDR 0x400A0000u
-
-/**
- * Peripheral size for pwrmgr in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_PWRMGR_BASE_ADDR and
- * `TOP_EARLGREY_PWRMGR_BASE_ADDR + TOP_EARLGREY_PWRMGR_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_PWRMGR_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for rstmgr in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_RSTMGR_BASE_ADDR 0x400B0000u
-
-/**
- * Peripheral size for rstmgr in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_RSTMGR_BASE_ADDR and
- * `TOP_EARLGREY_RSTMGR_BASE_ADDR + TOP_EARLGREY_RSTMGR_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_RSTMGR_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for clkmgr in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_CLKMGR_BASE_ADDR 0x400C0000u
-
-/**
- * Peripheral size for clkmgr in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_CLKMGR_BASE_ADDR and
- * `TOP_EARLGREY_CLKMGR_BASE_ADDR + TOP_EARLGREY_CLKMGR_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_CLKMGR_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for nmi_gen in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_NMI_GEN_BASE_ADDR 0x411c0000u
-
-/**
- * Peripheral size for nmi_gen in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_NMI_GEN_BASE_ADDR and
- * `TOP_EARLGREY_NMI_GEN_BASE_ADDR + TOP_EARLGREY_NMI_GEN_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_NMI_GEN_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for usbdev in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40150000u
-
-/**
- * Peripheral size for usbdev in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_USBDEV_BASE_ADDR and
- * `TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for sensor_ctrl in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR 0x40170000u
-
-/**
- * Peripheral size for sensor_ctrl in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR and
- * `TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES 0x1000u
-
-/**
* Peripheral base address for keymgr in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_KEYMGR_BASE_ADDR 0x401a0000u
+#define TOP_EARLGREY_KEYMGR_BASE_ADDR 0x41130000u
/**
* Peripheral size for keymgr in top earlgrey.
@@ -368,24 +350,6 @@
#define TOP_EARLGREY_KEYMGR_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for otp_ctrl in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_OTP_CTRL_BASE_ADDR 0x401b0000u
-
-/**
- * Peripheral size for otp_ctrl in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_OTP_CTRL_BASE_ADDR and
- * `TOP_EARLGREY_OTP_CTRL_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_OTP_CTRL_SIZE_BYTES 0x4000u
-
-/**
* Peripheral base address for csrng in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -458,12 +422,48 @@
#define TOP_EARLGREY_EDN1_SIZE_BYTES 0x1000u
/**
+ * Peripheral base address for alert_handler in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x411b0000u
+
+/**
+ * Peripheral size for alert_handler in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR and
+ * `TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR + TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for nmi_gen in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_NMI_GEN_BASE_ADDR 0x411c0000u
+
+/**
+ * Peripheral size for nmi_gen in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_NMI_GEN_BASE_ADDR and
+ * `TOP_EARLGREY_NMI_GEN_BASE_ADDR + TOP_EARLGREY_NMI_GEN_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_NMI_GEN_SIZE_BYTES 0x1000u
+
+/**
* Peripheral base address for otbn in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_OTBN_BASE_ADDR 0x50000000u
+#define TOP_EARLGREY_OTBN_BASE_ADDR 0x411d0000u
/**
* Peripheral size for otbn in top earlgrey.
