| commit | cc3772d62dfeba973c535f8c0b7c3640770e4233 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Mon Nov 23 11:30:07 2020 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Tue Nov 24 08:15:07 2020 +0000 |
| tree | 4c615ca4fadb5dad465e8306d62d3a2e5e2880bd | |
| parent | 7075a02b59799a4a743d05611f250d4915d36ce5 [diff] |
Knock OTBN memory range from 4MiB to 256KiB This should make it a bit easier to fit all the peripherals together in the memory map. There's still a 64KiB address space for each memory (they're currently 4KiB in size), so we can grow by a factor of 16 without running out of addresses. If we're slapping down more SRAM than that, our address map will be the least of our worries! Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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