[entropy_src/dv] dv doc, testplan, checklist, V1
Signed-off-by: Steve Nelson <steve.nelson@wdc.com>
diff --git a/hw/ip/entropy_src/data/entropy_src.prj.hjson b/hw/ip/entropy_src/data/entropy_src.prj.hjson
index dbf19ac..07b56dd 100644
--- a/hw/ip/entropy_src/data/entropy_src.prj.hjson
+++ b/hw/ip/entropy_src/data/entropy_src.prj.hjson
@@ -10,5 +10,5 @@
version: "0.5",
life_stage: "L1",
design_stage: "D1",
- verification_stage: "V0",
+ verification_stage: "V1",
}
diff --git a/hw/ip/entropy_src/data/entropy_src_testplan.hjson b/hw/ip/entropy_src/data/entropy_src_testplan.hjson
index ed01629..27a06a9 100644
--- a/hw/ip/entropy_src/data/entropy_src_testplan.hjson
+++ b/hw/ip/entropy_src/data/entropy_src_testplan.hjson
@@ -20,6 +20,18 @@
desc: '''
Verify ability to access entropy register based on value of efuse input
Verify es_regen bit enables/disables write access to control registers
+ Verify registers at End-Of-Test
+ '''
+ milestone: V2
+ tests: []
+ }
+ {
+ name: firmware_mode
+ desc: '''
+ Verify health_checks aren't active
+ Verify bypass active
+ Verify read FIFO
+ - Random FIFO depths
'''
milestone: V2
tests: []
@@ -27,10 +39,11 @@
{
name: lfsr_mode
desc: '''
- Verify LFSR entropy
- - Various seeds
- - Various FIFO depths
- Verify rng activity does not affect lfsr operation.
+ Verify LFSR entropy matches predicted
+ - Random seeds
+ - Random rng activity
+ - Random rates
+ Verify FIPS bits match predicted
'''
milestone: V2
tests: []
@@ -39,23 +52,36 @@
name: rng_mode
desc: '''
Verify rng entropy
- - Various clk speeds
- - Various FIFO depths
+ - Random FIFO depths
+ - Random rates
Verify rng single_bit_mode for all bit_selector values
+ Verify FIPS bits match predicted
'''
milestone: V2
- tests: ["entropy_src_rng"]
+ tests: []
}
{
name: health_checks
desc: '''
- Verify AdaptProp health check behaves as predicted
- Verify RepCnt health check behaves as predicted
- Verify Bucket health check behaves as predicted
- Verify Markov health check behaves as predicted
+ Verify AdaptProp, RepCnt, RepCntSym, Bucket, Markov health check results match predicted.
+ - Generate passing and failing raw entropy streams
+ - Random window sizes
+ - Default and random hi/lo bypass/fips thresholds
+ - Enables/fail counts/clears
+ Verify hi/lo bypass/fips watermarks
Verify External health check behaves as predicted
- Various thresholds, clears, enables
- Verify alerts
+ - Verify outputs match internal reg values/entropy bus
+ - Pulse inputs and verify captured
+ Verify health testing stops when no demand for entropy
+ '''
+ milestone: V2
+ tests: []
+ }
+ {
+ name: conditioning
+ desc: '''
+ Verify genbits in bypass mode as predicted.
+ Verify genbits after shah3 conditioning as predicted.
'''
milestone: V2
tests: []
@@ -63,16 +89,36 @@
{
name: interrupts
desc: '''
- Verify all entropy_src interrupts assert/clear when expected.'''
+ Verify es_entropy_valid interrupt asserts as predicted.
+ Verify es_health_test_failed interrupt asserts as predicted.
+ Verify es_fifo_err interrupt asserts as predicted.
+ '''
+ milestone: V2
+ tests: []
+ }
+ {
+ name: alerts
+ desc: '''
+ Verify es_alert_count_met asserts as expected.
+ '''
milestone: V2
tests: []
}
{
name: stress_all
desc: '''
- Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel.'''
+ Combine the individual test points while injecting TL errors and running CSR tests in parallel.
+ '''
milestone: V2
tests: ["entropy_src_stress_all"]
}
+ {
+ name: fifo_errs
+ desc: '''
+ Verify they never occur with asserts
+ '''
+ milestone: V2
+ tests: []
+ }
]
}
diff --git a/hw/ip/entropy_src/doc/checklist.md b/hw/ip/entropy_src/doc/checklist.md
index 18fae70..d9c18dd 100644
--- a/hw/ip/entropy_src/doc/checklist.md
+++ b/hw/ip/entropy_src/doc/checklist.md
@@ -127,11 +127,11 @@
Regression | [FPV_REGRESSION_SETUP][] | N/A |
Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done |
Code Quality | [TB_LINT_SETUP][] | Done |
-Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A |
-Review | [DESIGN_SPEC_REVIEWED][] | Not Started |
-Review | [DV_PLAN_REVIEWED][] | Not Started |
-Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?)
-Review | [V2_CHECKLIST_SCOPED][] | Not Started |
+Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done | AES
+Review | [DESIGN_SPEC_REVIEWED][] | Done |
+Review | [DV_PLAN_REVIEWED][] | Done |
+Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug)
+Review | [V2_CHECKLIST_SCOPED][] | Done |
[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_plan_completed" >}}
diff --git a/hw/ip/entropy_src/doc/dv/index.md b/hw/ip/entropy_src/doc/dv/index.md
index 31bb863..07b7265 100644
--- a/hw/ip/entropy_src/doc/dv/index.md
+++ b/hw/ip/entropy_src/doc/dv/index.md
@@ -30,6 +30,8 @@
* [TileLink host interface]({{< relref "hw/dv/sv/tl_agent/README.md" >}})
* ENTROPY_SRC IOs
* Interrupts ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})
+* Alerts ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})
+* Devmode ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})
### Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
@@ -52,6 +54,12 @@
which provides the ability to drive and independently monitor random traffic via
TL host interface into ENTROPY_SRC device.
+### Rng_agent
+Entropy_src testbench instantiates this PUSH_pull_agent({{< relref "hw/dv/sv/push_pull_agent/README.md" >}}) which models the rng source.
+
+### Csrng_agent
+Entropy_src testbench instantiates this push_PULL_agent({{< relref "hw/dv/sv/push_pull_agent/README.md" >}}) which models the csrng module.
+
### UVM RAL Model
The ENTROPY_SRC RAL model is created with the [`ralgen`]({{< relref "hw/dv/tools/ralgen/README.md" >}}) FuseSoC generator script automatically when the simulation is at the build stage.
@@ -75,7 +83,8 @@
#### Scoreboard
The `entropy_src_scoreboard` is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
-* tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of Tilelink address channel and data channel respectively
+* tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of Tilelink address channel and data channel respectively
+* rng_fifo, csrng_fifo: The rng_fifo provides transaction items from the predictor and the csrng_fifo provide actual post-entropy_src transaction items to compare
#### Assertions
* TLUL assertions: The `tb/entropy_src_bind.sv` binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}}) to the IP to ensure TileLink interface protocol compliance.
