[entropy_src/rtl] review round2 changes
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/entropy_src/rtl/entropy_src.sv b/hw/ip/entropy_src/rtl/entropy_src.sv
index 1269dd1..c731016 100755
--- a/hw/ip/entropy_src/rtl/entropy_src.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src.sv
@@ -6,7 +6,7 @@
module entropy_src import entropy_src_pkg::*; #(
- parameter int unsigned EsFifoDepth = 16
+ parameter int unsigned EsFifoDepth = 2
) (
input clk_i,
input rst_ni,
@@ -26,10 +26,13 @@
output entropy_src_rng_req_t entropy_src_rng_o,
input entropy_src_rng_rsp_t entropy_src_rng_i,
+ // Alerts
+ input prim_alert_pkg::alert_rx_t alert_rx_i,
+ output prim_alert_pkg::alert_tx_t alert_tx_o,
+
// Interrupts
output logic es_entropy_valid_o,
- output logic es_rct_failed_o,
- output logic es_apt_failed_o,
+ output logic es_health_test_failed_o,
output logic es_fifo_err_o
);
@@ -38,6 +41,8 @@
entropy_src_reg2hw_t reg2hw;
entropy_src_hw2reg_t hw2reg;
+ logic alert_event;
+
entropy_src_reg_top u_reg (
.clk_i,
.rst_ni,
@@ -65,10 +70,24 @@
.entropy_src_rng_o,
.entropy_src_rng_i,
+ .alert_event_o(alert_event),
+
.es_entropy_valid_o,
- .es_rct_failed_o,
- .es_apt_failed_o,
+ .es_health_test_failed_o,
.es_fifo_err_o
);
+ prim_alert_sender #(
+ .AsyncOn(1'b0) // TODO: does this need to be AsyncOn
+ ) u_alert_sender_i (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
+ .alert_i ( alert_event ),
+ .alert_rx_i ( alert_rx_i ),
+ .alert_tx_o ( alert_tx_o )
+ );
+
+ // Outputs should have a known value after reset
+ `ASSERT_KNOWN(AlertTxKnown, alert_tx_o)
+
endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv
new file mode 100755
index 0000000..e89c17d
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv
@@ -0,0 +1,83 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src adaptive proportion health test module
+//
+
+module entropy_src_adaptp_ht #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned RngBusWidth = 4
+) (
+ input clk_i,
+ input rst_ni,
+
+ // ins req interface
+ input logic [RngBusWidth-1:0] entropy_bit_i,
+ input logic entropy_bit_vld_i,
+ input logic clear_i,
+ input logic active_i,
+ input logic [RegWidth-1:0] thresh_hi_i,
+ input logic [RegWidth-1:0] thresh_lo_i,
+ input logic [RegWidth-1:0] window_i,
+ output logic [RegWidth-1:0] test_cnt_o,
+ output logic test_done_pulse_o,
+ output logic test_fail_hi_pulse_o,
+ output logic test_fail_lo_pulse_o
+);
+
+ // signals
+ logic [RegWidth-1:0] column_cnt;
+ logic window_cntr_wrap;
+
+ // flops
+ logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
+ logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ window_cntr_q <= '0;
+ test_cnt_q <= '0;
+ end else begin
+ window_cntr_q <= window_cntr_d;
+ test_cnt_q <= test_cnt_d;
+ end
+
+
+ // Adaptive Proportion Test
+ //
+ // Test operation
+ // This is an approved modification of the NIST Adaptive Proportion test in that
+ // instead of counting the first sampled value (1'b1 or 1'b0), it will count
+ // only the 1's on all four bit streams and accumulate for the during of the
+ // window size (W) of the test.
+
+
+ // Number of ones per column
+ assign column_cnt = entropy_bit_i[3]+entropy_bit_i[2]+entropy_bit_i[1]+entropy_bit_i[0];
+
+ // Window wrap condition
+ assign window_cntr_wrap = (window_cntr_q == window_i);
+
+ // Window counter
+ assign window_cntr_d =
+ clear_i ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (window_cntr_q+1) :
+ window_cntr_q;
+
+ // Test event counter
+ assign test_cnt_d =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (test_cnt_q+column_cnt) :
+ test_cnt_q;
+
+ // the pulses will be only one clock in length
+ assign test_fail_hi_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > thresh_hi_i);
+ assign test_fail_lo_pulse_o = active_i && window_cntr_wrap && (test_cnt_q < thresh_lo_i);
+ assign test_done_pulse_o = window_cntr_wrap;
+ assign test_cnt_o = test_cnt_q;
+
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_align_sm.sv b/hw/ip/entropy_src/rtl/entropy_src_align_sm.sv
deleted file mode 100755
index 0a93d4f..0000000
--- a/hw/ip/entropy_src/rtl/entropy_src_align_sm.sv
+++ /dev/null
@@ -1,140 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: entropy_src byte allignment of entropy bits state machine module
-//
-
-module entropy_src_align_sm (
- input clk_i,
- input rst_ni,
-
- // ins req interface
- input logic es_enable_i,
- input logic es_health_fail_i,
- input logic upstr_fifo_vld_i,
- input logic dwstr_fifo_not_full_i,
- output logic dwstr_fifo_push_o,
- output logic es_load_byte0_o,
- output logic es_load_byte1_o,
- output logic es_load_byte2_o,
- output logic es_load_byte3_o,
- input logic other_dwstr_fifo_empty_i,
- output logic dwstr_fifo_swap_o,
- output logic dwstr_fifo_clr_o
-);
-
-
- typedef enum logic [3:0] {
- IDLE = 4'h0,
- BYTE0 = 4'h1,
- BYTE1 = 4'h2,
- BYTE2 = 4'h3,
- BYTE3 = 4'h4,
- PUSH = 4'h5,
- FCHK = 4'h6,
- SWAP = 4'h7,
- BAIL = 4'h8
- } state_e;
-
- state_e state_q, state_d;
-
-
- always_ff @(posedge clk_i or negedge rst_ni)
- if (!rst_ni) begin
- state_q <= IDLE;
- end else begin
- state_q <= state_d;
- end
-
-
- always_comb begin
- state_d = state_q;
- dwstr_fifo_push_o = 1'b0;
- es_load_byte0_o = 1'b0;
- es_load_byte1_o = 1'b0;
- es_load_byte2_o = 1'b0;
- es_load_byte3_o = 1'b0;
- dwstr_fifo_clr_o = 1'b0;
- dwstr_fifo_swap_o = 1'b0;
- unique case (state_q)
-// case (state_q)
- IDLE: begin
- if (es_enable_i) begin
- state_d = BYTE0;
- end
- end
- BYTE0: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (upstr_fifo_vld_i) begin
- es_load_byte0_o = 1'b1;
- state_d = BYTE1;
- end else begin
- state_d = BYTE0;
- end
- end
- BYTE1: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (upstr_fifo_vld_i) begin
- es_load_byte1_o = 1'b1;
- state_d = BYTE2;
- end else begin
- state_d = BYTE1;
- end
- end
- BYTE2: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (upstr_fifo_vld_i) begin
- es_load_byte2_o = 1'b1;
- state_d = BYTE3;
- end else begin
- state_d = BYTE2;
- end
- end
- BYTE3: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (upstr_fifo_vld_i) begin
- es_load_byte3_o = 1'b1;
- state_d = PUSH;
- end else begin
- state_d = BYTE3;
- end
- end
- PUSH: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (dwstr_fifo_not_full_i) begin
- dwstr_fifo_push_o = 1'b1;
- state_d = FCHK;
- end else begin
- state_d = PUSH;
- end
- end
- FCHK: begin
- if (!dwstr_fifo_not_full_i) begin
- state_d = SWAP;
- end else begin
- state_d = IDLE;
- end
- end
- SWAP: begin
- if (other_dwstr_fifo_empty_i) begin
- dwstr_fifo_swap_o = 1'b1;
- state_d = IDLE;
- end else begin
- state_d = SWAP;
- end
- end
- BAIL: begin
- dwstr_fifo_clr_o = 1'b1;
- state_d = IDLE;
- end
- default: state_d = IDLE;
- endcase
- end
-
-endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv
new file mode 100755
index 0000000..bb29249
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv
@@ -0,0 +1,100 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src bucket health test module
+//
+
+module entropy_src_bucket_ht #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned RngBusWidth = 4
+) (
+ input clk_i,
+ input rst_ni,
+
+ // ins req interface
+ input logic [RngBusWidth-1:0] entropy_bit_i,
+ input logic entropy_bit_vld_i,
+ input logic clear_i,
+ input logic active_i,
+ input logic [RegWidth-1:0] thresh_i,
+ input logic [RegWidth-1:0] window_i,
+ output logic [RegWidth-1:0] test_cnt_o,
+ output logic test_done_pulse_o,
+ output logic test_fail_pulse_o
+);
+
+ localparam int NUM_BINS = 2**RngBusWidth;
+
+ // signals
+ logic window_cntr_wrap;
+ logic [NUM_BINS-1:0] bin_incr;
+ logic [NUM_BINS-1:0] bin_cnt_exceeds_thresh;
+
+ // flops
+ logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
+ logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
+ logic [RegWidth-1:0] bin_cntr_q[NUM_BINS], bin_cntr_d[NUM_BINS];
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ window_cntr_q <= '0;
+ test_cnt_q <= '0;
+ bin_cntr_q <= {10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,
+ 10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,10'b0};
+ end else begin
+ window_cntr_q <= window_cntr_d;
+ test_cnt_q <= test_cnt_d;
+ bin_cntr_q <= bin_cntr_d;
+ end
+
+
+ // Bucket Test
+ //
+ // Test operation
+ // This test will look at 4 bit symbols and increment one of sixteen
+ // counters, or buckets, to show a histogram of the data stream.
+ // An error will occur if one of the counters reaches the thresh
+ // value.
+
+
+ // Analyze the incoming symbols
+
+ genvar i;
+ generate
+ for (i = 0; i < NUM_BINS; i = i + 1) begin : g_symbol_match
+ // set the bin incrementer if the symbol matches that bin
+ assign bin_incr[i] = entropy_bit_vld_i && (entropy_bit_i == i);
+ // use the bin incrementer to increase the bin total count
+ assign bin_cntr_d[i] = window_cntr_wrap ? '0 :
+ ((active_i && bin_incr[i]) ? (bin_cntr_q[i]+1) : bin_cntr_q[i]);
+ // use the bin incrementer to increase the bin total count
+ assign bin_cnt_exceeds_thresh[i] = (bin_cntr_q[i] > thresh_i);
+ end
+ endgenerate
+
+
+ // Window wrap condition
+ assign window_cntr_wrap = (window_cntr_q == window_i);
+
+ // Window counter
+ assign window_cntr_d =
+ clear_i ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (window_cntr_q+1) :
+ window_cntr_q;
+
+ // Test event counter
+ assign test_cnt_d =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i && (|bin_cnt_exceeds_thresh) ? (test_cnt_q+1) :
+ test_cnt_q;
+
+ // the pulses will be only one clock in length
+ assign test_fail_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > '0);
+ assign test_done_pulse_o = window_cntr_wrap;
+ assign test_cnt_o = test_cnt_q;
+
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv b/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv
new file mode 100755
index 0000000..4846829
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv
@@ -0,0 +1,40 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src counter register module
+//
+
+module entropy_src_cntr_reg #(
+ parameter int unsigned RegWidth = 16
+) (
+ input logic clk_i,
+ input logic rst_ni,
+
+ // functional interface
+ input logic clear_i,
+ input logic active_i,
+ input logic event_i,
+ output logic [RegWidth-1:0] value_o
+);
+
+ // signals
+
+ // flops
+ logic [RegWidth-1:0] event_cntr_q, event_cntr_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ event_cntr_q <= '0;
+ end else begin
+ event_cntr_q <= event_cntr_d;
+ end
+
+ // counter will not wrap when full value is reached
+ assign event_cntr_d = (!active_i || clear_i) ? '0 :
+ (event_i && (~event_cntr_q != '0)) ? event_cntr_q+1 :
+ event_cntr_q;
+
+ assign value_o = event_cntr_q;
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv
index 8c8d601..c144bca 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_core.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -6,7 +6,7 @@
//
module entropy_src_core import entropy_src_pkg::*; #(
- parameter int unsigned EsFifoDepth = 16
+ parameter int unsigned EsFifoDepth = 2
) (
input clk_i,
input rst_ni,
@@ -26,124 +26,213 @@
output entropy_src_rng_req_t entropy_src_rng_o,
input entropy_src_rng_rsp_t entropy_src_rng_i,
+ output logic alert_event_o,
+
output logic es_entropy_valid_o,
- output logic es_rct_failed_o,
- output logic es_apt_failed_o,
+ output logic es_health_test_failed_o,
output logic es_fifo_err_o
);
import entropy_src_reg_pkg::*;
- localparam int unsigned PostHTDepth = $clog2(EsFifoDepth);
+ localparam int unsigned Clog2EsFifoDepth = $clog2(EsFifoDepth);
+ localparam int unsigned PostHTWidth = 64;
localparam int unsigned RngBusWidth = 4;
+ localparam int unsigned HalfRegWidth = 16;
+ localparam int unsigned FullRegWidth = 32;
+ localparam int unsigned EigthRegWidth = 4;
+ localparam int unsigned SeedLen = 384;
// signals
logic [RngBusWidth-1:0] lfsr_value;
logic [RngBusWidth-1:0] seed_value;
logic load_seed;
logic es_enable;
- logic es_enable_dig;
+ logic es_enable_lfsr;
logic es_enable_rng;
logic rng_bit_en;
logic [1:0] rng_bit_sel;
- logic lfsr_enable;
- logic esentropy_rd_pls;
+ logic lfsr_incr;
+ logic sw_es_rd_pulse;
logic event_es_entropy_valid;
- logic event_es_apt_failed;
- logic event_es_rct_failed;
-// logic event_es_rng_bits_err;
+ logic event_es_health_test_failed;
logic event_es_fifo_err;
logic [15:0] es_rate;
- logic es_rate_entropy_valid;
- logic es_rate_entropy_valid_en;
- logic [2:0] es_fifo_thresh;
- logic es_rng_src_ok;
+ logic es_rate_entropy_pulse;
+ logic es_rng_src_ok;
+ logic [RngBusWidth-1:0] es_rng_bus;
- logic sfifo_esdig_push;
- logic sfifo_esdig_pop;
- logic sfifo_esdig_clr;
- logic [RngBusWidth-1:0] sfifo_esdig_wdata;
- logic [RngBusWidth-1:0] sfifo_esdig_rdata;
- logic [2:0] sfifo_esdig_depth;
- logic sfifo_esdig_not_full;
- logic sfifo_esdig_not_empty;
- logic sfifo_esdig_err;
+ logic [RngBusWidth-1:0] sfifo_esrng_wdata;
+ logic [RngBusWidth-1:0] sfifo_esrng_rdata;
+ logic sfifo_esrng_push;
+ logic sfifo_esrng_pop;
+ logic sfifo_esrng_clr;
+ logic sfifo_esrng_not_empty;
+ logic sfifo_esrng_err;
- logic sfifo_postht_push;
- logic sfifo_postht_pop;
- logic sfifo_postht_clr;
- logic [31:0] sfifo_postht_wdata;
- logic [31:0] sfifo_postht_rdata;
- logic [PostHTDepth:0] sfifo_postht_depth;
- logic sfifo_postht_not_full;
- logic sfifo_postht_not_empty;
- logic sfifo_postht_err;
- logic sfifo_postht_avail;
+ logic [Clog2EsFifoDepth:0] sfifo_esfinal_depth;
+ logic [(1+SeedLen)-1:0] sfifo_esfinal_wdata;
+ logic [(1+SeedLen)-1:0] sfifo_esfinal_rdata;
+ logic sfifo_esfinal_push;
+ logic sfifo_esfinal_pop;
+ logic sfifo_esfinal_clr;
+ logic sfifo_esfinal_not_full;
+ logic sfifo_esfinal_not_empty;
+ logic sfifo_esfinal_err;
+ logic [SeedLen-1:0] esfinal_data;
+ logic esfinal_fips_flag;
- logic sfifo_essw_push;
- logic sfifo_essw_pop;
- logic sfifo_essw_clr;
- logic [31:0] sfifo_essw_wdata;
- logic [31:0] sfifo_essw_rdata;
- logic [2:0 ] sfifo_essw_depth;
- logic sfifo_essw_not_full;
- logic sfifo_essw_not_empty;
- logic sfifo_essw_err;
+ logic any_active;
+ logic any_fail_pulse;
+ logic main_stage_pop;
+ logic bypass_stage_pop;
+ logic [EigthRegWidth-1:0] any_fail_count;
+ logic [EigthRegWidth-1:0] alert_threshold;
+ logic alert_event;
+ logic repcnt_active;
+ logic adaptp_active;
+ logic bucket_active;
+ logic markov_active;
+ logic alert_cntrs_clr;
+ logic health_test_clr;
+ logic health_test_done_pulse;
+ logic [RngBusWidth-1:0] health_test_esbus;
+ logic health_test_esbus_vld;
+ logic es_route_to_sw;
+ logic es_bypass_to_sw;
+ logic es_bypass_mode;
+ logic rst_bypass_mode;
+ logic rst_alert_cntr;
+ logic boot_bypass_disable;
+ logic fips_compliance;
- logic sfifo_eshw_push;
- logic sfifo_eshw_pop;
- logic sfifo_eshw_clr;
- logic [31:0] sfifo_eshw_wdata;
- logic [31:0] sfifo_eshw_rdata;
- logic [2:0] sfifo_eshw_depth;
- logic sfifo_eshw_not_full;
- logic sfifo_eshw_not_empty;
- logic sfifo_eshw_err;
+ logic [HalfRegWidth-1:0] health_test_fips_window;
+ logic [HalfRegWidth-1:0] health_test_bypass_window;
+ logic [HalfRegWidth-1:0] health_test_window;
+ logic [HalfRegWidth-1:0] repcnt_fips_threshold;
+ logic [HalfRegWidth-1:0] repcnt_bypass_threshold;
+ logic [HalfRegWidth-1:0] repcnt_threshold;
+ logic [HalfRegWidth-1:0] repcnt_event_cnt;
+ logic [HalfRegWidth-1:0] repcnt_event_hwm_fips;
+ logic [HalfRegWidth-1:0] repcnt_event_hwm_bypass;
+ logic [FullRegWidth-1:0] repcnt_total_fails;
+ logic [EigthRegWidth-1:0] repcnt_fail_count;
+ logic repcnt_fail_pulse;
-// logic [RngBusWidth-1:0] rng_bits_err;
- logic [RngBusWidth-1:0] rct_active;
- logic [15:0] rct_max_cnt;
- logic [RngBusWidth-1:0] apt_active;
- logic [15:0] apt_max_cnt;
- logic [15:0] apt_window;
- logic [RngBusWidth-1:0] apt_fail_pls;
- logic [RngBusWidth-1:0] rct_fail_pls;
- logic [RngBusWidth-1:0] shtests_passing;
- logic [RngBusWidth-1:0] packer_esbus_wdata;
- logic [31:0] packer_esbus_rdata;
- logic packer_esbus_push;
- logic packer_esbus_clr;
- logic packer_esbus_valid;
- logic packer_esbit_wdata;
- logic [31:0] packer_esbit_rdata;
- logic packer_esbit_push;
- logic packer_esbit_clr;
- logic packer_esbit_valid;
- logic packer_valid;
- logic fill_sfifo_essw;
+ logic [HalfRegWidth-1:0] adaptp_hi_fips_threshold;
+ logic [HalfRegWidth-1:0] adaptp_hi_bypass_threshold;
+ logic [HalfRegWidth-1:0] adaptp_hi_threshold;
+ logic [HalfRegWidth-1:0] adaptp_lo_fips_threshold;
+ logic [HalfRegWidth-1:0] adaptp_lo_bypass_threshold;
+ logic [HalfRegWidth-1:0] adaptp_lo_threshold;
+ logic [HalfRegWidth-1:0] adaptp_event_cnt;
+ logic [HalfRegWidth-1:0] adaptp_hi_event_hwm_fips;
+ logic [HalfRegWidth-1:0] adaptp_hi_event_hwm_bypass;
+ logic [HalfRegWidth-1:0] adaptp_lo_event_hwm_fips;
+ logic [HalfRegWidth-1:0] adaptp_lo_event_hwm_bypass;
+ logic [FullRegWidth-1:0] adaptp_hi_total_fails;
+ logic [FullRegWidth-1:0] adaptp_lo_total_fails;
+ logic [EigthRegWidth-1:0] adaptp_hi_fail_count;
+ logic [EigthRegWidth-1:0] adaptp_lo_fail_count;
+ logic adaptp_hi_fail_pulse;
+ logic adaptp_lo_fail_pulse;
+
+ logic [HalfRegWidth-1:0] bucket_fips_threshold;
+ logic [HalfRegWidth-1:0] bucket_bypass_threshold;
+ logic [HalfRegWidth-1:0] bucket_threshold;
+ logic [HalfRegWidth-1:0] bucket_event_cnt;
+ logic [HalfRegWidth-1:0] bucket_event_hwm_fips;
+ logic [HalfRegWidth-1:0] bucket_event_hwm_bypass;
+ logic [FullRegWidth-1:0] bucket_total_fails;
+ logic [EigthRegWidth-1:0] bucket_fail_count;
+ logic bucket_fail_pulse;
+
+ logic [HalfRegWidth-1:0] markov_fips_threshold;
+ logic [HalfRegWidth-1:0] markov_bypass_threshold;
+ logic [HalfRegWidth-1:0] markov_threshold;
+ logic [HalfRegWidth-1:0] markov_event_cnt;
+ logic [HalfRegWidth-1:0] markov_event_hwm_fips;
+ logic [HalfRegWidth-1:0] markov_event_hwm_bypass;
+ logic [FullRegWidth-1:0] markov_total_fails;
+ logic [EigthRegWidth-1:0] markov_fail_count;
+ logic markov_fail_pulse;
+
+ logic pfifo_esbit_wdata;
+ logic [RngBusWidth-1:0] pfifo_esbit_rdata;
+ logic pfifo_esbit_not_empty;
+ logic pfifo_esbit_push;
+ logic pfifo_esbit_clr;
+ logic pfifo_esbit_pop;
+
+ logic [RngBusWidth-1:0] pfifo_postht_wdata;
+ logic [PostHTWidth-1:0] pfifo_postht_rdata;
+ logic pfifo_postht_not_empty;
+ logic pfifo_postht_push;
+ logic pfifo_postht_clr;
+ logic pfifo_postht_pop;
+
+ logic [PostHTWidth-1:0] pfifo_cond_wdata;
+ logic [SeedLen-1:0] pfifo_cond_rdata;
+ logic pfifo_cond_not_empty;
+ logic pfifo_cond_push;
+ logic pfifo_cond_clr;
+ logic pfifo_cond_pop;
+
+ logic [PostHTWidth-1:0] pfifo_bypass_wdata;
+ logic [SeedLen-1:0] pfifo_bypass_rdata;
+ logic pfifo_bypass_not_empty;
+ logic pfifo_bypass_push;
+ logic pfifo_bypass_clr;
+ logic pfifo_bypass_pop;
+
+ logic [SeedLen-1:0] pfifo_swread_wdata;
+ logic pfifo_swread_not_full;
+ logic [FullRegWidth-1:0] pfifo_swread_rdata;
+ logic pfifo_swread_not_empty;
+ logic pfifo_swread_push;
+ logic pfifo_swread_clr;
+ logic pfifo_swread_pop;
+
+ logic [SeedLen-1:0] final_es_data;
+
// flops
- logic entropy_val_q, entropy_val_d;
logic [15:0] es_rate_cntr_q, es_rate_cntr_d;
-// logic rng_bits_err_q, rng_bits_err_d;
+ logic lfsr_incr_dly_q, lfsr_incr_dly_d;
+ logic [RngBusWidth-1:0] ht_esbus_dly_q, ht_esbus_dly_d;
+ logic ht_esbus_vld_dly_q, ht_esbus_vld_dly_d;
+ logic ht_esbus_vld_dly2_q, ht_esbus_vld_dly2_d;
+ logic boot_bypass_q, boot_bypass_d;
+ logic ht_failed_q, ht_failed_d;
always_ff @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
- entropy_val_q <= '0;
es_rate_cntr_q <= 16'h0001;
-// rng_bits_err_q <= '0;
+ lfsr_incr_dly_q <= '0;
+ boot_bypass_q <= 1'b1;
+ ht_failed_q <= '0;
+ ht_esbus_dly_q <= '0;
+ ht_esbus_vld_dly_q <= '0;
+ ht_esbus_vld_dly2_q <= '0;
end else begin
- entropy_val_q <= entropy_val_d;
es_rate_cntr_q <= es_rate_cntr_d;
-// rng_bits_err_q <= rng_bits_err_d;
+ lfsr_incr_dly_q <= lfsr_incr_dly_d;
+ boot_bypass_q <= boot_bypass_d;
+ ht_failed_q <= ht_failed_d;
+ ht_esbus_dly_q <= ht_esbus_dly_d;
+ ht_esbus_vld_dly_q <= ht_esbus_vld_dly_d;
+ ht_esbus_vld_dly2_q <= ht_esbus_vld_dly2_d;
end
- assign es_enable = (|reg2hw.es_conf.enable.q);
- assign es_enable_dig = reg2hw.es_conf.enable.q[0];
- assign es_enable_rng = reg2hw.es_conf.enable.q[1];
- assign load_seed = ~es_enable;
+ assign es_enable = (|reg2hw.conf.enable.q);
+ assign es_enable_lfsr = reg2hw.conf.enable.q[1];
+ assign es_enable_rng = reg2hw.conf.enable.q[0];
+ assign load_seed = !es_enable;
- assign entropy_src_rng_o.rng_enable = reg2hw.es_conf.rng_src_en.q;
+ assign entropy_src_rng_o.rng_enable = es_enable_rng;
+
+ assign es_rng_src_ok = entropy_src_rng_i.rng_ok;
+ assign es_rng_bus = entropy_src_rng_i.rng_b;
//--------------------------------------------
@@ -151,8 +240,8 @@
//--------------------------------------------
prim_intr_hw #(.Width(1)) intr_hw_es_entropy_valid (
- .clk_i,
- .rst_ni,
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
.event_intr_i (event_es_entropy_valid),
.reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_entropy_valid.q),
.reg2hw_intr_test_q_i (reg2hw.intr_test.es_entropy_valid.q),
@@ -163,36 +252,22 @@
.intr_o (es_entropy_valid_o)
);
- prim_intr_hw #(.Width(1)) intr_hw_es_rct_failed (
- .clk_i,
- .rst_ni,
- .event_intr_i (event_es_rct_failed),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_rct_failed.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.es_rct_failed.q),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.es_rct_failed.qe),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.es_rct_failed.q),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.es_rct_failed.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.es_rct_failed.d),
- .intr_o (es_rct_failed_o)
+ prim_intr_hw #(.Width(1)) intr_hw_es_health_test_failed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .event_intr_i (event_es_health_test_failed),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_health_test_failed.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.es_health_test_failed.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.es_health_test_failed.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.es_health_test_failed.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.es_health_test_failed.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.es_health_test_failed.d),
+ .intr_o (es_health_test_failed_o)
);
- prim_intr_hw #(.Width(1)) intr_hw_es_apt_failed (
- .clk_i,
- .rst_ni,
- .event_intr_i (event_es_apt_failed),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_apt_failed.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.es_apt_failed.q),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.es_apt_failed.qe),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.es_apt_failed.q),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.es_apt_failed.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.es_apt_failed.d),
- .intr_o (es_apt_failed_o)
- );
-
-
prim_intr_hw #(.Width(1)) intr_hw_es_fifo_err (
- .clk_i,
- .rst_ni,
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
.event_intr_i (event_es_fifo_err),
.reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_fifo_err.q),
.reg2hw_intr_test_q_i (reg2hw.intr_test.es_fifo_err.q),
@@ -207,7 +282,8 @@
// lfsr - a version of a entropy source
//--------------------------------------------
- assign lfsr_enable = es_enable_dig && es_rate_entropy_valid;
+ assign lfsr_incr = es_enable_lfsr && es_rate_entropy_pulse;
+ assign lfsr_incr_dly_d = lfsr_incr;
prim_lfsr #(.LfsrDw(RngBusWidth),
.EntropyDw(RngBusWidth),
@@ -219,7 +295,7 @@
.rst_ni (rst_ni),
.seed_en_i (load_seed),
.seed_i (seed_value),
- .lfsr_en_i (lfsr_enable),
+ .lfsr_en_i (lfsr_incr_dly_q),
.entropy_i ('0),
.state_o (lfsr_value)
);
@@ -227,295 +303,713 @@
// entropy rate limiter
assign es_rate_cntr_d =
- ~es_rate_entropy_valid_en ? 16'h0001 :
+ !es_enable ? 16'h0001 :
(es_rate == '0) ? 16'h0000 :
- es_rate_entropy_valid ? es_rate :
+ es_rate_entropy_pulse ? es_rate :
(es_rate_cntr_q - 1);
- assign es_rate_entropy_valid =
- ~es_rate_entropy_valid_en ? 1'b0 :
+ assign es_rate_entropy_pulse =
+ !es_enable ? 1'b0 :
(es_rate == '0) ? 1'b0 :
(es_rate_cntr_q == 16'h0001);
- assign es_rate_entropy_valid_en = (es_enable_rng & es_rng_src_ok) | es_enable_dig;
-
//--------------------------------------------
// tlul register settings
//--------------------------------------------
// seed register
- assign seed_value = reg2hw.es_seed.q;
+ assign seed_value = reg2hw.seed.q;
// es rate register
- assign es_rate = reg2hw.es_rate.q;
+ assign es_rate = reg2hw.rate.q;
// set the interrupt event when enabled
- assign event_es_entropy_valid = entropy_val_q;
+ assign event_es_entropy_valid = pfifo_swread_not_empty;
// set the interrupt sources
- assign event_es_fifo_err =
- sfifo_esdig_err |
- sfifo_postht_err |
- sfifo_essw_err |
- sfifo_eshw_err;
+ assign event_es_fifo_err = sfifo_esrng_err || sfifo_esfinal_err;
// set the debug status reg
- assign hw2reg.es_fifo_status.dig_src_depth.d = sfifo_esdig_depth;
- assign hw2reg.es_fifo_status.hwif_depth.d = sfifo_eshw_depth;
- assign hw2reg.es_fifo_status.es_depth.d = sfifo_postht_depth;
-
+ assign hw2reg.debug_status.entropy_fifo_depth.d = sfifo_esfinal_depth;
//--------------------------------------------
- // basic checks for RNG bus input
+ // receive in RNG bus input
//--------------------------------------------
- assign rng_bit_en = reg2hw.es_conf.rng_bit_en.q;
- assign rng_bit_sel = reg2hw.es_conf.rng_bit_sel.q;
-
- assign es_rng_src_ok = entropy_src_rng_i.rng_ok;
-
-
- prim_fifo_sync # (.Width(RngBusWidth),.Pass(0),.Depth(4))
- u_prim_fifo_sync_esdig (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .clr_i (sfifo_esdig_clr),
- .wvalid_i (sfifo_esdig_push),
- .wready_o (sfifo_esdig_not_full),
- .wdata_i (sfifo_esdig_wdata),
- .rvalid_o (sfifo_esdig_not_empty),
- .rready_i (sfifo_esdig_pop),
- .rdata_o (sfifo_esdig_rdata),
- .depth_o (sfifo_esdig_depth)
+ prim_fifo_sync # (.Width(RngBusWidth),.Pass(0),.Depth(2))
+ u_prim_fifo_sync_esrng (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (sfifo_esrng_clr),
+ .wvalid_i (sfifo_esrng_push),
+ .wdata_i (sfifo_esrng_wdata),
+ .wready_o (),
+ .rvalid_o (sfifo_esrng_not_empty),
+ .rdata_o (sfifo_esrng_rdata),
+ .rready_i (sfifo_esrng_pop),
+ .depth_o ()
);
// fifo controls
- assign sfifo_esdig_push = es_enable & es_rate_entropy_valid & sfifo_esdig_not_full;
- assign sfifo_esdig_clr = ~es_enable;
- assign sfifo_esdig_wdata = es_enable_dig ? lfsr_value : entropy_src_rng_i.rng_b;
- assign sfifo_esdig_pop = es_enable & sfifo_esdig_not_empty & sfifo_postht_avail;
+ assign sfifo_esrng_push = es_enable_rng && es_rng_src_ok && es_rate_entropy_pulse;
+ assign sfifo_esrng_clr = !es_enable;
+ assign sfifo_esrng_wdata = es_rng_bus;
+ assign sfifo_esrng_pop = es_enable && es_rate_entropy_pulse && sfifo_esrng_not_empty;
- // note: allow input lfsr entropy to drop
+ // note: allow input rng raw entropy to drop
// fifo err
- assign sfifo_esdig_err =
- (sfifo_esdig_pop & ~sfifo_esdig_not_empty );
+ assign sfifo_esrng_err =
+ (sfifo_esrng_pop && !sfifo_esrng_not_empty );
- // pack esbus before moving to a 32 bit bus
- prim_packer # (.InW(RngBusWidth),.OutW(32))
- u_prim_packer_esbus (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .valid_i (packer_esbus_push),
- .data_i (packer_esbus_wdata),
- .mask_i ({RngBusWidth{1'b1}}),
- .ready_o (),
- .valid_o (packer_esbus_valid),
- .data_o (packer_esbus_rdata),
- .mask_o (),
- .ready_i (1'b1),
- .flush_i (packer_esbus_clr),
- .flush_done_o ()
+ // pack esrng bus into signal bit packer
+
+ assign rng_bit_en = reg2hw.conf.rng_bit_en.q;
+ assign rng_bit_sel = reg2hw.conf.rng_bit_sel.q;
+
+ prim_packer_fifo # (.InW(1),.OutW(RngBusWidth))
+ u_prim_packer_fifo_esbit (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_esbit_clr),
+ .wvalid_i (pfifo_esbit_push),
+ .wdata_i (pfifo_esbit_wdata),
+ .wready_o (),
+ .rvalid_o (pfifo_esbit_not_empty),
+ .rdata_o (pfifo_esbit_rdata),
+ .rready_i (pfifo_esbit_pop),
+ .depth_o ()
);
- assign packer_esbus_push = ~rng_bit_en & sfifo_esdig_pop;
- assign packer_esbus_wdata = sfifo_esdig_rdata;
- assign packer_esbus_clr = ~es_enable;
-
- // pack esbit before moving to a 32 bit bus
-
- prim_packer # (.InW(1),.OutW(32))
- u_prim_packer_esbit (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .valid_i (packer_esbit_push),
- .data_i (packer_esbit_wdata),
- .mask_i (1'b1),
- .ready_o (),
- .valid_o (packer_esbit_valid),
- .data_o (packer_esbit_rdata),
- .mask_o (),
- .ready_i (1'b1),
- .flush_i (packer_esbit_clr),
- .flush_done_o ()
- );
-
- assign packer_esbit_push = rng_bit_en & sfifo_esdig_pop;
- assign packer_esbit_clr = ~es_enable;
- assign packer_esbit_wdata =
- (rng_bit_sel == 2'h0) ? sfifo_esdig_rdata[0] :
- (rng_bit_sel == 2'h1) ? sfifo_esdig_rdata[1] :
- (rng_bit_sel == 2'h2) ? sfifo_esdig_rdata[2] :
- sfifo_esdig_rdata[3];
+ assign pfifo_esbit_push = rng_bit_en && sfifo_esrng_pop && es_rate_entropy_pulse;
+ assign pfifo_esbit_clr = !es_enable;
+ assign pfifo_esbit_pop = es_rate_entropy_pulse && pfifo_esbit_not_empty;
+ assign pfifo_esbit_wdata =
+ (rng_bit_sel == 2'h0) ? sfifo_esrng_rdata[0] :
+ (rng_bit_sel == 2'h1) ? sfifo_esrng_rdata[1] :
+ (rng_bit_sel == 2'h2) ? sfifo_esrng_rdata[2] :
+ sfifo_esrng_rdata[3];
- // combine packers
- assign packer_valid = packer_esbus_valid | packer_esbit_valid;
+ // select source for health testing
+ assign health_test_esbus = es_enable_lfsr ? lfsr_value :
+ (es_enable_rng && rng_bit_en) ? pfifo_esbit_rdata :
+ sfifo_esrng_rdata;
- prim_fifo_sync # (.Width(32),.Pass(0),.Depth(EsFifoDepth))
- u_prim_fifo_sync_postht (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .clr_i (sfifo_postht_clr),
- .wvalid_i (sfifo_postht_push),
- .wready_o (sfifo_postht_not_full),
- .wdata_i (sfifo_postht_wdata),
- .rvalid_o (sfifo_postht_not_empty),
- .rready_i (sfifo_postht_pop),
- .rdata_o (sfifo_postht_rdata),
- .depth_o (sfifo_postht_depth)
- );
+ assign health_test_esbus_vld = es_enable_lfsr ? es_rate_entropy_pulse :
+ (es_enable_rng && rng_bit_en) ? pfifo_esbit_pop :
+ sfifo_esrng_pop;
- // fifo controls
- assign sfifo_postht_push = es_enable & packer_valid & (&shtests_passing);
- assign sfifo_postht_clr = ~es_enable;
- assign sfifo_postht_wdata = rng_bit_en ? packer_esbit_rdata : packer_esbus_rdata;
- assign sfifo_postht_pop = es_enable & sfifo_postht_not_empty &
- (fill_sfifo_essw | sfifo_eshw_not_full);
+ assign ht_esbus_vld_dly_d = health_test_esbus_vld;
+ assign ht_esbus_dly_d = health_test_esbus;
+ assign ht_esbus_vld_dly2_d = ht_esbus_vld_dly_q;
- // allow one extra location because of packer
- assign sfifo_postht_avail = (sfifo_postht_depth < (EsFifoDepth-1));
+ assign repcnt_active = !reg2hw.conf.repcnt_disable.q;
+ assign adaptp_active = !reg2hw.conf.adaptp_disable.q;
+ assign bucket_active = !reg2hw.conf.bucket_disable.q;
+ assign markov_active = !reg2hw.conf.markov_disable.q;
- // fifo err
- assign sfifo_postht_err =
- (sfifo_postht_push & ~sfifo_postht_not_full) |
- (sfifo_postht_pop & ~sfifo_postht_not_empty );
+ assign health_test_clr = reg2hw.conf.health_test_clr.q;
+ assign health_test_fips_window = reg2hw.health_test_windows.fips_window.q;
+ assign health_test_bypass_window = reg2hw.health_test_windows.bypass_window.q;
+ assign repcnt_fips_threshold = reg2hw.repcnt_thresholds.fips_repcnt_thresh.q;
+ assign repcnt_bypass_threshold = reg2hw.repcnt_thresholds.bypass_repcnt_thresh.q;
+
+ assign adaptp_hi_fips_threshold = reg2hw.adaptp_hi_thresholds.fips_adaptp_hi_thresh.q;
+ assign adaptp_hi_bypass_threshold = reg2hw.adaptp_hi_thresholds.bypass_adaptp_hi_thresh.q;
+
+ assign adaptp_lo_fips_threshold = reg2hw.adaptp_lo_thresholds.fips_adaptp_lo_thresh.q;
+ assign adaptp_lo_bypass_threshold = reg2hw.adaptp_lo_thresholds.bypass_adaptp_lo_thresh.q;
+
+ assign bucket_fips_threshold = reg2hw.bucket_thresholds.fips_bucket_thresh.q;
+ assign bucket_bypass_threshold = reg2hw.bucket_thresholds.bypass_bucket_thresh.q;
+
+ assign markov_fips_threshold = reg2hw.markov_thresholds.fips_markov_thresh.q;
+ assign markov_bypass_threshold = reg2hw.markov_thresholds.bypass_markov_thresh.q;
+ assign health_test_window = es_bypass_mode ? health_test_bypass_window : health_test_fips_window;
+ assign repcnt_threshold = es_bypass_mode ? repcnt_bypass_threshold : repcnt_fips_threshold;
+ assign adaptp_hi_threshold = es_bypass_mode ? adaptp_hi_bypass_threshold :
+ adaptp_hi_fips_threshold;
+ assign adaptp_lo_threshold = es_bypass_mode ? adaptp_lo_bypass_threshold :
+ adaptp_lo_fips_threshold;
+ assign bucket_threshold = es_bypass_mode ? bucket_bypass_threshold : bucket_fips_threshold;
+ assign markov_threshold = es_bypass_mode ? markov_bypass_threshold : markov_fips_threshold;
+
+ assign event_es_health_test_failed = alert_event;
+
+ assign es_route_to_sw = reg2hw.entropy_control.es_route.q;
+ assign es_bypass_to_sw = reg2hw.entropy_control.es_type.q;
+ assign boot_bypass_disable = reg2hw.conf.boot_bypass_disable.q;
+
+ assign boot_bypass_d =
+ boot_bypass_disable ? 1'b0 :
+ rst_bypass_mode ? 1'b0 :
+ boot_bypass_q;
+
+ assign es_bypass_mode = boot_bypass_q || es_bypass_to_sw;
//--------------------------------------------
- // health tests
+ // repetitive count test
//--------------------------------------------
- genvar ta;
- generate
- for (ta = 0; ta < RngBusWidth; ta = ta+1) begin : gen_test_act
- assign rct_active[ta] = rng_bit_en ? ((rng_bit_sel == ta) & reg2hw.es_conf.rct_en.q) :
- reg2hw.es_conf.rct_en.q;
- assign apt_active[ta] = rng_bit_en ? ((rng_bit_sel == ta) & reg2hw.es_conf.apt_en.q) :
- reg2hw.es_conf.apt_en.q;
- end
- endgenerate
-
- assign rct_max_cnt = reg2hw.es_rct_health.q;
-
- assign apt_max_cnt = reg2hw.es_apt_health.apt_max.q;
- assign apt_window = reg2hw.es_apt_health.apt_win.q;
-
- genvar sh;
- generate
- for (sh = 0; sh < RngBusWidth; sh = sh+1) begin : gen_shtests
- entropy_src_shtests
- u_entropy_src_shtests (
+ entropy_src_repcnt_ht # (.RegWidth(HalfRegWidth),.RngBusWidth(RngBusWidth))
+ u_entropy_src_repcnt_ht
+ (
.clk_i (clk_i),
.rst_ni (rst_ni),
- .entropy_bit_i (sfifo_esdig_rdata[sh]),
- .entropy_bit_vld_i (sfifo_esdig_pop),
- .rct_active_i (rct_active[sh]),
- .rct_max_cnt_i (rct_max_cnt),
- .apt_active_i (apt_active[sh]),
- .apt_max_cnt_i (apt_max_cnt),
- .apt_window_i (apt_window),
- .rct_fail_pls_o (rct_fail_pls[sh]),
- .apt_fail_pls_o (apt_fail_pls[sh]),
- .shtests_passing_o (shtests_passing[sh])
- );
- end
- endgenerate
+ .entropy_bit_i (health_test_esbus),
+ .entropy_bit_vld_i (health_test_esbus_vld),
+ .clear_i (health_test_clr),
+ .active_i (repcnt_active),
+ .thresh_i (repcnt_threshold),
+ .window_i (health_test_window),
+ .test_cnt_o (repcnt_event_cnt),
+ .test_done_pulse_o (health_test_done_pulse),
+ .test_fail_pulse_o (repcnt_fail_pulse)
+ );
- assign event_es_rct_failed = |rct_fail_pls;
- assign event_es_apt_failed = |apt_fail_pls;
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_repcnt_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (repcnt_active),
+ .event_i (repcnt_fail_pulse && !es_bypass_mode),
+ .value_i (repcnt_event_cnt),
+ .value_o (repcnt_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_repcnt_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (repcnt_active),
+ .event_i (repcnt_fail_pulse && es_bypass_mode),
+ .value_i (repcnt_event_cnt),
+ .value_o (repcnt_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_repcnt
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (repcnt_active),
+ .event_i (repcnt_fail_pulse),
+ .value_o (repcnt_total_fails)
+ );
+
+ assign hw2reg.repcnt_hi_watermarks.fips_repcnt_hi_watermark.d = repcnt_event_hwm_fips;
+ assign hw2reg.repcnt_hi_watermarks.bypass_repcnt_hi_watermark.d = repcnt_event_hwm_bypass;
+ assign hw2reg.repcnt_total_fails.d = repcnt_total_fails;
+
+ //--------------------------------------------
+ // adaptive proportion test
+ //--------------------------------------------
+
+ entropy_src_adaptp_ht # (.RegWidth(HalfRegWidth),.RngBusWidth(RngBusWidth))
+ u_entropy_src_adaptp_ht
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .entropy_bit_i (health_test_esbus),
+ .entropy_bit_vld_i (health_test_esbus_vld),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .thresh_hi_i (adaptp_hi_threshold),
+ .thresh_lo_i (adaptp_lo_threshold),
+ .window_i (health_test_window),
+ .test_cnt_o (adaptp_event_cnt),
+ .test_done_pulse_o (), // NC
+ .test_fail_hi_pulse_o(adaptp_hi_fail_pulse),
+ .test_fail_lo_pulse_o(adaptp_lo_fail_pulse)
+ );
+
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_adaptp_hi_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_hi_fail_pulse && !es_bypass_mode),
+ .value_i (adaptp_event_cnt),
+ .value_o (adaptp_hi_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_adaptp_hi_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_hi_fail_pulse && es_bypass_mode),
+ .value_i (adaptp_event_cnt),
+ .value_o (adaptp_hi_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_adaptp_hi
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_hi_fail_pulse),
+ .value_o (adaptp_hi_total_fails)
+ );
+
+
+ assign hw2reg.adaptp_hi_watermarks.fips_adaptp_hi_watermark.d = adaptp_hi_event_hwm_fips;
+ assign hw2reg.adaptp_hi_watermarks.bypass_adaptp_hi_watermark.d = adaptp_hi_event_hwm_bypass;
+ assign hw2reg.adaptp_hi_total_fails.d = adaptp_hi_total_fails;
+
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(0))
+ u_entropy_src_watermark_reg_adaptp_lo_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_lo_fail_pulse && !es_bypass_mode),
+ .value_i (adaptp_event_cnt),
+ .value_o (adaptp_lo_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(0))
+ u_entropy_src_watermark_reg_adaptp_lo_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_lo_fail_pulse && es_bypass_mode),
+ .value_i (adaptp_event_cnt),
+ .value_o (adaptp_lo_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_adaptp_lo
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_lo_fail_pulse),
+ .value_o (adaptp_lo_total_fails)
+ );
+
+ assign hw2reg.adaptp_lo_watermarks.fips_adaptp_lo_watermark.d = adaptp_lo_event_hwm_fips;
+ assign hw2reg.adaptp_lo_watermarks.bypass_adaptp_lo_watermark.d = adaptp_lo_event_hwm_bypass;
+ assign hw2reg.adaptp_lo_total_fails.d = adaptp_lo_total_fails;
//--------------------------------------------
- // fifos for final distribution
+ // bucket test
//--------------------------------------------
- assign fill_sfifo_essw = es_enable & sfifo_essw_not_full & efuse_es_sw_reg_en_i;
+ entropy_src_bucket_ht # (.RegWidth(HalfRegWidth),.RngBusWidth(RngBusWidth))
+ u_entropy_src_bucket_ht
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .entropy_bit_i (health_test_esbus),
+ .entropy_bit_vld_i (health_test_esbus_vld),
+ .clear_i (health_test_clr),
+ .active_i (bucket_active),
+ .thresh_i (bucket_threshold),
+ .window_i (health_test_window),
+ .test_cnt_o (bucket_event_cnt),
+ .test_done_pulse_o (), // NC
+ .test_fail_pulse_o (bucket_fail_pulse)
+ );
- // this fifo feeds the sw register interface
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_bucket_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (bucket_active),
+ .event_i (bucket_fail_pulse && !es_bypass_mode),
+ .value_i (bucket_event_cnt),
+ .value_o (bucket_event_hwm_fips)
+ );
- prim_fifo_sync # (.Width(32),.Pass(0),.Depth(4))
- u_prim_fifo_sync_essw (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .clr_i (sfifo_essw_clr),
- .wvalid_i (sfifo_essw_push),
- .wready_o (sfifo_essw_not_full),
- .wdata_i (sfifo_essw_wdata),
- .rvalid_o (sfifo_essw_not_empty),
- .rready_i (sfifo_essw_pop),
- .rdata_o (sfifo_essw_rdata),
- .depth_o (sfifo_essw_depth)
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_bucket_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (bucket_active),
+ .event_i (bucket_fail_pulse && es_bypass_mode),
+ .value_i (bucket_event_cnt),
+ .value_o (bucket_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_bucket
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (bucket_active),
+ .event_i (bucket_fail_pulse),
+ .value_o (bucket_total_fails)
+ );
+
+ assign hw2reg.bucket_hi_watermarks.fips_bucket_hi_watermark.d = bucket_event_hwm_fips;
+ assign hw2reg.bucket_hi_watermarks.bypass_bucket_hi_watermark.d = bucket_event_hwm_bypass;
+ assign hw2reg.bucket_total_fails.d = bucket_total_fails;
+
+
+ //--------------------------------------------
+ // Markov test
+ //--------------------------------------------
+
+ entropy_src_markov_ht # (.RegWidth(HalfRegWidth),.RngBusWidth(RngBusWidth))
+ u_entropy_src_markov_ht
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .entropy_bit_i (health_test_esbus),
+ .entropy_bit_vld_i (health_test_esbus_vld),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .thresh_i (markov_threshold),
+ .window_i (health_test_window),
+ .test_cnt_o (markov_event_cnt),
+ .test_done_pulse_o (),// NC
+ .test_fail_pulse_o (markov_fail_pulse)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_markov_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .event_i (markov_fail_pulse && !es_bypass_mode),
+ .value_i (markov_event_cnt),
+ .value_o (markov_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_markov_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .event_i (markov_fail_pulse && es_bypass_mode),
+ .value_i (markov_event_cnt),
+ .value_o (markov_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_markov
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .event_i (markov_fail_pulse),
+ .value_o (markov_total_fails)
+ );
+
+ assign hw2reg.markov_hi_watermarks.fips_markov_hi_watermark.d = markov_event_hwm_fips;
+ assign hw2reg.markov_hi_watermarks.bypass_markov_hi_watermark.d = markov_event_hwm_bypass;
+ assign hw2reg.markov_total_fails.d = markov_total_fails;
+
+ //--------------------------------------------
+ // summary and alert registers
+ //--------------------------------------------
+
+ assign alert_cntrs_clr = health_test_clr || rst_alert_cntr;
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_any_alert_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (any_active),
+ .event_i (any_fail_pulse),
+ .value_o (any_fail_count)
+ );
+
+ assign any_active = repcnt_active || adaptp_active || bucket_active || markov_active;
+ assign any_fail_pulse = repcnt_fail_pulse || adaptp_hi_fail_pulse || adaptp_lo_fail_pulse ||
+ bucket_fail_pulse || markov_fail_pulse;
+
+
+ assign ht_failed_d = sfifo_esfinal_push ? 1'b0 :
+ (any_fail_pulse && health_test_done_pulse) ? 1'b1 :
+ ht_failed_q;
+
+ assign hw2reg.alert_fail_counts.any_fail_count.d = any_fail_count;
+
+ // signal an alert
+ assign alert_threshold = reg2hw.alert_threshold.q;
+
+ assign alert_event = (any_fail_count >= alert_threshold) && (alert_threshold != '0);
+ assign alert_event_o = alert_event;
+
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_repcnt_alert_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (repcnt_active),
+ .event_i (repcnt_fail_pulse),
+ .value_o (repcnt_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.repcnt_fail_count.d = repcnt_fail_count;
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_adaptp_alert_hi_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_hi_fail_pulse),
+ .value_o (adaptp_hi_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.adaptp_hi_fail_count.d = adaptp_hi_fail_count;
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_adaptp_alert_lo_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_lo_fail_pulse),
+ .value_o (adaptp_lo_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.adaptp_lo_fail_count.d = adaptp_lo_fail_count;
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_bucket_alert_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (bucket_active),
+ .event_i (bucket_fail_pulse),
+ .value_o (bucket_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.bucket_fail_count.d = bucket_fail_count;
+
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_markov_alert_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (markov_active),
+ .event_i (markov_fail_pulse),
+ .value_o (markov_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.markov_fail_count.d = markov_fail_count;
+
+ //--------------------------------------------
+ // pack tested entropy into pre-conditioning packer
+ //--------------------------------------------
+
+ prim_packer_fifo # (.InW(RngBusWidth),.OutW(PostHTWidth))
+ u_prim_packer_fifo_postht (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_postht_clr),
+ .wvalid_i (pfifo_postht_push),
+ .wdata_i (pfifo_postht_wdata),
+ .wready_o (),
+ .rvalid_o (pfifo_postht_not_empty),
+ .rdata_o (pfifo_postht_rdata),
+ .rready_i (pfifo_postht_pop),
+ .depth_o ()
);
- // fifo controls
- assign sfifo_essw_push = es_enable & sfifo_postht_pop & fill_sfifo_essw;
- assign sfifo_essw_clr = ~es_enable;
- assign sfifo_essw_wdata = sfifo_postht_rdata;
- assign sfifo_essw_pop = es_enable & esentropy_rd_pls & efuse_es_sw_reg_en_i;
+ assign pfifo_postht_push = ht_esbus_vld_dly_q;
+ assign pfifo_postht_wdata = ht_esbus_dly_q;
- // fifo err
- assign sfifo_essw_err =
- (sfifo_essw_push & ~sfifo_essw_not_full) |
- (sfifo_essw_pop & ~sfifo_essw_not_empty );
-
- // set the es entropy to the read reg
- assign hw2reg.es_entropy.d = es_enable ? sfifo_essw_rdata : '0;
- assign esentropy_rd_pls = reg2hw.es_entropy.re;
-
- // threshold
- assign es_fifo_thresh = reg2hw.es_thresh.q;
-
- // entropy valid
- assign entropy_val_d = ~es_enable ? 1'b0 : (sfifo_essw_depth >= es_fifo_thresh);
-
- // set the es fifo depth to the read reg
- assign hw2reg.es_fdepthst.d = sfifo_essw_depth;
+ assign pfifo_postht_clr = !es_enable;
+ assign pfifo_postht_pop = ht_esbus_vld_dly2_q && pfifo_postht_not_empty;
+ //--------------------------------------------
+ // TODO: replace standin block with SHA conditioner
+ //--------------------------------------------
- // this fifo feeds the hw bus interface
- prim_fifo_sync # (.Width(32),.Pass(0),.Depth(4))
- u_prim_fifo_sync_eshw (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .clr_i (sfifo_eshw_clr),
- .wvalid_i (sfifo_eshw_push),
- .wready_o (sfifo_eshw_not_full),
- .wdata_i (sfifo_eshw_wdata),
- .rvalid_o (sfifo_eshw_not_empty),
- .rready_i (sfifo_eshw_pop),
- .rdata_o (sfifo_eshw_rdata),
- .depth_o (sfifo_eshw_depth)
+ prim_packer_fifo # (.InW(PostHTWidth),.OutW(SeedLen))
+ u_prim_packer_fifo_cond (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_cond_clr),
+ .wvalid_i (pfifo_cond_push),
+ .wdata_i (pfifo_cond_wdata),
+ .wready_o (),
+ .rvalid_o (pfifo_cond_not_empty),
+ .rdata_o (pfifo_cond_rdata),
+ .rready_i (pfifo_cond_pop),
+ .depth_o ()
);
+ assign pfifo_cond_push = pfifo_postht_pop && !es_bypass_mode;
+ assign pfifo_cond_wdata = pfifo_postht_rdata;
+
+ assign pfifo_cond_clr = !es_enable;
+ assign pfifo_cond_pop = main_stage_pop;
+
+ //--------------------------------------------
+ // bypass SHA conditioner path
+ //--------------------------------------------
+
+ prim_packer_fifo # (.InW(PostHTWidth),.OutW(SeedLen))
+ u_prim_packer_fifo_bypass (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_bypass_clr),
+ .wvalid_i (pfifo_bypass_push),
+ .wdata_i (pfifo_bypass_wdata),
+ .wready_o (),
+ .rvalid_o (pfifo_bypass_not_empty),
+ .rdata_o (pfifo_bypass_rdata),
+ .rready_i (pfifo_bypass_pop),
+ .depth_o ()
+ );
+
+ assign pfifo_bypass_push = pfifo_postht_pop && es_bypass_mode;
+ assign pfifo_bypass_wdata = pfifo_postht_rdata;
+
+ assign pfifo_bypass_clr = !es_enable;
+ assign pfifo_bypass_pop = bypass_stage_pop;
+
+
+// mux to select between fips and bypass mode
+
+ assign final_es_data = es_bypass_mode ? pfifo_bypass_rdata : pfifo_cond_rdata;
+
+
+ //--------------------------------------------
+ // state machine to coordinate fifo flow
+ //--------------------------------------------
+
+ entropy_src_main_sm
+ u_entropy_src_main_sm (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .enable_i (es_enable),
+ .ht_done_pulse_i (health_test_done_pulse),
+ .ht_fail_pulse_i (any_fail_pulse),
+ .postht_not_empty_i (pfifo_postht_not_empty),
+ .rst_alert_cntr_o (rst_alert_cntr),
+ .bypass_mode_i (es_bypass_mode),
+ .rst_bypass_mode_o (rst_bypass_mode),
+ .main_stage_rdy_i (pfifo_cond_not_empty),
+ .bypass_stage_rdy_i (pfifo_bypass_not_empty),
+ .main_stage_pop_o (main_stage_pop),
+ .bypass_stage_pop_o (bypass_stage_pop)
+ );
+
+
+ //--------------------------------------------
+ // send processed entropy to final fifo
+ //--------------------------------------------
+
+ prim_fifo_sync # (.Width(1+SeedLen),.Pass(0),.Depth(EsFifoDepth))
+ u_prim_fifo_sync_esfinal (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (sfifo_esfinal_clr),
+ .wvalid_i (sfifo_esfinal_push),
+ .wready_o (sfifo_esfinal_not_full),
+ .wdata_i (sfifo_esfinal_wdata),
+ .rvalid_o (sfifo_esfinal_not_empty),
+ .rready_i (sfifo_esfinal_pop),
+ .rdata_o (sfifo_esfinal_rdata),
+ .depth_o (sfifo_esfinal_depth)
+ );
+
+ assign fips_compliance = !es_bypass_mode && es_enable_rng && !es_enable_lfsr && !rng_bit_en;
+
// fifo controls
- assign sfifo_eshw_push = es_enable & sfifo_postht_pop & ~fill_sfifo_essw;
- assign sfifo_eshw_clr = ~es_enable;
- assign sfifo_eshw_wdata = sfifo_postht_rdata;
- assign sfifo_eshw_pop = es_enable & entropy_src_hw_if_i.entropy_src_rdy
- & sfifo_eshw_not_empty;
+ assign sfifo_esfinal_push = sfifo_esfinal_not_full &&
+ ((main_stage_pop || bypass_stage_pop) && !ht_failed_q);
+ assign sfifo_esfinal_clr = ~es_enable;
+ assign sfifo_esfinal_wdata = {fips_compliance,final_es_data};
+ assign sfifo_esfinal_pop = es_route_to_sw ? pfifo_swread_not_full :
+ (es_enable && entropy_src_hw_if_i.es_req);
+ assign {esfinal_fips_flag,esfinal_data} = sfifo_esfinal_rdata;
// fifo err
- assign sfifo_eshw_err =
- (sfifo_eshw_push & ~sfifo_eshw_not_full) |
- (sfifo_eshw_pop & ~sfifo_eshw_not_empty );
+ assign sfifo_esfinal_err =
+ (sfifo_esfinal_push && !sfifo_esfinal_not_full) |
+ (sfifo_esfinal_pop && !sfifo_esfinal_not_empty );
// drive out hw interface
- assign entropy_src_hw_if_o.entropy_src_vld = sfifo_eshw_not_empty;
- assign entropy_src_hw_if_o.entropy_src_bits = sfifo_eshw_rdata;
+ assign entropy_src_hw_if_o.es_ack = sfifo_esfinal_not_empty && !es_route_to_sw;
+ assign entropy_src_hw_if_o.es_bits = esfinal_data;
+ assign entropy_src_hw_if_o.es_fips = esfinal_fips_flag;
//--------------------------------------------
+ // software es read path
+ //--------------------------------------------
+
+ prim_packer_fifo # (.InW(SeedLen),.OutW(FullRegWidth))
+ u_prim_packer_fifo_swread (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_swread_clr),
+ .wvalid_i (pfifo_swread_push),
+ .wdata_i (pfifo_swread_wdata),
+ .wready_o (pfifo_swread_not_full),
+ .rvalid_o (pfifo_swread_not_empty),
+ .rdata_o (pfifo_swread_rdata),
+ .rready_i (pfifo_swread_pop),
+ .depth_o ()
+ );
+
+ assign pfifo_swread_push = sfifo_esfinal_pop;
+ assign pfifo_swread_wdata = esfinal_data;
+
+ assign pfifo_swread_clr = !es_enable;
+ assign pfifo_swread_pop = es_enable && sw_es_rd_pulse;
+
+ // set the es entropy to the read reg
+ assign hw2reg.entropy_data.d = es_enable ? pfifo_swread_rdata : '0;
+ assign sw_es_rd_pulse = efuse_es_sw_reg_en_i && reg2hw.entropy_data.re;
+ //--------------------------------------------
// diag settings
//--------------------------------------------
- assign hw2reg.es_fifo_status.diag.d =
- reg2hw.es_regen.q &
- (®2hw.es_entropy.q);
+ assign hw2reg.debug_status.diag.d =
+ reg2hw.regen.q &&
+ (®2hw.entropy_data.q);
endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
new file mode 100755
index 0000000..5e4ea67
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
@@ -0,0 +1,96 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src main state machine module
+//
+// determines when new entropy is ready to be forwarded
+
+module entropy_src_main_sm (
+ input logic clk_i,
+ input logic rst_ni,
+
+ input logic enable_i,
+ input logic ht_done_pulse_i,
+ input logic ht_fail_pulse_i,
+ input logic postht_not_empty_i,
+ output logic rst_alert_cntr_o,
+ input logic bypass_mode_i,
+ output logic rst_bypass_mode_o,
+ input logic main_stage_rdy_i,
+ input logic bypass_stage_rdy_i,
+ output logic main_stage_pop_o,
+ output logic bypass_stage_pop_o
+);
+
+ // TODO: consider hamming-distance expansion of state encoding
+ typedef enum logic [2:0] {
+ IDLE = 3'h0, // idle
+ HTDP = 3'h1, // wait for health test done pulse
+ PNMT = 3'h2, // wait for post health test packer not empty state
+ MODE = 3'h3, // determine what mode the flow is in
+ BYPS = 3'h4, // in bypass mode
+ NORM = 3'h5 // in normal mode
+ } state_e;
+
+ state_e state_q, state_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ state_q <= IDLE;
+ end else begin
+ state_q <= state_d;
+ end
+
+ always_comb begin
+ state_d = state_q;
+ rst_bypass_mode_o = 1'b0;
+ rst_alert_cntr_o = 1'b0;
+ main_stage_pop_o = 1'b0;
+ bypass_stage_pop_o = 1'b0;
+ unique case (state_q)
+ IDLE: begin
+ if (enable_i) begin
+ state_d = HTDP;
+ end
+ end
+ HTDP: begin
+ if (ht_done_pulse_i) begin
+ if (ht_fail_pulse_i) begin
+ state_d = IDLE;
+ end else begin
+ state_d = PNMT;
+ end
+ end
+ end
+ PNMT: begin
+ rst_alert_cntr_o = 1'b1;
+ if (postht_not_empty_i) begin
+ state_d = MODE;
+ end
+ end
+ MODE: begin
+ if (bypass_mode_i) begin
+ state_d = BYPS;
+ end else begin
+ state_d = NORM;
+ end
+ end
+ BYPS: begin
+ if (bypass_stage_rdy_i) begin
+ rst_bypass_mode_o = 1'b1;
+ bypass_stage_pop_o = 1'b1;
+ state_d = IDLE;
+ end
+ end
+ NORM: begin
+ if (main_stage_rdy_i) begin
+ main_stage_pop_o = 1'b1;
+ state_d = IDLE;
+ end
+ end
+ default: state_d = IDLE;
+ endcase
+ end
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv
new file mode 100755
index 0000000..f8b8f3e
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv
@@ -0,0 +1,111 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src Markov health test module
+//
+
+module entropy_src_markov_ht #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned RngBusWidth = 4
+) (
+ input clk_i,
+ input rst_ni,
+
+ // ins req interface
+ input logic [RngBusWidth-1:0] entropy_bit_i,
+ input logic entropy_bit_vld_i,
+ input logic clear_i,
+ input logic active_i,
+ input logic [RegWidth-1:0] thresh_i,
+ input logic [RegWidth-1:0] window_i,
+ output logic [RegWidth-1:0] test_cnt_o,
+ output logic test_done_pulse_o,
+ output logic test_fail_pulse_o
+);
+
+ // signals
+ logic window_cntr_wrap;
+ logic [RngBusWidth-1:0] samples_no_match_pulse;
+ logic [RngBusWidth-1:0] pair_cnt_fail;
+
+ // flops
+ logic [RngBusWidth-1:0] prev_sample_q, prev_sample_d;
+ logic [RegWidth-1:0] pair_cntr_q[RngBusWidth], pair_cntr_d[RngBusWidth];
+ logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
+ logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ prev_sample_q <= '0;
+ pair_cntr_q <= {{RegWidth{1'b0}},{RegWidth{1'b0}},
+ {RegWidth{1'b0}},{RegWidth{1'b0}}};
+ window_cntr_q <= '0;
+ test_cnt_q <= '0;
+ end else begin
+ prev_sample_q <= prev_sample_d;
+ pair_cntr_q <= pair_cntr_d;
+ window_cntr_q <= window_cntr_d;
+ test_cnt_q <= test_cnt_d;
+ end
+
+
+ // Markov Test
+ //
+ // Test operation
+ // This test will look at pairs of bit levels per bitstream. A counter for
+ // stream will only count when the pair equals 0b01 or 0b10.
+
+
+ genvar sh;
+ generate
+ for (sh = 0; sh < RngBusWidth; sh = sh+1) begin : gen_cntrs
+
+ // bit sampler
+ assign prev_sample_d[sh] =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? entropy_bit_i[sh] :
+ prev_sample_q[sh];
+
+ // pair check
+ assign samples_no_match_pulse[sh] = entropy_bit_vld_i && window_cntr_q[0] &&
+ (prev_sample_q[sh] == !entropy_bit_i[sh]);
+
+ // pair counter
+ assign pair_cntr_d[sh] =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ samples_no_match_pulse[sh] ? (pair_cntr_q[sh]+1) :
+ pair_cntr_q[sh];
+
+ assign pair_cnt_fail[sh] = (pair_cntr_q[sh] >= thresh_i);
+
+ end
+ endgenerate
+
+
+ // Window wrap condition
+ assign window_cntr_wrap = (window_cntr_q == window_i);
+
+ // Window counter
+ assign window_cntr_d =
+ clear_i ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (window_cntr_q+1) :
+ window_cntr_q;
+
+ // Test event counter
+ assign test_cnt_d =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i && (|pair_cnt_fail) ? (test_cnt_q+1) :
+ test_cnt_q;
+
+ // the pulses will be only one clock in length
+ assign test_fail_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > '0);
+ assign test_done_pulse_o = window_cntr_wrap;
+ assign test_cnt_o = test_cnt_q;
+
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_pkg.sv
index cd45ab0..afa3320 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_pkg.sv
@@ -11,12 +11,13 @@
//-------------------------
typedef struct packed {
- logic entropy_src_vld;
- logic [31:0] entropy_src_bits;
+ logic es_ack;
+ logic [383:0] es_bits;
+ logic es_fips;
} entropy_src_hw_if_rsp_t;
typedef struct packed {
- logic entropy_src_rdy;
+ logic es_req;
} entropy_src_hw_if_req_t;
typedef struct packed {
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
index b4c9813..12116f2 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -8,6 +8,7 @@
// Param list
parameter int EsFifoDepth = 32;
+ parameter int NumAlerts = 1;
////////////////////////////
// Typedefs for registers //
@@ -18,10 +19,7 @@
} es_entropy_valid;
struct packed {
logic q;
- } es_rct_failed;
- struct packed {
- logic q;
- } es_apt_failed;
+ } es_health_test_failed;
struct packed {
logic q;
} es_fifo_err;
@@ -33,10 +31,7 @@
} es_entropy_valid;
struct packed {
logic q;
- } es_rct_failed;
- struct packed {
- logic q;
- } es_apt_failed;
+ } es_health_test_failed;
struct packed {
logic q;
} es_fifo_err;
@@ -50,11 +45,7 @@
struct packed {
logic q;
logic qe;
- } es_rct_failed;
- struct packed {
- logic q;
- logic qe;
- } es_apt_failed;
+ } es_health_test_failed;
struct packed {
logic q;
logic qe;
@@ -63,7 +54,7 @@
typedef struct packed {
logic q;
- } entropy_src_reg2hw_es_regen_reg_t;
+ } entropy_src_reg2hw_regen_reg_t;
typedef struct packed {
struct packed {
@@ -71,50 +62,109 @@
} enable;
struct packed {
logic q;
- } rng_src_en;
+ } boot_bypass_disable;
struct packed {
logic q;
- } rct_en;
+ } repcnt_disable;
struct packed {
logic q;
- } apt_en;
+ } adaptp_disable;
+ struct packed {
+ logic q;
+ } bucket_disable;
+ struct packed {
+ logic q;
+ } markov_disable;
+ struct packed {
+ logic q;
+ } health_test_clr;
struct packed {
logic q;
} rng_bit_en;
struct packed {
logic [1:0] q;
} rng_bit_sel;
- } entropy_src_reg2hw_es_conf_reg_t;
+ } entropy_src_reg2hw_conf_reg_t;
typedef struct packed {
logic [15:0] q;
- } entropy_src_reg2hw_es_rct_health_reg_t;
+ } entropy_src_reg2hw_rate_reg_t;
typedef struct packed {
struct packed {
- logic [15:0] q;
- } apt_max;
+ logic q;
+ } es_route;
struct packed {
- logic [15:0] q;
- } apt_win;
- } entropy_src_reg2hw_es_apt_health_reg_t;
+ logic q;
+ } es_type;
+ } entropy_src_reg2hw_entropy_control_reg_t;
typedef struct packed {
logic [31:0] q;
logic re;
- } entropy_src_reg2hw_es_entropy_reg_t;
+ } entropy_src_reg2hw_entropy_data_reg_t;
typedef struct packed {
- logic [2:0] q;
- } entropy_src_reg2hw_es_thresh_reg_t;
+ struct packed {
+ logic [15:0] q;
+ } fips_window;
+ struct packed {
+ logic [15:0] q;
+ } bypass_window;
+ } entropy_src_reg2hw_health_test_windows_reg_t;
typedef struct packed {
- logic [15:0] q;
- } entropy_src_reg2hw_es_rate_reg_t;
+ struct packed {
+ logic [15:0] q;
+ } fips_repcnt_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_repcnt_thresh;
+ } entropy_src_reg2hw_repcnt_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ } fips_adaptp_hi_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_adaptp_hi_thresh;
+ } entropy_src_reg2hw_adaptp_hi_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ } fips_adaptp_lo_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_adaptp_lo_thresh;
+ } entropy_src_reg2hw_adaptp_lo_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ } fips_bucket_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_bucket_thresh;
+ } entropy_src_reg2hw_bucket_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ } fips_markov_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_markov_thresh;
+ } entropy_src_reg2hw_markov_thresholds_reg_t;
typedef struct packed {
logic [3:0] q;
- } entropy_src_reg2hw_es_seed_reg_t;
+ } entropy_src_reg2hw_alert_threshold_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } entropy_src_reg2hw_seed_reg_t;
typedef struct packed {
@@ -125,11 +175,7 @@
struct packed {
logic d;
logic de;
- } es_rct_failed;
- struct packed {
- logic d;
- logic de;
- } es_apt_failed;
+ } es_health_test_failed;
struct packed {
logic d;
logic de;
@@ -138,70 +184,176 @@
typedef struct packed {
logic [31:0] d;
- } entropy_src_hw2reg_es_entropy_reg_t;
+ } entropy_src_hw2reg_entropy_data_reg_t;
typedef struct packed {
struct packed {
- logic [2:0] d;
- } dig_src_depth;
+ logic [15:0] d;
+ } fips_repcnt_hi_watermark;
struct packed {
- logic [2:0] d;
- } hwif_depth;
+ logic [15:0] d;
+ } bypass_repcnt_hi_watermark;
+ } entropy_src_hw2reg_repcnt_hi_watermarks_reg_t;
+
+ typedef struct packed {
struct packed {
- logic [4:0] d;
- } es_depth;
+ logic [15:0] d;
+ } fips_adaptp_hi_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_adaptp_hi_watermark;
+ } entropy_src_hw2reg_adaptp_hi_watermarks_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] d;
+ } fips_adaptp_lo_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_adaptp_lo_watermark;
+ } entropy_src_hw2reg_adaptp_lo_watermarks_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] d;
+ } fips_bucket_hi_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_bucket_hi_watermark;
+ } entropy_src_hw2reg_bucket_hi_watermarks_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] d;
+ } fips_markov_hi_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_markov_hi_watermark;
+ } entropy_src_hw2reg_markov_hi_watermarks_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_repcnt_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_adaptp_hi_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_adaptp_lo_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_bucket_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_markov_total_fails_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] d;
+ } any_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } repcnt_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } adaptp_hi_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } adaptp_lo_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } bucket_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } markov_fail_count;
+ } entropy_src_hw2reg_alert_fail_counts_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [1:0] d;
+ } entropy_fifo_depth;
struct packed {
logic d;
} diag;
- } entropy_src_hw2reg_es_fifo_status_reg_t;
-
- typedef struct packed {
- logic [2:0] d;
- } entropy_src_hw2reg_es_fdepthst_reg_t;
+ } entropy_src_hw2reg_debug_status_reg_t;
///////////////////////////////////////
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- entropy_src_reg2hw_intr_state_reg_t intr_state; // [128:125]
- entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [124:121]
- entropy_src_reg2hw_intr_test_reg_t intr_test; // [120:113]
- entropy_src_reg2hw_es_regen_reg_t es_regen; // [112:112]
- entropy_src_reg2hw_es_conf_reg_t es_conf; // [111:104]
- entropy_src_reg2hw_es_rct_health_reg_t es_rct_health; // [103:88]
- entropy_src_reg2hw_es_apt_health_reg_t es_apt_health; // [87:56]
- entropy_src_reg2hw_es_entropy_reg_t es_entropy; // [55:23]
- entropy_src_reg2hw_es_thresh_reg_t es_thresh; // [22:20]
- entropy_src_reg2hw_es_rate_reg_t es_rate; // [19:4]
- entropy_src_reg2hw_es_seed_reg_t es_seed; // [3:0]
+ entropy_src_reg2hw_intr_state_reg_t intr_state; // [274:272]
+ entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [271:269]
+ entropy_src_reg2hw_intr_test_reg_t intr_test; // [268:263]
+ entropy_src_reg2hw_regen_reg_t regen; // [262:262]
+ entropy_src_reg2hw_conf_reg_t conf; // [261:251]
+ entropy_src_reg2hw_rate_reg_t rate; // [250:235]
+ entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [234:233]
+ entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [232:200]
+ entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [199:168]
+ entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [167:136]
+ entropy_src_reg2hw_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [135:104]
+ entropy_src_reg2hw_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [103:72]
+ entropy_src_reg2hw_bucket_thresholds_reg_t bucket_thresholds; // [71:40]
+ entropy_src_reg2hw_markov_thresholds_reg_t markov_thresholds; // [39:8]
+ entropy_src_reg2hw_alert_threshold_reg_t alert_threshold; // [7:4]
+ entropy_src_reg2hw_seed_reg_t seed; // [3:0]
} entropy_src_reg2hw_t;
///////////////////////////////////////
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- entropy_src_hw2reg_intr_state_reg_t intr_state; // [54:51]
- entropy_src_hw2reg_es_entropy_reg_t es_entropy; // [50:18]
- entropy_src_hw2reg_es_fifo_status_reg_t es_fifo_status; // [17:18]
- entropy_src_hw2reg_es_fdepthst_reg_t es_fdepthst; // [17:18]
+ entropy_src_hw2reg_intr_state_reg_t intr_state; // [384:382]
+ entropy_src_hw2reg_entropy_data_reg_t entropy_data; // [381:349]
+ entropy_src_hw2reg_repcnt_hi_watermarks_reg_t repcnt_hi_watermarks; // [348:349]
+ entropy_src_hw2reg_adaptp_hi_watermarks_reg_t adaptp_hi_watermarks; // [348:349]
+ entropy_src_hw2reg_adaptp_lo_watermarks_reg_t adaptp_lo_watermarks; // [348:349]
+ entropy_src_hw2reg_bucket_hi_watermarks_reg_t bucket_hi_watermarks; // [348:349]
+ entropy_src_hw2reg_markov_hi_watermarks_reg_t markov_hi_watermarks; // [348:349]
+ entropy_src_hw2reg_repcnt_total_fails_reg_t repcnt_total_fails; // [348:349]
+ entropy_src_hw2reg_adaptp_hi_total_fails_reg_t adaptp_hi_total_fails; // [348:349]
+ entropy_src_hw2reg_adaptp_lo_total_fails_reg_t adaptp_lo_total_fails; // [348:349]
+ entropy_src_hw2reg_bucket_total_fails_reg_t bucket_total_fails; // [348:349]
+ entropy_src_hw2reg_markov_total_fails_reg_t markov_total_fails; // [348:349]
+ entropy_src_hw2reg_alert_fail_counts_reg_t alert_fail_counts; // [348:349]
+ entropy_src_hw2reg_debug_status_reg_t debug_status; // [348:349]
} entropy_src_hw2reg_t;
// Register Address
- parameter logic [5:0] ENTROPY_SRC_INTR_STATE_OFFSET = 6'h 0;
- parameter logic [5:0] ENTROPY_SRC_INTR_ENABLE_OFFSET = 6'h 4;
- parameter logic [5:0] ENTROPY_SRC_INTR_TEST_OFFSET = 6'h 8;
- parameter logic [5:0] ENTROPY_SRC_ES_REGEN_OFFSET = 6'h c;
- parameter logic [5:0] ENTROPY_SRC_ES_REV_OFFSET = 6'h 10;
- parameter logic [5:0] ENTROPY_SRC_ES_CONF_OFFSET = 6'h 14;
- parameter logic [5:0] ENTROPY_SRC_ES_RCT_HEALTH_OFFSET = 6'h 18;
- parameter logic [5:0] ENTROPY_SRC_ES_APT_HEALTH_OFFSET = 6'h 1c;
- parameter logic [5:0] ENTROPY_SRC_ES_ENTROPY_OFFSET = 6'h 20;
- parameter logic [5:0] ENTROPY_SRC_ES_FIFO_STATUS_OFFSET = 6'h 24;
- parameter logic [5:0] ENTROPY_SRC_ES_FDEPTHST_OFFSET = 6'h 28;
- parameter logic [5:0] ENTROPY_SRC_ES_THRESH_OFFSET = 6'h 2c;
- parameter logic [5:0] ENTROPY_SRC_ES_RATE_OFFSET = 6'h 30;
- parameter logic [5:0] ENTROPY_SRC_ES_SEED_OFFSET = 6'h 34;
+ parameter logic [6:0] ENTROPY_SRC_INTR_STATE_OFFSET = 7'h 0;
+ parameter logic [6:0] ENTROPY_SRC_INTR_ENABLE_OFFSET = 7'h 4;
+ parameter logic [6:0] ENTROPY_SRC_INTR_TEST_OFFSET = 7'h 8;
+ parameter logic [6:0] ENTROPY_SRC_REGEN_OFFSET = 7'h c;
+ parameter logic [6:0] ENTROPY_SRC_REV_OFFSET = 7'h 10;
+ parameter logic [6:0] ENTROPY_SRC_CONF_OFFSET = 7'h 14;
+ parameter logic [6:0] ENTROPY_SRC_RATE_OFFSET = 7'h 18;
+ parameter logic [6:0] ENTROPY_SRC_ENTROPY_CONTROL_OFFSET = 7'h 1c;
+ parameter logic [6:0] ENTROPY_SRC_ENTROPY_DATA_OFFSET = 7'h 20;
+ parameter logic [6:0] ENTROPY_SRC_HEALTH_TEST_WINDOWS_OFFSET = 7'h 24;
+ parameter logic [6:0] ENTROPY_SRC_REPCNT_THRESHOLDS_OFFSET = 7'h 28;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET = 7'h 2c;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET = 7'h 30;
+ parameter logic [6:0] ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET = 7'h 34;
+ parameter logic [6:0] ENTROPY_SRC_MARKOV_THRESHOLDS_OFFSET = 7'h 38;
+ parameter logic [6:0] ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET = 7'h 3c;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET = 7'h 40;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET = 7'h 44;
+ parameter logic [6:0] ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET = 7'h 48;
+ parameter logic [6:0] ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET = 7'h 4c;
+ parameter logic [6:0] ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET = 7'h 50;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET = 7'h 54;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET = 7'h 58;
+ parameter logic [6:0] ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET = 7'h 5c;
+ parameter logic [6:0] ENTROPY_SRC_MARKOV_TOTAL_FAILS_OFFSET = 7'h 60;
+ parameter logic [6:0] ENTROPY_SRC_ALERT_THRESHOLD_OFFSET = 7'h 64;
+ parameter logic [6:0] ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET = 7'h 68;
+ parameter logic [6:0] ENTROPY_SRC_DEBUG_STATUS_OFFSET = 7'h 6c;
+ parameter logic [6:0] ENTROPY_SRC_SEED_OFFSET = 7'h 70;
// Register Index
@@ -209,35 +361,65 @@
ENTROPY_SRC_INTR_STATE,
ENTROPY_SRC_INTR_ENABLE,
ENTROPY_SRC_INTR_TEST,
- ENTROPY_SRC_ES_REGEN,
- ENTROPY_SRC_ES_REV,
- ENTROPY_SRC_ES_CONF,
- ENTROPY_SRC_ES_RCT_HEALTH,
- ENTROPY_SRC_ES_APT_HEALTH,
- ENTROPY_SRC_ES_ENTROPY,
- ENTROPY_SRC_ES_FIFO_STATUS,
- ENTROPY_SRC_ES_FDEPTHST,
- ENTROPY_SRC_ES_THRESH,
- ENTROPY_SRC_ES_RATE,
- ENTROPY_SRC_ES_SEED
+ ENTROPY_SRC_REGEN,
+ ENTROPY_SRC_REV,
+ ENTROPY_SRC_CONF,
+ ENTROPY_SRC_RATE,
+ ENTROPY_SRC_ENTROPY_CONTROL,
+ ENTROPY_SRC_ENTROPY_DATA,
+ ENTROPY_SRC_HEALTH_TEST_WINDOWS,
+ ENTROPY_SRC_REPCNT_THRESHOLDS,
+ ENTROPY_SRC_ADAPTP_HI_THRESHOLDS,
+ ENTROPY_SRC_ADAPTP_LO_THRESHOLDS,
+ ENTROPY_SRC_BUCKET_THRESHOLDS,
+ ENTROPY_SRC_MARKOV_THRESHOLDS,
+ ENTROPY_SRC_REPCNT_HI_WATERMARKS,
+ ENTROPY_SRC_ADAPTP_HI_WATERMARKS,
+ ENTROPY_SRC_ADAPTP_LO_WATERMARKS,
+ ENTROPY_SRC_BUCKET_HI_WATERMARKS,
+ ENTROPY_SRC_MARKOV_HI_WATERMARKS,
+ ENTROPY_SRC_REPCNT_TOTAL_FAILS,
+ ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS,
+ ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS,
+ ENTROPY_SRC_BUCKET_TOTAL_FAILS,
+ ENTROPY_SRC_MARKOV_TOTAL_FAILS,
+ ENTROPY_SRC_ALERT_THRESHOLD,
+ ENTROPY_SRC_ALERT_FAIL_COUNTS,
+ ENTROPY_SRC_DEBUG_STATUS,
+ ENTROPY_SRC_SEED
} entropy_src_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ENTROPY_SRC_PERMIT [14] = '{
+ parameter logic [3:0] ENTROPY_SRC_PERMIT [29] = '{
4'b 0001, // index[ 0] ENTROPY_SRC_INTR_STATE
4'b 0001, // index[ 1] ENTROPY_SRC_INTR_ENABLE
4'b 0001, // index[ 2] ENTROPY_SRC_INTR_TEST
- 4'b 0001, // index[ 3] ENTROPY_SRC_ES_REGEN
- 4'b 0111, // index[ 4] ENTROPY_SRC_ES_REV
- 4'b 0011, // index[ 5] ENTROPY_SRC_ES_CONF
- 4'b 0011, // index[ 6] ENTROPY_SRC_ES_RCT_HEALTH
- 4'b 1111, // index[ 7] ENTROPY_SRC_ES_APT_HEALTH
- 4'b 1111, // index[ 8] ENTROPY_SRC_ES_ENTROPY
- 4'b 1111, // index[ 9] ENTROPY_SRC_ES_FIFO_STATUS
- 4'b 0001, // index[10] ENTROPY_SRC_ES_FDEPTHST
- 4'b 0001, // index[11] ENTROPY_SRC_ES_THRESH
- 4'b 0011, // index[12] ENTROPY_SRC_ES_RATE
- 4'b 0001 // index[13] ENTROPY_SRC_ES_SEED
+ 4'b 0001, // index[ 3] ENTROPY_SRC_REGEN
+ 4'b 0111, // index[ 4] ENTROPY_SRC_REV
+ 4'b 0011, // index[ 5] ENTROPY_SRC_CONF
+ 4'b 0011, // index[ 6] ENTROPY_SRC_RATE
+ 4'b 0001, // index[ 7] ENTROPY_SRC_ENTROPY_CONTROL
+ 4'b 1111, // index[ 8] ENTROPY_SRC_ENTROPY_DATA
+ 4'b 1111, // index[ 9] ENTROPY_SRC_HEALTH_TEST_WINDOWS
+ 4'b 1111, // index[10] ENTROPY_SRC_REPCNT_THRESHOLDS
+ 4'b 1111, // index[11] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS
+ 4'b 1111, // index[12] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS
+ 4'b 1111, // index[13] ENTROPY_SRC_BUCKET_THRESHOLDS
+ 4'b 1111, // index[14] ENTROPY_SRC_MARKOV_THRESHOLDS
+ 4'b 1111, // index[15] ENTROPY_SRC_REPCNT_HI_WATERMARKS
+ 4'b 1111, // index[16] ENTROPY_SRC_ADAPTP_HI_WATERMARKS
+ 4'b 1111, // index[17] ENTROPY_SRC_ADAPTP_LO_WATERMARKS
+ 4'b 1111, // index[18] ENTROPY_SRC_BUCKET_HI_WATERMARKS
+ 4'b 1111, // index[19] ENTROPY_SRC_MARKOV_HI_WATERMARKS
+ 4'b 1111, // index[20] ENTROPY_SRC_REPCNT_TOTAL_FAILS
+ 4'b 1111, // index[21] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS
+ 4'b 1111, // index[22] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS
+ 4'b 1111, // index[23] ENTROPY_SRC_BUCKET_TOTAL_FAILS
+ 4'b 1111, // index[24] ENTROPY_SRC_MARKOV_TOTAL_FAILS
+ 4'b 0001, // index[25] ENTROPY_SRC_ALERT_THRESHOLD
+ 4'b 0111, // index[26] ENTROPY_SRC_ALERT_FAIL_COUNTS
+ 4'b 1111, // index[27] ENTROPY_SRC_DEBUG_STATUS
+ 4'b 0001 // index[28] ENTROPY_SRC_SEED
};
endpackage
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
index bd27cc3..a49f03d 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
@@ -23,7 +23,7 @@
import entropy_src_reg_pkg::* ;
- localparam int AW = 6;
+ localparam int AW = 7;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
@@ -74,89 +74,159 @@
logic intr_state_es_entropy_valid_qs;
logic intr_state_es_entropy_valid_wd;
logic intr_state_es_entropy_valid_we;
- logic intr_state_es_rct_failed_qs;
- logic intr_state_es_rct_failed_wd;
- logic intr_state_es_rct_failed_we;
- logic intr_state_es_apt_failed_qs;
- logic intr_state_es_apt_failed_wd;
- logic intr_state_es_apt_failed_we;
+ logic intr_state_es_health_test_failed_qs;
+ logic intr_state_es_health_test_failed_wd;
+ logic intr_state_es_health_test_failed_we;
logic intr_state_es_fifo_err_qs;
logic intr_state_es_fifo_err_wd;
logic intr_state_es_fifo_err_we;
logic intr_enable_es_entropy_valid_qs;
logic intr_enable_es_entropy_valid_wd;
logic intr_enable_es_entropy_valid_we;
- logic intr_enable_es_rct_failed_qs;
- logic intr_enable_es_rct_failed_wd;
- logic intr_enable_es_rct_failed_we;
- logic intr_enable_es_apt_failed_qs;
- logic intr_enable_es_apt_failed_wd;
- logic intr_enable_es_apt_failed_we;
+ logic intr_enable_es_health_test_failed_qs;
+ logic intr_enable_es_health_test_failed_wd;
+ logic intr_enable_es_health_test_failed_we;
logic intr_enable_es_fifo_err_qs;
logic intr_enable_es_fifo_err_wd;
logic intr_enable_es_fifo_err_we;
logic intr_test_es_entropy_valid_wd;
logic intr_test_es_entropy_valid_we;
- logic intr_test_es_rct_failed_wd;
- logic intr_test_es_rct_failed_we;
- logic intr_test_es_apt_failed_wd;
- logic intr_test_es_apt_failed_we;
+ logic intr_test_es_health_test_failed_wd;
+ logic intr_test_es_health_test_failed_we;
logic intr_test_es_fifo_err_wd;
logic intr_test_es_fifo_err_we;
- logic es_regen_qs;
- logic es_regen_wd;
- logic es_regen_we;
- logic [7:0] es_rev_abi_revision_qs;
- logic [7:0] es_rev_hw_revision_qs;
- logic [7:0] es_rev_chip_type_qs;
- logic [1:0] es_conf_enable_qs;
- logic [1:0] es_conf_enable_wd;
- logic es_conf_enable_we;
- logic es_conf_rng_src_en_qs;
- logic es_conf_rng_src_en_wd;
- logic es_conf_rng_src_en_we;
- logic es_conf_rct_en_qs;
- logic es_conf_rct_en_wd;
- logic es_conf_rct_en_we;
- logic es_conf_apt_en_qs;
- logic es_conf_apt_en_wd;
- logic es_conf_apt_en_we;
- logic es_conf_rng_bit_en_qs;
- logic es_conf_rng_bit_en_wd;
- logic es_conf_rng_bit_en_we;
- logic [1:0] es_conf_rng_bit_sel_qs;
- logic [1:0] es_conf_rng_bit_sel_wd;
- logic es_conf_rng_bit_sel_we;
- logic [15:0] es_rct_health_qs;
- logic [15:0] es_rct_health_wd;
- logic es_rct_health_we;
- logic [15:0] es_apt_health_apt_max_qs;
- logic [15:0] es_apt_health_apt_max_wd;
- logic es_apt_health_apt_max_we;
- logic [15:0] es_apt_health_apt_win_qs;
- logic [15:0] es_apt_health_apt_win_wd;
- logic es_apt_health_apt_win_we;
- logic [31:0] es_entropy_qs;
- logic es_entropy_re;
- logic [2:0] es_fifo_status_dig_src_depth_qs;
- logic es_fifo_status_dig_src_depth_re;
- logic [2:0] es_fifo_status_hwif_depth_qs;
- logic es_fifo_status_hwif_depth_re;
- logic [4:0] es_fifo_status_es_depth_qs;
- logic es_fifo_status_es_depth_re;
- logic es_fifo_status_diag_qs;
- logic es_fifo_status_diag_re;
- logic [2:0] es_fdepthst_qs;
- logic es_fdepthst_re;
- logic [2:0] es_thresh_qs;
- logic [2:0] es_thresh_wd;
- logic es_thresh_we;
- logic [15:0] es_rate_qs;
- logic [15:0] es_rate_wd;
- logic es_rate_we;
- logic [3:0] es_seed_qs;
- logic [3:0] es_seed_wd;
- logic es_seed_we;
+ logic regen_qs;
+ logic regen_wd;
+ logic regen_we;
+ logic [7:0] rev_abi_revision_qs;
+ logic [7:0] rev_hw_revision_qs;
+ logic [7:0] rev_chip_type_qs;
+ logic [1:0] conf_enable_qs;
+ logic [1:0] conf_enable_wd;
+ logic conf_enable_we;
+ logic conf_boot_bypass_disable_qs;
+ logic conf_boot_bypass_disable_wd;
+ logic conf_boot_bypass_disable_we;
+ logic conf_repcnt_disable_qs;
+ logic conf_repcnt_disable_wd;
+ logic conf_repcnt_disable_we;
+ logic conf_adaptp_disable_qs;
+ logic conf_adaptp_disable_wd;
+ logic conf_adaptp_disable_we;
+ logic conf_bucket_disable_qs;
+ logic conf_bucket_disable_wd;
+ logic conf_bucket_disable_we;
+ logic conf_markov_disable_qs;
+ logic conf_markov_disable_wd;
+ logic conf_markov_disable_we;
+ logic conf_health_test_clr_qs;
+ logic conf_health_test_clr_wd;
+ logic conf_health_test_clr_we;
+ logic conf_rng_bit_en_qs;
+ logic conf_rng_bit_en_wd;
+ logic conf_rng_bit_en_we;
+ logic [1:0] conf_rng_bit_sel_qs;
+ logic [1:0] conf_rng_bit_sel_wd;
+ logic conf_rng_bit_sel_we;
+ logic [15:0] rate_qs;
+ logic [15:0] rate_wd;
+ logic rate_we;
+ logic entropy_control_es_route_qs;
+ logic entropy_control_es_route_wd;
+ logic entropy_control_es_route_we;
+ logic entropy_control_es_type_qs;
+ logic entropy_control_es_type_wd;
+ logic entropy_control_es_type_we;
+ logic [31:0] entropy_data_qs;
+ logic entropy_data_re;
+ logic [15:0] health_test_windows_fips_window_qs;
+ logic [15:0] health_test_windows_fips_window_wd;
+ logic health_test_windows_fips_window_we;
+ logic [15:0] health_test_windows_bypass_window_qs;
+ logic [15:0] health_test_windows_bypass_window_wd;
+ logic health_test_windows_bypass_window_we;
+ logic [15:0] repcnt_thresholds_fips_repcnt_thresh_qs;
+ logic [15:0] repcnt_thresholds_fips_repcnt_thresh_wd;
+ logic repcnt_thresholds_fips_repcnt_thresh_we;
+ logic [15:0] repcnt_thresholds_bypass_repcnt_thresh_qs;
+ logic [15:0] repcnt_thresholds_bypass_repcnt_thresh_wd;
+ logic repcnt_thresholds_bypass_repcnt_thresh_we;
+ logic [15:0] adaptp_hi_thresholds_fips_adaptp_hi_thresh_qs;
+ logic [15:0] adaptp_hi_thresholds_fips_adaptp_hi_thresh_wd;
+ logic adaptp_hi_thresholds_fips_adaptp_hi_thresh_we;
+ logic [15:0] adaptp_hi_thresholds_bypass_adaptp_hi_thresh_qs;
+ logic [15:0] adaptp_hi_thresholds_bypass_adaptp_hi_thresh_wd;
+ logic adaptp_hi_thresholds_bypass_adaptp_hi_thresh_we;
+ logic [15:0] adaptp_lo_thresholds_fips_adaptp_lo_thresh_qs;
+ logic [15:0] adaptp_lo_thresholds_fips_adaptp_lo_thresh_wd;
+ logic adaptp_lo_thresholds_fips_adaptp_lo_thresh_we;
+ logic [15:0] adaptp_lo_thresholds_bypass_adaptp_lo_thresh_qs;
+ logic [15:0] adaptp_lo_thresholds_bypass_adaptp_lo_thresh_wd;
+ logic adaptp_lo_thresholds_bypass_adaptp_lo_thresh_we;
+ logic [15:0] bucket_thresholds_fips_bucket_thresh_qs;
+ logic [15:0] bucket_thresholds_fips_bucket_thresh_wd;
+ logic bucket_thresholds_fips_bucket_thresh_we;
+ logic [15:0] bucket_thresholds_bypass_bucket_thresh_qs;
+ logic [15:0] bucket_thresholds_bypass_bucket_thresh_wd;
+ logic bucket_thresholds_bypass_bucket_thresh_we;
+ logic [15:0] markov_thresholds_fips_markov_thresh_qs;
+ logic [15:0] markov_thresholds_fips_markov_thresh_wd;
+ logic markov_thresholds_fips_markov_thresh_we;
+ logic [15:0] markov_thresholds_bypass_markov_thresh_qs;
+ logic [15:0] markov_thresholds_bypass_markov_thresh_wd;
+ logic markov_thresholds_bypass_markov_thresh_we;
+ logic [15:0] repcnt_hi_watermarks_fips_repcnt_hi_watermark_qs;
+ logic repcnt_hi_watermarks_fips_repcnt_hi_watermark_re;
+ logic [15:0] repcnt_hi_watermarks_bypass_repcnt_hi_watermark_qs;
+ logic repcnt_hi_watermarks_bypass_repcnt_hi_watermark_re;
+ logic [15:0] adaptp_hi_watermarks_fips_adaptp_hi_watermark_qs;
+ logic adaptp_hi_watermarks_fips_adaptp_hi_watermark_re;
+ logic [15:0] adaptp_hi_watermarks_bypass_adaptp_hi_watermark_qs;
+ logic adaptp_hi_watermarks_bypass_adaptp_hi_watermark_re;
+ logic [15:0] adaptp_lo_watermarks_fips_adaptp_lo_watermark_qs;
+ logic adaptp_lo_watermarks_fips_adaptp_lo_watermark_re;
+ logic [15:0] adaptp_lo_watermarks_bypass_adaptp_lo_watermark_qs;
+ logic adaptp_lo_watermarks_bypass_adaptp_lo_watermark_re;
+ logic [15:0] bucket_hi_watermarks_fips_bucket_hi_watermark_qs;
+ logic bucket_hi_watermarks_fips_bucket_hi_watermark_re;
+ logic [15:0] bucket_hi_watermarks_bypass_bucket_hi_watermark_qs;
+ logic bucket_hi_watermarks_bypass_bucket_hi_watermark_re;
+ logic [15:0] markov_hi_watermarks_fips_markov_hi_watermark_qs;
+ logic markov_hi_watermarks_fips_markov_hi_watermark_re;
+ logic [15:0] markov_hi_watermarks_bypass_markov_hi_watermark_qs;
+ logic markov_hi_watermarks_bypass_markov_hi_watermark_re;
+ logic [31:0] repcnt_total_fails_qs;
+ logic repcnt_total_fails_re;
+ logic [31:0] adaptp_hi_total_fails_qs;
+ logic adaptp_hi_total_fails_re;
+ logic [31:0] adaptp_lo_total_fails_qs;
+ logic adaptp_lo_total_fails_re;
+ logic [31:0] bucket_total_fails_qs;
+ logic bucket_total_fails_re;
+ logic [31:0] markov_total_fails_qs;
+ logic markov_total_fails_re;
+ logic [3:0] alert_threshold_qs;
+ logic [3:0] alert_threshold_wd;
+ logic alert_threshold_we;
+ logic [3:0] alert_fail_counts_any_fail_count_qs;
+ logic alert_fail_counts_any_fail_count_re;
+ logic [3:0] alert_fail_counts_repcnt_fail_count_qs;
+ logic alert_fail_counts_repcnt_fail_count_re;
+ logic [3:0] alert_fail_counts_adaptp_hi_fail_count_qs;
+ logic alert_fail_counts_adaptp_hi_fail_count_re;
+ logic [3:0] alert_fail_counts_adaptp_lo_fail_count_qs;
+ logic alert_fail_counts_adaptp_lo_fail_count_re;
+ logic [3:0] alert_fail_counts_bucket_fail_count_qs;
+ logic alert_fail_counts_bucket_fail_count_re;
+ logic [3:0] alert_fail_counts_markov_fail_count_qs;
+ logic alert_fail_counts_markov_fail_count_re;
+ logic [1:0] debug_status_entropy_fifo_depth_qs;
+ logic debug_status_entropy_fifo_depth_re;
+ logic debug_status_diag_qs;
+ logic debug_status_diag_re;
+ logic [3:0] seed_qs;
+ logic [3:0] seed_wd;
+ logic seed_we;
// Register instances
// R[intr_state]: V(False)
@@ -187,59 +257,33 @@
);
- // F[es_rct_failed]: 1:1
+ // F[es_health_test_failed]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
- ) u_intr_state_es_rct_failed (
+ ) u_intr_state_es_health_test_failed (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_state_es_rct_failed_we),
- .wd (intr_state_es_rct_failed_wd),
+ .we (intr_state_es_health_test_failed_we),
+ .wd (intr_state_es_health_test_failed_wd),
// from internal hardware
- .de (hw2reg.intr_state.es_rct_failed.de),
- .d (hw2reg.intr_state.es_rct_failed.d ),
+ .de (hw2reg.intr_state.es_health_test_failed.de),
+ .d (hw2reg.intr_state.es_health_test_failed.d ),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.es_rct_failed.q ),
+ .q (reg2hw.intr_state.es_health_test_failed.q ),
// to register interface (read)
- .qs (intr_state_es_rct_failed_qs)
+ .qs (intr_state_es_health_test_failed_qs)
);
- // F[es_apt_failed]: 2:2
- prim_subreg #(
- .DW (1),
- .SWACCESS("W1C"),
- .RESVAL (1'h0)
- ) u_intr_state_es_apt_failed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (intr_state_es_apt_failed_we),
- .wd (intr_state_es_apt_failed_wd),
-
- // from internal hardware
- .de (hw2reg.intr_state.es_apt_failed.de),
- .d (hw2reg.intr_state.es_apt_failed.d ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_state.es_apt_failed.q ),
-
- // to register interface (read)
- .qs (intr_state_es_apt_failed_qs)
- );
-
-
- // F[es_fifo_err]: 3:3
+ // F[es_fifo_err]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
@@ -293,18 +337,18 @@
);
- // F[es_rct_failed]: 1:1
+ // F[es_health_test_failed]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_intr_enable_es_rct_failed (
+ ) u_intr_enable_es_health_test_failed (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_enable_es_rct_failed_we),
- .wd (intr_enable_es_rct_failed_wd),
+ .we (intr_enable_es_health_test_failed_we),
+ .wd (intr_enable_es_health_test_failed_wd),
// from internal hardware
.de (1'b0),
@@ -312,40 +356,14 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.es_rct_failed.q ),
+ .q (reg2hw.intr_enable.es_health_test_failed.q ),
// to register interface (read)
- .qs (intr_enable_es_rct_failed_qs)
+ .qs (intr_enable_es_health_test_failed_qs)
);
- // F[es_apt_failed]: 2:2
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_intr_enable_es_apt_failed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (intr_enable_es_apt_failed_we),
- .wd (intr_enable_es_apt_failed_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_enable.es_apt_failed.q ),
-
- // to register interface (read)
- .qs (intr_enable_es_apt_failed_qs)
- );
-
-
- // F[es_fifo_err]: 3:3
+ // F[es_fifo_err]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -388,37 +406,22 @@
);
- // F[es_rct_failed]: 1:1
+ // F[es_health_test_failed]: 1:1
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_es_rct_failed (
+ ) u_intr_test_es_health_test_failed (
.re (1'b0),
- .we (intr_test_es_rct_failed_we),
- .wd (intr_test_es_rct_failed_wd),
+ .we (intr_test_es_health_test_failed_we),
+ .wd (intr_test_es_health_test_failed_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.es_rct_failed.qe),
- .q (reg2hw.intr_test.es_rct_failed.q ),
+ .qe (reg2hw.intr_test.es_health_test_failed.qe),
+ .q (reg2hw.intr_test.es_health_test_failed.q ),
.qs ()
);
- // F[es_apt_failed]: 2:2
- prim_subreg_ext #(
- .DW (1)
- ) u_intr_test_es_apt_failed (
- .re (1'b0),
- .we (intr_test_es_apt_failed_we),
- .wd (intr_test_es_apt_failed_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.intr_test.es_apt_failed.qe),
- .q (reg2hw.intr_test.es_apt_failed.q ),
- .qs ()
- );
-
-
- // F[es_fifo_err]: 3:3
+ // F[es_fifo_err]: 2:2
prim_subreg_ext #(
.DW (1)
) u_intr_test_es_fifo_err (
@@ -433,19 +436,19 @@
);
- // R[es_regen]: V(False)
+ // R[regen]: V(False)
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h1)
- ) u_es_regen (
+ ) u_regen (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (es_regen_we),
- .wd (es_regen_wd),
+ .we (regen_we),
+ .wd (regen_wd),
// from internal hardware
.de (1'b0),
@@ -453,44 +456,44 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_regen.q ),
+ .q (reg2hw.regen.q ),
// to register interface (read)
- .qs (es_regen_qs)
+ .qs (regen_qs)
);
- // R[es_rev]: V(False)
+ // R[rev]: V(False)
// F[abi_revision]: 7:0
// constant-only read
- assign es_rev_abi_revision_qs = 8'h1;
+ assign rev_abi_revision_qs = 8'h3;
// F[hw_revision]: 15:8
// constant-only read
- assign es_rev_hw_revision_qs = 8'h1;
+ assign rev_hw_revision_qs = 8'h3;
// F[chip_type]: 23:16
// constant-only read
- assign es_rev_chip_type_qs = 8'h1;
+ assign rev_chip_type_qs = 8'h1;
- // R[es_conf]: V(False)
+ // R[conf]: V(False)
// F[enable]: 1:0
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h0)
- ) u_es_conf_enable (
+ ) u_conf_enable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_enable_we & es_regen_qs),
- .wd (es_conf_enable_wd),
+ .we (conf_enable_we & regen_qs),
+ .wd (conf_enable_wd),
// from internal hardware
.de (1'b0),
@@ -498,25 +501,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.enable.q ),
+ .q (reg2hw.conf.enable.q ),
// to register interface (read)
- .qs (es_conf_enable_qs)
+ .qs (conf_enable_qs)
);
- // F[rng_src_en]: 4:4
+ // F[boot_bypass_disable]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_es_conf_rng_src_en (
+ ) u_conf_boot_bypass_disable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_rng_src_en_we & es_regen_qs),
- .wd (es_conf_rng_src_en_wd),
+ .we (conf_boot_bypass_disable_we & regen_qs),
+ .wd (conf_boot_bypass_disable_wd),
// from internal hardware
.de (1'b0),
@@ -524,25 +527,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.rng_src_en.q ),
+ .q (reg2hw.conf.boot_bypass_disable.q ),
// to register interface (read)
- .qs (es_conf_rng_src_en_qs)
+ .qs (conf_boot_bypass_disable_qs)
);
- // F[rct_en]: 5:5
+ // F[repcnt_disable]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_es_conf_rct_en (
+ ) u_conf_repcnt_disable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_rct_en_we & es_regen_qs),
- .wd (es_conf_rct_en_wd),
+ .we (conf_repcnt_disable_we & regen_qs),
+ .wd (conf_repcnt_disable_wd),
// from internal hardware
.de (1'b0),
@@ -550,25 +553,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.rct_en.q ),
+ .q (reg2hw.conf.repcnt_disable.q ),
// to register interface (read)
- .qs (es_conf_rct_en_qs)
+ .qs (conf_repcnt_disable_qs)
);
- // F[apt_en]: 6:6
+ // F[adaptp_disable]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_es_conf_apt_en (
+ ) u_conf_adaptp_disable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_apt_en_we & es_regen_qs),
- .wd (es_conf_apt_en_wd),
+ .we (conf_adaptp_disable_we & regen_qs),
+ .wd (conf_adaptp_disable_wd),
// from internal hardware
.de (1'b0),
@@ -576,25 +579,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.apt_en.q ),
+ .q (reg2hw.conf.adaptp_disable.q ),
// to register interface (read)
- .qs (es_conf_apt_en_qs)
+ .qs (conf_adaptp_disable_qs)
);
- // F[rng_bit_en]: 8:8
+ // F[bucket_disable]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_es_conf_rng_bit_en (
+ ) u_conf_bucket_disable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_rng_bit_en_we & es_regen_qs),
- .wd (es_conf_rng_bit_en_wd),
+ .we (conf_bucket_disable_we & regen_qs),
+ .wd (conf_bucket_disable_wd),
// from internal hardware
.de (1'b0),
@@ -602,25 +605,103 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.rng_bit_en.q ),
+ .q (reg2hw.conf.bucket_disable.q ),
// to register interface (read)
- .qs (es_conf_rng_bit_en_qs)
+ .qs (conf_bucket_disable_qs)
);
- // F[rng_bit_sel]: 10:9
+ // F[markov_disable]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_conf_markov_disable (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (conf_markov_disable_we & regen_qs),
+ .wd (conf_markov_disable_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.conf.markov_disable.q ),
+
+ // to register interface (read)
+ .qs (conf_markov_disable_qs)
+ );
+
+
+ // F[health_test_clr]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_conf_health_test_clr (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (conf_health_test_clr_we & regen_qs),
+ .wd (conf_health_test_clr_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.conf.health_test_clr.q ),
+
+ // to register interface (read)
+ .qs (conf_health_test_clr_qs)
+ );
+
+
+ // F[rng_bit_en]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_conf_rng_bit_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (conf_rng_bit_en_we & regen_qs),
+ .wd (conf_rng_bit_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.conf.rng_bit_en.q ),
+
+ // to register interface (read)
+ .qs (conf_rng_bit_en_qs)
+ );
+
+
+ // F[rng_bit_sel]: 11:10
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h0)
- ) u_es_conf_rng_bit_sel (
+ ) u_conf_rng_bit_sel (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_rng_bit_sel_we & es_regen_qs),
- .wd (es_conf_rng_bit_sel_wd),
+ .we (conf_rng_bit_sel_we & regen_qs),
+ .wd (conf_rng_bit_sel_wd),
// from internal hardware
.de (1'b0),
@@ -628,26 +709,26 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.rng_bit_sel.q ),
+ .q (reg2hw.conf.rng_bit_sel.q ),
// to register interface (read)
- .qs (es_conf_rng_bit_sel_qs)
+ .qs (conf_rng_bit_sel_qs)
);
- // R[es_rct_health]: V(False)
+ // R[rate]: V(False)
prim_subreg #(
.DW (16),
.SWACCESS("RW"),
- .RESVAL (16'hb)
- ) u_es_rct_health (
+ .RESVAL (16'h7d0)
+ ) u_rate (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface (qualified with register enable)
- .we (es_rct_health_we & es_regen_qs),
- .wd (es_rct_health_wd),
+ // from register interface
+ .we (rate_we),
+ .wd (rate_wd),
// from internal hardware
.de (1'b0),
@@ -655,27 +736,27 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_rct_health.q ),
+ .q (reg2hw.rate.q ),
// to register interface (read)
- .qs (es_rct_health_qs)
+ .qs (rate_qs)
);
- // R[es_apt_health]: V(False)
+ // R[entropy_control]: V(False)
- // F[apt_max]: 15:0
+ // F[es_route]: 0:0
prim_subreg #(
- .DW (16),
+ .DW (1),
.SWACCESS("RW"),
- .RESVAL (16'h298)
- ) u_es_apt_health_apt_max (
+ .RESVAL (1'h0)
+ ) u_entropy_control_es_route (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_apt_health_apt_max_we & es_regen_qs),
- .wd (es_apt_health_apt_max_wd),
+ .we (entropy_control_es_route_we & regen_qs),
+ .wd (entropy_control_es_route_wd),
// from internal hardware
.de (1'b0),
@@ -683,25 +764,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_apt_health.apt_max.q ),
+ .q (reg2hw.entropy_control.es_route.q ),
// to register interface (read)
- .qs (es_apt_health_apt_max_qs)
+ .qs (entropy_control_es_route_qs)
);
- // F[apt_win]: 31:16
+ // F[es_type]: 1:1
prim_subreg #(
- .DW (16),
+ .DW (1),
.SWACCESS("RW"),
- .RESVAL (16'h400)
- ) u_es_apt_health_apt_win (
+ .RESVAL (1'h0)
+ ) u_entropy_control_es_type (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_apt_health_apt_win_we & es_regen_qs),
- .wd (es_apt_health_apt_win_wd),
+ .we (entropy_control_es_type_we & regen_qs),
+ .wd (entropy_control_es_type_wd),
// from internal hardware
.de (1'b0),
@@ -709,174 +790,757 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_apt_health.apt_win.q ),
+ .q (reg2hw.entropy_control.es_type.q ),
// to register interface (read)
- .qs (es_apt_health_apt_win_qs)
+ .qs (entropy_control_es_type_qs)
);
- // R[es_entropy]: V(True)
+ // R[entropy_data]: V(True)
prim_subreg_ext #(
.DW (32)
- ) u_es_entropy (
- .re (es_entropy_re),
+ ) u_entropy_data (
+ .re (entropy_data_re),
.we (1'b0),
.wd ('0),
- .d (hw2reg.es_entropy.d),
- .qre (reg2hw.es_entropy.re),
+ .d (hw2reg.entropy_data.d),
+ .qre (reg2hw.entropy_data.re),
.qe (),
- .q (reg2hw.es_entropy.q ),
- .qs (es_entropy_qs)
+ .q (reg2hw.entropy_data.q ),
+ .qs (entropy_data_qs)
);
- // R[es_fifo_status]: V(True)
+ // R[health_test_windows]: V(False)
- // F[dig_src_depth]: 2:0
- prim_subreg_ext #(
- .DW (3)
- ) u_es_fifo_status_dig_src_depth (
- .re (es_fifo_status_dig_src_depth_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.es_fifo_status.dig_src_depth.d),
- .qre (),
+ // F[fips_window]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h100)
+ ) u_health_test_windows_fips_window (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (health_test_windows_fips_window_we & regen_qs),
+ .wd (health_test_windows_fips_window_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
.qe (),
- .q (),
- .qs (es_fifo_status_dig_src_depth_qs)
+ .q (reg2hw.health_test_windows.fips_window.q ),
+
+ // to register interface (read)
+ .qs (health_test_windows_fips_window_qs)
);
- // F[hwif_depth]: 6:4
- prim_subreg_ext #(
- .DW (3)
- ) u_es_fifo_status_hwif_depth (
- .re (es_fifo_status_hwif_depth_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.es_fifo_status.hwif_depth.d),
- .qre (),
+ // F[bypass_window]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h60)
+ ) u_health_test_windows_bypass_window (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (health_test_windows_bypass_window_we & regen_qs),
+ .wd (health_test_windows_bypass_window_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
.qe (),
- .q (),
- .qs (es_fifo_status_hwif_depth_qs)
+ .q (reg2hw.health_test_windows.bypass_window.q ),
+
+ // to register interface (read)
+ .qs (health_test_windows_bypass_window_qs)
);
- // F[es_depth]: 16:12
+ // R[repcnt_thresholds]: V(False)
+
+ // F[fips_repcnt_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h20)
+ ) u_repcnt_thresholds_fips_repcnt_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (repcnt_thresholds_fips_repcnt_thresh_we & regen_qs),
+ .wd (repcnt_thresholds_fips_repcnt_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.repcnt_thresholds.fips_repcnt_thresh.q ),
+
+ // to register interface (read)
+ .qs (repcnt_thresholds_fips_repcnt_thresh_qs)
+ );
+
+
+ // F[bypass_repcnt_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h20)
+ ) u_repcnt_thresholds_bypass_repcnt_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (repcnt_thresholds_bypass_repcnt_thresh_we & regen_qs),
+ .wd (repcnt_thresholds_bypass_repcnt_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.repcnt_thresholds.bypass_repcnt_thresh.q ),
+
+ // to register interface (read)
+ .qs (repcnt_thresholds_bypass_repcnt_thresh_qs)
+ );
+
+
+ // R[adaptp_hi_thresholds]: V(False)
+
+ // F[fips_adaptp_hi_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h256)
+ ) u_adaptp_hi_thresholds_fips_adaptp_hi_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (adaptp_hi_thresholds_fips_adaptp_hi_thresh_we & regen_qs),
+ .wd (adaptp_hi_thresholds_fips_adaptp_hi_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.adaptp_hi_thresholds.fips_adaptp_hi_thresh.q ),
+
+ // to register interface (read)
+ .qs (adaptp_hi_thresholds_fips_adaptp_hi_thresh_qs)
+ );
+
+
+ // F[bypass_adaptp_hi_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'he0)
+ ) u_adaptp_hi_thresholds_bypass_adaptp_hi_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (adaptp_hi_thresholds_bypass_adaptp_hi_thresh_we & regen_qs),
+ .wd (adaptp_hi_thresholds_bypass_adaptp_hi_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.adaptp_hi_thresholds.bypass_adaptp_hi_thresh.q ),
+
+ // to register interface (read)
+ .qs (adaptp_hi_thresholds_bypass_adaptp_hi_thresh_qs)
+ );
+
+
+ // R[adaptp_lo_thresholds]: V(False)
+
+ // F[fips_adaptp_lo_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h1aa)
+ ) u_adaptp_lo_thresholds_fips_adaptp_lo_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (adaptp_lo_thresholds_fips_adaptp_lo_thresh_we & regen_qs),
+ .wd (adaptp_lo_thresholds_fips_adaptp_lo_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.adaptp_lo_thresholds.fips_adaptp_lo_thresh.q ),
+
+ // to register interface (read)
+ .qs (adaptp_lo_thresholds_fips_adaptp_lo_thresh_qs)
+ );
+
+
+ // F[bypass_adaptp_lo_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'ha0)
+ ) u_adaptp_lo_thresholds_bypass_adaptp_lo_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (adaptp_lo_thresholds_bypass_adaptp_lo_thresh_we & regen_qs),
+ .wd (adaptp_lo_thresholds_bypass_adaptp_lo_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.adaptp_lo_thresholds.bypass_adaptp_lo_thresh.q ),
+
+ // to register interface (read)
+ .qs (adaptp_lo_thresholds_bypass_adaptp_lo_thresh_qs)
+ );
+
+
+ // R[bucket_thresholds]: V(False)
+
+ // F[fips_bucket_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h20)
+ ) u_bucket_thresholds_fips_bucket_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bucket_thresholds_fips_bucket_thresh_we & regen_qs),
+ .wd (bucket_thresholds_fips_bucket_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bucket_thresholds.fips_bucket_thresh.q ),
+
+ // to register interface (read)
+ .qs (bucket_thresholds_fips_bucket_thresh_qs)
+ );
+
+
+ // F[bypass_bucket_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h20)
+ ) u_bucket_thresholds_bypass_bucket_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bucket_thresholds_bypass_bucket_thresh_we & regen_qs),
+ .wd (bucket_thresholds_bypass_bucket_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bucket_thresholds.bypass_bucket_thresh.q ),
+
+ // to register interface (read)
+ .qs (bucket_thresholds_bypass_bucket_thresh_qs)
+ );
+
+
+ // R[markov_thresholds]: V(False)
+
+ // F[fips_markov_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h100)
+ ) u_markov_thresholds_fips_markov_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (markov_thresholds_fips_markov_thresh_we & regen_qs),
+ .wd (markov_thresholds_fips_markov_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.markov_thresholds.fips_markov_thresh.q ),
+
+ // to register interface (read)
+ .qs (markov_thresholds_fips_markov_thresh_qs)
+ );
+
+
+ // F[bypass_markov_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h60)
+ ) u_markov_thresholds_bypass_markov_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (markov_thresholds_bypass_markov_thresh_we & regen_qs),
+ .wd (markov_thresholds_bypass_markov_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.markov_thresholds.bypass_markov_thresh.q ),
+
+ // to register interface (read)
+ .qs (markov_thresholds_bypass_markov_thresh_qs)
+ );
+
+
+ // R[repcnt_hi_watermarks]: V(True)
+
+ // F[fips_repcnt_hi_watermark]: 15:0
prim_subreg_ext #(
- .DW (5)
- ) u_es_fifo_status_es_depth (
- .re (es_fifo_status_es_depth_re),
+ .DW (16)
+ ) u_repcnt_hi_watermarks_fips_repcnt_hi_watermark (
+ .re (repcnt_hi_watermarks_fips_repcnt_hi_watermark_re),
.we (1'b0),
.wd ('0),
- .d (hw2reg.es_fifo_status.es_depth.d),
+ .d (hw2reg.repcnt_hi_watermarks.fips_repcnt_hi_watermark.d),
.qre (),
.qe (),
.q (),
- .qs (es_fifo_status_es_depth_qs)
+ .qs (repcnt_hi_watermarks_fips_repcnt_hi_watermark_qs)
+ );
+
+
+ // F[bypass_repcnt_hi_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_repcnt_hi_watermarks_bypass_repcnt_hi_watermark (
+ .re (repcnt_hi_watermarks_bypass_repcnt_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.repcnt_hi_watermarks.bypass_repcnt_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (repcnt_hi_watermarks_bypass_repcnt_hi_watermark_qs)
+ );
+
+
+ // R[adaptp_hi_watermarks]: V(True)
+
+ // F[fips_adaptp_hi_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_adaptp_hi_watermarks_fips_adaptp_hi_watermark (
+ .re (adaptp_hi_watermarks_fips_adaptp_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_hi_watermarks.fips_adaptp_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_hi_watermarks_fips_adaptp_hi_watermark_qs)
+ );
+
+
+ // F[bypass_adaptp_hi_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_adaptp_hi_watermarks_bypass_adaptp_hi_watermark (
+ .re (adaptp_hi_watermarks_bypass_adaptp_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_hi_watermarks.bypass_adaptp_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_hi_watermarks_bypass_adaptp_hi_watermark_qs)
+ );
+
+
+ // R[adaptp_lo_watermarks]: V(True)
+
+ // F[fips_adaptp_lo_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_adaptp_lo_watermarks_fips_adaptp_lo_watermark (
+ .re (adaptp_lo_watermarks_fips_adaptp_lo_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_lo_watermarks.fips_adaptp_lo_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_lo_watermarks_fips_adaptp_lo_watermark_qs)
+ );
+
+
+ // F[bypass_adaptp_lo_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_adaptp_lo_watermarks_bypass_adaptp_lo_watermark (
+ .re (adaptp_lo_watermarks_bypass_adaptp_lo_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_lo_watermarks.bypass_adaptp_lo_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_lo_watermarks_bypass_adaptp_lo_watermark_qs)
+ );
+
+
+ // R[bucket_hi_watermarks]: V(True)
+
+ // F[fips_bucket_hi_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_bucket_hi_watermarks_fips_bucket_hi_watermark (
+ .re (bucket_hi_watermarks_fips_bucket_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.bucket_hi_watermarks.fips_bucket_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (bucket_hi_watermarks_fips_bucket_hi_watermark_qs)
+ );
+
+
+ // F[bypass_bucket_hi_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_bucket_hi_watermarks_bypass_bucket_hi_watermark (
+ .re (bucket_hi_watermarks_bypass_bucket_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.bucket_hi_watermarks.bypass_bucket_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (bucket_hi_watermarks_bypass_bucket_hi_watermark_qs)
+ );
+
+
+ // R[markov_hi_watermarks]: V(True)
+
+ // F[fips_markov_hi_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_markov_hi_watermarks_fips_markov_hi_watermark (
+ .re (markov_hi_watermarks_fips_markov_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.markov_hi_watermarks.fips_markov_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (markov_hi_watermarks_fips_markov_hi_watermark_qs)
+ );
+
+
+ // F[bypass_markov_hi_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_markov_hi_watermarks_bypass_markov_hi_watermark (
+ .re (markov_hi_watermarks_bypass_markov_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.markov_hi_watermarks.bypass_markov_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (markov_hi_watermarks_bypass_markov_hi_watermark_qs)
+ );
+
+
+ // R[repcnt_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_repcnt_total_fails (
+ .re (repcnt_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.repcnt_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (repcnt_total_fails_qs)
+ );
+
+
+ // R[adaptp_hi_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_adaptp_hi_total_fails (
+ .re (adaptp_hi_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_hi_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_hi_total_fails_qs)
+ );
+
+
+ // R[adaptp_lo_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_adaptp_lo_total_fails (
+ .re (adaptp_lo_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_lo_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_lo_total_fails_qs)
+ );
+
+
+ // R[bucket_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_bucket_total_fails (
+ .re (bucket_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.bucket_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (bucket_total_fails_qs)
+ );
+
+
+ // R[markov_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_markov_total_fails (
+ .re (markov_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.markov_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (markov_total_fails_qs)
+ );
+
+
+ // R[alert_threshold]: V(False)
+
+ prim_subreg #(
+ .DW (4),
+ .SWACCESS("RW"),
+ .RESVAL (4'h2)
+ ) u_alert_threshold (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_threshold_we & regen_qs),
+ .wd (alert_threshold_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_threshold.q ),
+
+ // to register interface (read)
+ .qs (alert_threshold_qs)
+ );
+
+
+ // R[alert_fail_counts]: V(True)
+
+ // F[any_fail_count]: 3:0
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_any_fail_count (
+ .re (alert_fail_counts_any_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.any_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_any_fail_count_qs)
+ );
+
+
+ // F[repcnt_fail_count]: 7:4
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_repcnt_fail_count (
+ .re (alert_fail_counts_repcnt_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.repcnt_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_repcnt_fail_count_qs)
+ );
+
+
+ // F[adaptp_hi_fail_count]: 11:8
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_adaptp_hi_fail_count (
+ .re (alert_fail_counts_adaptp_hi_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.adaptp_hi_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_adaptp_hi_fail_count_qs)
+ );
+
+
+ // F[adaptp_lo_fail_count]: 15:12
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_adaptp_lo_fail_count (
+ .re (alert_fail_counts_adaptp_lo_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.adaptp_lo_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_adaptp_lo_fail_count_qs)
+ );
+
+
+ // F[bucket_fail_count]: 19:16
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_bucket_fail_count (
+ .re (alert_fail_counts_bucket_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.bucket_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_bucket_fail_count_qs)
+ );
+
+
+ // F[markov_fail_count]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_markov_fail_count (
+ .re (alert_fail_counts_markov_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.markov_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_markov_fail_count_qs)
+ );
+
+
+ // R[debug_status]: V(True)
+
+ // F[entropy_fifo_depth]: 1:0
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_debug_status_entropy_fifo_depth (
+ .re (debug_status_entropy_fifo_depth_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.debug_status.entropy_fifo_depth.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (debug_status_entropy_fifo_depth_qs)
);
// F[diag]: 31:31
prim_subreg_ext #(
.DW (1)
- ) u_es_fifo_status_diag (
- .re (es_fifo_status_diag_re),
+ ) u_debug_status_diag (
+ .re (debug_status_diag_re),
.we (1'b0),
.wd ('0),
- .d (hw2reg.es_fifo_status.diag.d),
+ .d (hw2reg.debug_status.diag.d),
.qre (),
.qe (),
.q (),
- .qs (es_fifo_status_diag_qs)
+ .qs (debug_status_diag_qs)
);
- // R[es_fdepthst]: V(True)
-
- prim_subreg_ext #(
- .DW (3)
- ) u_es_fdepthst (
- .re (es_fdepthst_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.es_fdepthst.d),
- .qre (),
- .qe (),
- .q (),
- .qs (es_fdepthst_qs)
- );
-
-
- // R[es_thresh]: V(False)
-
- prim_subreg #(
- .DW (3),
- .SWACCESS("RW"),
- .RESVAL (3'h0)
- ) u_es_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (es_thresh_we),
- .wd (es_thresh_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.es_thresh.q ),
-
- // to register interface (read)
- .qs (es_thresh_qs)
- );
-
-
- // R[es_rate]: V(False)
-
- prim_subreg #(
- .DW (16),
- .SWACCESS("RW"),
- .RESVAL (16'h4)
- ) u_es_rate (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (es_rate_we),
- .wd (es_rate_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.es_rate.q ),
-
- // to register interface (read)
- .qs (es_rate_qs)
- );
-
-
- // R[es_seed]: V(False)
+ // R[seed]: V(False)
prim_subreg #(
.DW (4),
.SWACCESS("RW"),
.RESVAL (4'hb)
- ) u_es_seed (
+ ) u_seed (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_seed_we & es_regen_qs),
- .wd (es_seed_wd),
+ .we (seed_we & regen_qs),
+ .wd (seed_wd),
// from internal hardware
.de (1'b0),
@@ -884,32 +1548,47 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_seed.q ),
+ .q (reg2hw.seed.q ),
// to register interface (read)
- .qs (es_seed_qs)
+ .qs (seed_qs)
);
- logic [13:0] addr_hit;
+ logic [28:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ENTROPY_SRC_INTR_STATE_OFFSET);
addr_hit[ 1] = (reg_addr == ENTROPY_SRC_INTR_ENABLE_OFFSET);
addr_hit[ 2] = (reg_addr == ENTROPY_SRC_INTR_TEST_OFFSET);
- addr_hit[ 3] = (reg_addr == ENTROPY_SRC_ES_REGEN_OFFSET);
- addr_hit[ 4] = (reg_addr == ENTROPY_SRC_ES_REV_OFFSET);
- addr_hit[ 5] = (reg_addr == ENTROPY_SRC_ES_CONF_OFFSET);
- addr_hit[ 6] = (reg_addr == ENTROPY_SRC_ES_RCT_HEALTH_OFFSET);
- addr_hit[ 7] = (reg_addr == ENTROPY_SRC_ES_APT_HEALTH_OFFSET);
- addr_hit[ 8] = (reg_addr == ENTROPY_SRC_ES_ENTROPY_OFFSET);
- addr_hit[ 9] = (reg_addr == ENTROPY_SRC_ES_FIFO_STATUS_OFFSET);
- addr_hit[10] = (reg_addr == ENTROPY_SRC_ES_FDEPTHST_OFFSET);
- addr_hit[11] = (reg_addr == ENTROPY_SRC_ES_THRESH_OFFSET);
- addr_hit[12] = (reg_addr == ENTROPY_SRC_ES_RATE_OFFSET);
- addr_hit[13] = (reg_addr == ENTROPY_SRC_ES_SEED_OFFSET);
+ addr_hit[ 3] = (reg_addr == ENTROPY_SRC_REGEN_OFFSET);
+ addr_hit[ 4] = (reg_addr == ENTROPY_SRC_REV_OFFSET);
+ addr_hit[ 5] = (reg_addr == ENTROPY_SRC_CONF_OFFSET);
+ addr_hit[ 6] = (reg_addr == ENTROPY_SRC_RATE_OFFSET);
+ addr_hit[ 7] = (reg_addr == ENTROPY_SRC_ENTROPY_CONTROL_OFFSET);
+ addr_hit[ 8] = (reg_addr == ENTROPY_SRC_ENTROPY_DATA_OFFSET);
+ addr_hit[ 9] = (reg_addr == ENTROPY_SRC_HEALTH_TEST_WINDOWS_OFFSET);
+ addr_hit[10] = (reg_addr == ENTROPY_SRC_REPCNT_THRESHOLDS_OFFSET);
+ addr_hit[11] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET);
+ addr_hit[12] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET);
+ addr_hit[13] = (reg_addr == ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET);
+ addr_hit[14] = (reg_addr == ENTROPY_SRC_MARKOV_THRESHOLDS_OFFSET);
+ addr_hit[15] = (reg_addr == ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET);
+ addr_hit[16] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET);
+ addr_hit[17] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET);
+ addr_hit[18] = (reg_addr == ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET);
+ addr_hit[19] = (reg_addr == ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET);
+ addr_hit[20] = (reg_addr == ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET);
+ addr_hit[21] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET);
+ addr_hit[22] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET);
+ addr_hit[23] = (reg_addr == ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET);
+ addr_hit[24] = (reg_addr == ENTROPY_SRC_MARKOV_TOTAL_FAILS_OFFSET);
+ addr_hit[25] = (reg_addr == ENTROPY_SRC_ALERT_THRESHOLD_OFFSET);
+ addr_hit[26] = (reg_addr == ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET);
+ addr_hit[27] = (reg_addr == ENTROPY_SRC_DEBUG_STATUS_OFFSET);
+ addr_hit[28] = (reg_addr == ENTROPY_SRC_SEED_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -931,97 +1610,181 @@
if (addr_hit[11] && reg_we && (ENTROPY_SRC_PERMIT[11] != (ENTROPY_SRC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[12] && reg_we && (ENTROPY_SRC_PERMIT[12] != (ENTROPY_SRC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[13] && reg_we && (ENTROPY_SRC_PERMIT[13] != (ENTROPY_SRC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (ENTROPY_SRC_PERMIT[14] != (ENTROPY_SRC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[15] && reg_we && (ENTROPY_SRC_PERMIT[15] != (ENTROPY_SRC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[16] && reg_we && (ENTROPY_SRC_PERMIT[16] != (ENTROPY_SRC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[17] && reg_we && (ENTROPY_SRC_PERMIT[17] != (ENTROPY_SRC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[18] && reg_we && (ENTROPY_SRC_PERMIT[18] != (ENTROPY_SRC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[19] && reg_we && (ENTROPY_SRC_PERMIT[19] != (ENTROPY_SRC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[20] && reg_we && (ENTROPY_SRC_PERMIT[20] != (ENTROPY_SRC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[21] && reg_we && (ENTROPY_SRC_PERMIT[21] != (ENTROPY_SRC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[22] && reg_we && (ENTROPY_SRC_PERMIT[22] != (ENTROPY_SRC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[23] && reg_we && (ENTROPY_SRC_PERMIT[23] != (ENTROPY_SRC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[24] && reg_we && (ENTROPY_SRC_PERMIT[24] != (ENTROPY_SRC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[25] && reg_we && (ENTROPY_SRC_PERMIT[25] != (ENTROPY_SRC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[26] && reg_we && (ENTROPY_SRC_PERMIT[26] != (ENTROPY_SRC_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[27] && reg_we && (ENTROPY_SRC_PERMIT[27] != (ENTROPY_SRC_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[28] && reg_we && (ENTROPY_SRC_PERMIT[28] != (ENTROPY_SRC_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_es_entropy_valid_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_es_entropy_valid_wd = reg_wdata[0];
- assign intr_state_es_rct_failed_we = addr_hit[0] & reg_we & ~wr_err;
- assign intr_state_es_rct_failed_wd = reg_wdata[1];
-
- assign intr_state_es_apt_failed_we = addr_hit[0] & reg_we & ~wr_err;
- assign intr_state_es_apt_failed_wd = reg_wdata[2];
+ assign intr_state_es_health_test_failed_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_es_health_test_failed_wd = reg_wdata[1];
assign intr_state_es_fifo_err_we = addr_hit[0] & reg_we & ~wr_err;
- assign intr_state_es_fifo_err_wd = reg_wdata[3];
+ assign intr_state_es_fifo_err_wd = reg_wdata[2];
assign intr_enable_es_entropy_valid_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_es_entropy_valid_wd = reg_wdata[0];
- assign intr_enable_es_rct_failed_we = addr_hit[1] & reg_we & ~wr_err;
- assign intr_enable_es_rct_failed_wd = reg_wdata[1];
-
- assign intr_enable_es_apt_failed_we = addr_hit[1] & reg_we & ~wr_err;
- assign intr_enable_es_apt_failed_wd = reg_wdata[2];
+ assign intr_enable_es_health_test_failed_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_es_health_test_failed_wd = reg_wdata[1];
assign intr_enable_es_fifo_err_we = addr_hit[1] & reg_we & ~wr_err;
- assign intr_enable_es_fifo_err_wd = reg_wdata[3];
+ assign intr_enable_es_fifo_err_wd = reg_wdata[2];
assign intr_test_es_entropy_valid_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_es_entropy_valid_wd = reg_wdata[0];
- assign intr_test_es_rct_failed_we = addr_hit[2] & reg_we & ~wr_err;
- assign intr_test_es_rct_failed_wd = reg_wdata[1];
-
- assign intr_test_es_apt_failed_we = addr_hit[2] & reg_we & ~wr_err;
- assign intr_test_es_apt_failed_wd = reg_wdata[2];
+ assign intr_test_es_health_test_failed_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_es_health_test_failed_wd = reg_wdata[1];
assign intr_test_es_fifo_err_we = addr_hit[2] & reg_we & ~wr_err;
- assign intr_test_es_fifo_err_wd = reg_wdata[3];
+ assign intr_test_es_fifo_err_wd = reg_wdata[2];
- assign es_regen_we = addr_hit[3] & reg_we & ~wr_err;
- assign es_regen_wd = reg_wdata[0];
+ assign regen_we = addr_hit[3] & reg_we & ~wr_err;
+ assign regen_wd = reg_wdata[0];
- assign es_conf_enable_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_enable_wd = reg_wdata[1:0];
+ assign conf_enable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_enable_wd = reg_wdata[1:0];
- assign es_conf_rng_src_en_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_rng_src_en_wd = reg_wdata[4];
+ assign conf_boot_bypass_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_boot_bypass_disable_wd = reg_wdata[3];
- assign es_conf_rct_en_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_rct_en_wd = reg_wdata[5];
+ assign conf_repcnt_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_repcnt_disable_wd = reg_wdata[4];
- assign es_conf_apt_en_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_apt_en_wd = reg_wdata[6];
+ assign conf_adaptp_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_adaptp_disable_wd = reg_wdata[5];
- assign es_conf_rng_bit_en_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_rng_bit_en_wd = reg_wdata[8];
+ assign conf_bucket_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_bucket_disable_wd = reg_wdata[6];
- assign es_conf_rng_bit_sel_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_rng_bit_sel_wd = reg_wdata[10:9];
+ assign conf_markov_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_markov_disable_wd = reg_wdata[7];
- assign es_rct_health_we = addr_hit[6] & reg_we & ~wr_err;
- assign es_rct_health_wd = reg_wdata[15:0];
+ assign conf_health_test_clr_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_health_test_clr_wd = reg_wdata[8];
- assign es_apt_health_apt_max_we = addr_hit[7] & reg_we & ~wr_err;
- assign es_apt_health_apt_max_wd = reg_wdata[15:0];
+ assign conf_rng_bit_en_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_rng_bit_en_wd = reg_wdata[9];
- assign es_apt_health_apt_win_we = addr_hit[7] & reg_we & ~wr_err;
- assign es_apt_health_apt_win_wd = reg_wdata[31:16];
+ assign conf_rng_bit_sel_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_rng_bit_sel_wd = reg_wdata[11:10];
- assign es_entropy_re = addr_hit[8] && reg_re;
+ assign rate_we = addr_hit[6] & reg_we & ~wr_err;
+ assign rate_wd = reg_wdata[15:0];
- assign es_fifo_status_dig_src_depth_re = addr_hit[9] && reg_re;
+ assign entropy_control_es_route_we = addr_hit[7] & reg_we & ~wr_err;
+ assign entropy_control_es_route_wd = reg_wdata[0];
- assign es_fifo_status_hwif_depth_re = addr_hit[9] && reg_re;
+ assign entropy_control_es_type_we = addr_hit[7] & reg_we & ~wr_err;
+ assign entropy_control_es_type_wd = reg_wdata[1];
- assign es_fifo_status_es_depth_re = addr_hit[9] && reg_re;
+ assign entropy_data_re = addr_hit[8] && reg_re;
- assign es_fifo_status_diag_re = addr_hit[9] && reg_re;
+ assign health_test_windows_fips_window_we = addr_hit[9] & reg_we & ~wr_err;
+ assign health_test_windows_fips_window_wd = reg_wdata[15:0];
- assign es_fdepthst_re = addr_hit[10] && reg_re;
+ assign health_test_windows_bypass_window_we = addr_hit[9] & reg_we & ~wr_err;
+ assign health_test_windows_bypass_window_wd = reg_wdata[31:16];
- assign es_thresh_we = addr_hit[11] & reg_we & ~wr_err;
- assign es_thresh_wd = reg_wdata[2:0];
+ assign repcnt_thresholds_fips_repcnt_thresh_we = addr_hit[10] & reg_we & ~wr_err;
+ assign repcnt_thresholds_fips_repcnt_thresh_wd = reg_wdata[15:0];
- assign es_rate_we = addr_hit[12] & reg_we & ~wr_err;
- assign es_rate_wd = reg_wdata[15:0];
+ assign repcnt_thresholds_bypass_repcnt_thresh_we = addr_hit[10] & reg_we & ~wr_err;
+ assign repcnt_thresholds_bypass_repcnt_thresh_wd = reg_wdata[31:16];
- assign es_seed_we = addr_hit[13] & reg_we & ~wr_err;
- assign es_seed_wd = reg_wdata[3:0];
+ assign adaptp_hi_thresholds_fips_adaptp_hi_thresh_we = addr_hit[11] & reg_we & ~wr_err;
+ assign adaptp_hi_thresholds_fips_adaptp_hi_thresh_wd = reg_wdata[15:0];
+
+ assign adaptp_hi_thresholds_bypass_adaptp_hi_thresh_we = addr_hit[11] & reg_we & ~wr_err;
+ assign adaptp_hi_thresholds_bypass_adaptp_hi_thresh_wd = reg_wdata[31:16];
+
+ assign adaptp_lo_thresholds_fips_adaptp_lo_thresh_we = addr_hit[12] & reg_we & ~wr_err;
+ assign adaptp_lo_thresholds_fips_adaptp_lo_thresh_wd = reg_wdata[15:0];
+
+ assign adaptp_lo_thresholds_bypass_adaptp_lo_thresh_we = addr_hit[12] & reg_we & ~wr_err;
+ assign adaptp_lo_thresholds_bypass_adaptp_lo_thresh_wd = reg_wdata[31:16];
+
+ assign bucket_thresholds_fips_bucket_thresh_we = addr_hit[13] & reg_we & ~wr_err;
+ assign bucket_thresholds_fips_bucket_thresh_wd = reg_wdata[15:0];
+
+ assign bucket_thresholds_bypass_bucket_thresh_we = addr_hit[13] & reg_we & ~wr_err;
+ assign bucket_thresholds_bypass_bucket_thresh_wd = reg_wdata[31:16];
+
+ assign markov_thresholds_fips_markov_thresh_we = addr_hit[14] & reg_we & ~wr_err;
+ assign markov_thresholds_fips_markov_thresh_wd = reg_wdata[15:0];
+
+ assign markov_thresholds_bypass_markov_thresh_we = addr_hit[14] & reg_we & ~wr_err;
+ assign markov_thresholds_bypass_markov_thresh_wd = reg_wdata[31:16];
+
+ assign repcnt_hi_watermarks_fips_repcnt_hi_watermark_re = addr_hit[15] && reg_re;
+
+ assign repcnt_hi_watermarks_bypass_repcnt_hi_watermark_re = addr_hit[15] && reg_re;
+
+ assign adaptp_hi_watermarks_fips_adaptp_hi_watermark_re = addr_hit[16] && reg_re;
+
+ assign adaptp_hi_watermarks_bypass_adaptp_hi_watermark_re = addr_hit[16] && reg_re;
+
+ assign adaptp_lo_watermarks_fips_adaptp_lo_watermark_re = addr_hit[17] && reg_re;
+
+ assign adaptp_lo_watermarks_bypass_adaptp_lo_watermark_re = addr_hit[17] && reg_re;
+
+ assign bucket_hi_watermarks_fips_bucket_hi_watermark_re = addr_hit[18] && reg_re;
+
+ assign bucket_hi_watermarks_bypass_bucket_hi_watermark_re = addr_hit[18] && reg_re;
+
+ assign markov_hi_watermarks_fips_markov_hi_watermark_re = addr_hit[19] && reg_re;
+
+ assign markov_hi_watermarks_bypass_markov_hi_watermark_re = addr_hit[19] && reg_re;
+
+ assign repcnt_total_fails_re = addr_hit[20] && reg_re;
+
+ assign adaptp_hi_total_fails_re = addr_hit[21] && reg_re;
+
+ assign adaptp_lo_total_fails_re = addr_hit[22] && reg_re;
+
+ assign bucket_total_fails_re = addr_hit[23] && reg_re;
+
+ assign markov_total_fails_re = addr_hit[24] && reg_re;
+
+ assign alert_threshold_we = addr_hit[25] & reg_we & ~wr_err;
+ assign alert_threshold_wd = reg_wdata[3:0];
+
+ assign alert_fail_counts_any_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_repcnt_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_adaptp_hi_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_adaptp_lo_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_bucket_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_markov_fail_count_re = addr_hit[26] && reg_re;
+
+ assign debug_status_entropy_fifo_depth_re = addr_hit[27] && reg_re;
+
+ assign debug_status_diag_re = addr_hit[27] && reg_re;
+
+ assign seed_we = addr_hit[28] & reg_we & ~wr_err;
+ assign seed_wd = reg_wdata[3:0];
// Read data return
always_comb begin
@@ -1029,78 +1792,152 @@
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = intr_state_es_entropy_valid_qs;
- reg_rdata_next[1] = intr_state_es_rct_failed_qs;
- reg_rdata_next[2] = intr_state_es_apt_failed_qs;
- reg_rdata_next[3] = intr_state_es_fifo_err_qs;
+ reg_rdata_next[1] = intr_state_es_health_test_failed_qs;
+ reg_rdata_next[2] = intr_state_es_fifo_err_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = intr_enable_es_entropy_valid_qs;
- reg_rdata_next[1] = intr_enable_es_rct_failed_qs;
- reg_rdata_next[2] = intr_enable_es_apt_failed_qs;
- reg_rdata_next[3] = intr_enable_es_fifo_err_qs;
+ reg_rdata_next[1] = intr_enable_es_health_test_failed_qs;
+ reg_rdata_next[2] = intr_enable_es_fifo_err_qs;
end
addr_hit[2]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
reg_rdata_next[2] = '0;
- reg_rdata_next[3] = '0;
end
addr_hit[3]: begin
- reg_rdata_next[0] = es_regen_qs;
+ reg_rdata_next[0] = regen_qs;
end
addr_hit[4]: begin
- reg_rdata_next[7:0] = es_rev_abi_revision_qs;
- reg_rdata_next[15:8] = es_rev_hw_revision_qs;
- reg_rdata_next[23:16] = es_rev_chip_type_qs;
+ reg_rdata_next[7:0] = rev_abi_revision_qs;
+ reg_rdata_next[15:8] = rev_hw_revision_qs;
+ reg_rdata_next[23:16] = rev_chip_type_qs;
end
addr_hit[5]: begin
- reg_rdata_next[1:0] = es_conf_enable_qs;
- reg_rdata_next[4] = es_conf_rng_src_en_qs;
- reg_rdata_next[5] = es_conf_rct_en_qs;
- reg_rdata_next[6] = es_conf_apt_en_qs;
- reg_rdata_next[8] = es_conf_rng_bit_en_qs;
- reg_rdata_next[10:9] = es_conf_rng_bit_sel_qs;
+ reg_rdata_next[1:0] = conf_enable_qs;
+ reg_rdata_next[3] = conf_boot_bypass_disable_qs;
+ reg_rdata_next[4] = conf_repcnt_disable_qs;
+ reg_rdata_next[5] = conf_adaptp_disable_qs;
+ reg_rdata_next[6] = conf_bucket_disable_qs;
+ reg_rdata_next[7] = conf_markov_disable_qs;
+ reg_rdata_next[8] = conf_health_test_clr_qs;
+ reg_rdata_next[9] = conf_rng_bit_en_qs;
+ reg_rdata_next[11:10] = conf_rng_bit_sel_qs;
end
addr_hit[6]: begin
- reg_rdata_next[15:0] = es_rct_health_qs;
+ reg_rdata_next[15:0] = rate_qs;
end
addr_hit[7]: begin
- reg_rdata_next[15:0] = es_apt_health_apt_max_qs;
- reg_rdata_next[31:16] = es_apt_health_apt_win_qs;
+ reg_rdata_next[0] = entropy_control_es_route_qs;
+ reg_rdata_next[1] = entropy_control_es_type_qs;
end
addr_hit[8]: begin
- reg_rdata_next[31:0] = es_entropy_qs;
+ reg_rdata_next[31:0] = entropy_data_qs;
end
addr_hit[9]: begin
- reg_rdata_next[2:0] = es_fifo_status_dig_src_depth_qs;
- reg_rdata_next[6:4] = es_fifo_status_hwif_depth_qs;
- reg_rdata_next[16:12] = es_fifo_status_es_depth_qs;
- reg_rdata_next[31] = es_fifo_status_diag_qs;
+ reg_rdata_next[15:0] = health_test_windows_fips_window_qs;
+ reg_rdata_next[31:16] = health_test_windows_bypass_window_qs;
end
addr_hit[10]: begin
- reg_rdata_next[2:0] = es_fdepthst_qs;
+ reg_rdata_next[15:0] = repcnt_thresholds_fips_repcnt_thresh_qs;
+ reg_rdata_next[31:16] = repcnt_thresholds_bypass_repcnt_thresh_qs;
end
addr_hit[11]: begin
- reg_rdata_next[2:0] = es_thresh_qs;
+ reg_rdata_next[15:0] = adaptp_hi_thresholds_fips_adaptp_hi_thresh_qs;
+ reg_rdata_next[31:16] = adaptp_hi_thresholds_bypass_adaptp_hi_thresh_qs;
end
addr_hit[12]: begin
- reg_rdata_next[15:0] = es_rate_qs;
+ reg_rdata_next[15:0] = adaptp_lo_thresholds_fips_adaptp_lo_thresh_qs;
+ reg_rdata_next[31:16] = adaptp_lo_thresholds_bypass_adaptp_lo_thresh_qs;
end
addr_hit[13]: begin
- reg_rdata_next[3:0] = es_seed_qs;
+ reg_rdata_next[15:0] = bucket_thresholds_fips_bucket_thresh_qs;
+ reg_rdata_next[31:16] = bucket_thresholds_bypass_bucket_thresh_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[15:0] = markov_thresholds_fips_markov_thresh_qs;
+ reg_rdata_next[31:16] = markov_thresholds_bypass_markov_thresh_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[15:0] = repcnt_hi_watermarks_fips_repcnt_hi_watermark_qs;
+ reg_rdata_next[31:16] = repcnt_hi_watermarks_bypass_repcnt_hi_watermark_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[15:0] = adaptp_hi_watermarks_fips_adaptp_hi_watermark_qs;
+ reg_rdata_next[31:16] = adaptp_hi_watermarks_bypass_adaptp_hi_watermark_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[15:0] = adaptp_lo_watermarks_fips_adaptp_lo_watermark_qs;
+ reg_rdata_next[31:16] = adaptp_lo_watermarks_bypass_adaptp_lo_watermark_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[15:0] = bucket_hi_watermarks_fips_bucket_hi_watermark_qs;
+ reg_rdata_next[31:16] = bucket_hi_watermarks_bypass_bucket_hi_watermark_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[15:0] = markov_hi_watermarks_fips_markov_hi_watermark_qs;
+ reg_rdata_next[31:16] = markov_hi_watermarks_bypass_markov_hi_watermark_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[31:0] = repcnt_total_fails_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[31:0] = adaptp_hi_total_fails_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[31:0] = adaptp_lo_total_fails_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[31:0] = bucket_total_fails_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[31:0] = markov_total_fails_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[3:0] = alert_threshold_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[3:0] = alert_fail_counts_any_fail_count_qs;
+ reg_rdata_next[7:4] = alert_fail_counts_repcnt_fail_count_qs;
+ reg_rdata_next[11:8] = alert_fail_counts_adaptp_hi_fail_count_qs;
+ reg_rdata_next[15:12] = alert_fail_counts_adaptp_lo_fail_count_qs;
+ reg_rdata_next[19:16] = alert_fail_counts_bucket_fail_count_qs;
+ reg_rdata_next[23:20] = alert_fail_counts_markov_fail_count_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[1:0] = debug_status_entropy_fifo_depth_qs;
+ reg_rdata_next[31] = debug_status_diag_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[3:0] = seed_qs;
end
default: begin
diff --git a/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv
new file mode 100755
index 0000000..7ace6b7
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv
@@ -0,0 +1,114 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src repetitive count health test module
+//
+
+module entropy_src_repcnt_ht #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned RngBusWidth = 4
+) (
+ input clk_i,
+ input rst_ni,
+
+ // ins req interface
+ input logic [RngBusWidth-1:0] entropy_bit_i,
+ input logic entropy_bit_vld_i,
+ input logic clear_i,
+ input logic active_i,
+ input logic [RegWidth-1:0] thresh_i,
+ input logic [RegWidth-1:0] window_i,
+ output logic [RegWidth-1:0] test_cnt_o,
+ output logic test_done_pulse_o,
+ output logic test_fail_pulse_o
+);
+
+ // signals
+ logic window_cntr_wrap;
+ logic [RngBusWidth-1:0] samples_match_pulse;
+ logic [RngBusWidth-1:0] samples_no_match_pulse;
+ logic [RngBusWidth-1:0] rep_cnt_fail;
+
+ // flops
+ logic [RngBusWidth-1:0] prev_sample_q, prev_sample_d;
+ logic [RegWidth-1:0] rep_cntr_q[RngBusWidth], rep_cntr_d[RngBusWidth];
+ logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
+ logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ prev_sample_q <= '0;
+ rep_cntr_q <= {{RegWidth{1'b0}},{RegWidth{1'b0}},
+ {RegWidth{1'b0}},{RegWidth{1'b0}}};
+ window_cntr_q <= '0;
+ test_cnt_q <= '0;
+ end else begin
+ prev_sample_q <= prev_sample_d;
+ rep_cntr_q <= rep_cntr_d;
+ window_cntr_q <= window_cntr_d;
+ test_cnt_q <= test_cnt_d;
+ end
+
+
+ // Repetitive Count Test
+ //
+ // Test operation
+ // This test will look for catastrophic stuck bit failures. The rep_cntr
+ // uses zero as the starting value, differing from the NIST value of one.
+
+
+ genvar sh;
+ generate
+ for (sh = 0; sh < RngBusWidth; sh = sh+1) begin : gen_cntrs
+
+ // NIST A sample
+ assign prev_sample_d[sh] =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? entropy_bit_i[sh] :
+ prev_sample_q[sh];
+
+ assign samples_match_pulse[sh] = entropy_bit_vld_i &&
+ (prev_sample_q[sh] == entropy_bit_i[sh]);
+ assign samples_no_match_pulse[sh] = entropy_bit_vld_i &&
+ (prev_sample_q[sh] != entropy_bit_i[sh]);
+
+ // NIST B counter
+ assign rep_cntr_d[sh] =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ samples_match_pulse[sh] ? (rep_cntr_q[sh]+1) :
+ samples_no_match_pulse[sh] ? '0 :
+ rep_cntr_q[sh];
+
+ assign rep_cnt_fail[sh] = (rep_cntr_q[sh] >= thresh_i);
+
+ end
+ endgenerate
+
+
+ // Window wrap condition
+ assign window_cntr_wrap = (window_cntr_q == window_i);
+
+ // Window counter
+ assign window_cntr_d =
+ clear_i ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (window_cntr_q+1) :
+ window_cntr_q;
+
+ // Test event counter
+ assign test_cnt_d =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i && (|rep_cnt_fail) ? (test_cnt_q+1) :
+ test_cnt_q;
+
+ // the pulses will be only one clock in length
+ assign test_fail_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > '0);
+ assign test_done_pulse_o = window_cntr_wrap;
+ assign test_cnt_o = test_cnt_q;
+
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_shtests.sv b/hw/ip/entropy_src/rtl/entropy_src_shtests.sv
deleted file mode 100755
index 7c3cd0e..0000000
--- a/hw/ip/entropy_src/rtl/entropy_src_shtests.sv
+++ /dev/null
@@ -1,138 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: entropy_src health tests module
-//
-
-module entropy_src_shtests (
- input clk_i,
- input rst_ni,
-
- // ins req interface
- input logic entropy_bit_i,
- input logic entropy_bit_vld_i,
- input logic rct_active_i,
- input logic [15:0] rct_max_cnt_i,
- input logic apt_active_i,
- input logic [15:0] apt_max_cnt_i,
- input logic [15:0] apt_window_i,
- output logic rct_fail_pls_o,
- output logic apt_fail_pls_o,
- output logic shtests_passing_o
-);
-
- // signals
- logic rct_samples_match;
- logic rct_fail;
- logic rct_pass;
- logic apt_reset_test;
- logic apt_samples_match;
- logic apt_fail;
- logic apt_pass;
-
-
- // flops
- logic rct_prev_sample_q, rct_prev_sample_d;
- logic [15:0] rct_rep_cntr_q, rct_rep_cntr_d;
- logic apt_initial_sample_q, apt_initial_sample_d;
- logic [15:0] apt_sample_cntr_q, apt_sample_cntr_d;
- logic [15:0] apt_match_cntr_q, apt_match_cntr_d;
- logic rct_passing_q, rct_passing_d;
- logic apt_passing_q, apt_passing_d;
-
- always_ff @(posedge clk_i or negedge rst_ni)
- if (!rst_ni) begin
- rct_prev_sample_q <= '0;
- rct_rep_cntr_q <= '0;
- apt_initial_sample_q <= '0;
- apt_sample_cntr_q <= '0;
- apt_match_cntr_q <= '0;
- rct_passing_q <= '0;
- apt_passing_q <= '0;
- end else begin
- rct_prev_sample_q <= rct_prev_sample_d;
- rct_rep_cntr_q <= rct_rep_cntr_d;
- apt_initial_sample_q <= apt_initial_sample_d;
- apt_sample_cntr_q <= apt_sample_cntr_d;
- apt_match_cntr_q <= apt_match_cntr_d;
- rct_passing_q <= rct_passing_d;
- apt_passing_q <= apt_passing_d;
- end
-
-
-
- // Repetition Count Test (RCT)
- //
- // Point of test
- // check for back to back patterns up to a
- // limit, fail if it does
-
-
- // NIST A sample
- assign rct_prev_sample_d = ~rct_active_i ? 1'b0 :
- (entropy_bit_vld_i & (rct_rep_cntr_q == 16'h0001)) ? entropy_bit_i :
- rct_prev_sample_q;
-
- assign rct_samples_match = (rct_prev_sample_q == (entropy_bit_vld_i & entropy_bit_i));
-
- // NIST B counter
- assign rct_rep_cntr_d =
- ~rct_active_i ? 16'h0001 :
- rct_fail ? 16'h0001 :
- (entropy_bit_vld_i & rct_samples_match) ? (rct_rep_cntr_q+1) :
- rct_pass ? 16'h0001 :
- rct_rep_cntr_q;
-
- assign rct_pass = rct_active_i & (entropy_bit_vld_i & ~rct_samples_match);
- assign rct_fail = rct_active_i & (rct_rep_cntr_q >= rct_max_cnt_i);
- assign rct_fail_pls_o = rct_fail;
-
- assign rct_passing_d =
- ~rct_active_i ? 1'b1 :
- rct_fail ? 1'b0 :
- rct_pass ? 1'b1 :
- rct_passing_q;
-
-
- // Adaptive Proportion Test (APT)
- //
- // Point of test
- // sample once, then check for period of time if
- // that pattern appears again, fail if it does
-
-
- // NIST N value
- assign apt_reset_test = ~apt_active_i | apt_fail | (apt_sample_cntr_q >= apt_window_i);
-
- // NIST A counter
- assign apt_initial_sample_d =
- ((apt_sample_cntr_q == 16'h0000) & entropy_bit_vld_i) ? entropy_bit_i :
- apt_initial_sample_q;
-
- // NIST S counter
- assign apt_sample_cntr_d = apt_reset_test ? 16'b0 :
- entropy_bit_vld_i ? (apt_sample_cntr_q+1) :
- apt_sample_cntr_q;
-
- assign apt_samples_match = entropy_bit_vld_i & (apt_initial_sample_q == entropy_bit_i);
-
- // NIST B counter
- assign apt_match_cntr_d = apt_reset_test ? 16'b0 :
- (entropy_bit_vld_i & apt_samples_match) ? (apt_match_cntr_q+1) :
- apt_match_cntr_q;
-
- assign apt_pass = (apt_sample_cntr_q >= apt_window_i);
- assign apt_fail = apt_active_i & (apt_match_cntr_q >= apt_max_cnt_i);
- assign apt_fail_pls_o = apt_fail;
-
- assign apt_passing_d =
- ~apt_active_i ? 1'b1 :
- apt_fail ? 1'b0 :
- apt_pass ? 1'b1 :
- apt_passing_q;
-
- // tests summary
- assign shtests_passing_o = rct_passing_q && apt_passing_q;
-
-endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv b/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv
new file mode 100755
index 0000000..577e5d7
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv
@@ -0,0 +1,55 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src high or how watermark register module
+//
+
+module entropy_src_watermark_reg #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned HighWatermark = 1
+) (
+ input logic clk_i,
+ input logic rst_ni,
+
+ // functional interface
+ input logic clear_i,
+ input logic active_i,
+ input logic event_i,
+ input logic [RegWidth-1:0] value_i,
+ output logic [RegWidth-1:0] value_o
+);
+
+ // signals
+ logic [RegWidth-1:0] event_cntr_change;
+
+ // flops
+ logic [RegWidth-1:0] event_cntr_q, event_cntr_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ event_cntr_q <= '0;
+ end else begin
+ event_cntr_q <= event_cntr_d;
+ end
+
+ assign event_cntr_d = (!active_i || clear_i) ? '0 :
+ event_i ? event_cntr_change :
+ event_cntr_q;
+
+ generate
+ if (HighWatermark) begin : gen_hi_wm
+
+ assign event_cntr_change = (value_i > event_cntr_q) ? (value_i) : event_cntr_q;
+
+ end else begin : gen_lo_wm
+
+ assign event_cntr_change = (value_i < event_cntr_q) ? (value_i) : event_cntr_q;
+
+ end
+ endgenerate
+
+ // drive output
+ assign value_o = event_cntr_q;
+
+endmodule
