[entropy_src/rtl] review round2 changes
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/entropy_src/data/entropy_src.hjson b/hw/ip/entropy_src/data/entropy_src.hjson
index cb16588..acc6049 100755
--- a/hw/ip/entropy_src/data/entropy_src.hjson
+++ b/hw/ip/entropy_src/data/entropy_src.hjson
@@ -16,10 +16,8 @@
interrupt_list: [
{ name: "es_entropy_valid"
desc: "Asserted when entropy source bits are available."}
- { name: "es_rct_failed"
- desc: "Asserted when the repetitive count test fails."}
- { name: "es_apt_failed"
- desc: "Asserted when the adaptive proportion test fails."}
+ { name: "es_health_test_failed"
+ desc: "Asserted when the alert count has been met."}
{ name: "es_fifo_err"
desc: "Asserted when a FIFO error occurs."}
],
@@ -49,26 +47,32 @@
package: "entropy_src_pkg",
}
],
+ alert_list: [
+ { name: "es_alert_count_met",
+ desc: '''This alert is triggered upon the alert count being met.
+ '''
+ }
+ ],
regwidth: "32",
registers: [
- { name: "ES_REGEN",
+ { name: "REGEN",
desc: "Register write enable for all control registers",
swaccess: "rw1c",
hwaccess: "hro",
fields: [
{
- bits: "0",
- desc: ''' When true, the ES_CONF, ES_RCT_HEALTH, ES_APT_HEALTH and ES_SEED registers can be modified.
+ bits: "0",
+ desc: ''' When true, all writeable registers can be modified.
When false, they become read-only. Defaults true, write one to clear. Note that this needs to be
cleared after initial configuration at boot in order to lock in the listed register settings.
'''
resval: 1
- },
+ }
]
},
- { name: "ES_REV",
- desc: "ENTROPY_SRC revision register",
+ { name: "REV",
+ desc: "Revision register",
swaccess: "ro",
hwaccess: "none",
fields: [
@@ -80,51 +84,62 @@
{ bits: "15:8",
name: "HW_REVISION",
desc: "Read of this register shows the revision of this block.",
- resval: "0x1"
- }
+ resval: "0x3"
+ }
{ bits: "7:0",
name: "ABI_REVISION",
desc: "Read of this register shows the ABI of this block.",
- resval: "0x1"
+ resval: "0x3"
}
]
},
- { name: "ES_CONF",
- desc: "ENTROPY_SRC configuration register",
+ { name: "CONF",
+ desc: "Configuration register",
swaccess: "rw",
hwaccess: "hro",
- regwen: "ES_REGEN",
+ regwen: "REGEN",
fields: [
{ bits: "1:0",
name: "ENABLE",
- desc: '''Primary enable for the ENTROPY_SRC entropy generation function.
- This two bit field determines what source will be used for health
- check processing:
+ desc: '''This field is the module enable for the ENTROPY_SRC entropy generation function.
+ This two bit field determines what source will be used for all processing:
0b00: Disabled
- 0b01: LFSR mode enabled
- 0b10: RNG mode enabled
+ 0b01: PTRNG mode enabled
+ 0b10: LFSR mode enabled
0b11: Reserved
'''
tags: [// Exclude from writes to these bits to avoid Xs from entropy FIFO.
"excl:CsrAllTests:CsrExclWrite"]
}
+ { bits: "3",
+ name: "BOOT_BYPASS_DISABLE",
+ desc: "Setting this bit disables the initial generation of non-FIPS entropy."
+ }
{ bits: "4",
- name: "RNG_SRC_EN",
- desc: "Setting this bit enables the RNG entropy source."
+ name: "REPCNT_DISABLE",
+ desc: "Setting this bit disables the health test called Repetition Count test."
}
{ bits: "5",
- name: "RCT_EN",
- desc: "Setting this bit enables the health test called Repetition Count Test."
+ name: "ADAPTP_DISABLE",
+ desc: "Setting this bit disables the health test called Adaptive Proportion test."
}
{ bits: "6",
- name: "APT_EN",
- desc: "Setting this bit enables the health test called Adaptive Proportion Test."
+ name: "BUCKET_DISABLE",
+ desc: "Setting this bit disables the health test called Bucket test."
+ }
+ { bits: "7",
+ name: "MARKOV_DISABLE",
+ desc: "Setting this bit disables the health test called Markov test."
}
{ bits: "8",
+ name: "HEALTH_TEST_CLR",
+ desc: "Setting this bit will clear all registers related to the health test operations."
+ }
+ { bits: "9",
name: "RNG_BIT_EN",
desc: "Setting this bit enables the single RNG bit mode, where only one bit is sampled."
}
- { bits: "10:9",
+ { bits: "11:10",
name: "RNG_BIT_SEL",
desc: '''When the above bit iset, this field selects which bit from the RNG bus will
be processed when in single RNG bit mode.
@@ -137,66 +152,446 @@
}
]
},
- { name: "ES_RCT_HEALTH",
- desc: "ENTROPY_SRC RCT health test register",
+ { name: "RATE",
+ desc: "Entropy rate register",
swaccess: "rw",
- hwaccess: "hro",
- regwen: "ES_REGEN",
fields: [
{ bits: "15:0",
- name: "RCT_MAX",
- desc: "This is the cutoff value for failures of the RCT health test."
- resval: "0x0b"
+ name: "ENTROPY_RATE",
+ desc: '''This register determines the rate that entropy bits will be supplied.
+ In LFSR mode, this is the rate that the LFSR value will be advanced.
+ In PTRNG mode, this is the rate that the raw entropy source will be sampled at.
+ The default rate is 50 KHz, or 4 physcial bits per 20 micro-seconds.
+ '''
+ resval: "0x000007d0"
}
]
},
- { name: "ES_APT_HEALTH",
- desc: "ENTROPY_SRC APT health test register",
+ { name: "ENTROPY_CONTROL",
+ desc: "Entropy control register",
swaccess: "rw",
hwaccess: "hro",
- regwen: "ES_REGEN",
+ regwen: "REGEN",
fields: [
- { bits: "15:0",
- name: "APT_MAX",
- desc: "This is the cutoff value for failures of the APT health test."
- resval: "0x0298"
+ { bits: "0",
+ name: "ES_ROUTE",
+ desc: '''Setting this bit routes the generated entropy value to the ENTROPY_DATA
+ register to be read by firmware. When this bit is zero, the generated
+ entropy will be forwarded out of this module to the hardware interface.
+ '''
}
- { bits: "31:16",
- name: "APT_WIN",
- desc: "This is the window value for testing of the APT health test."
- resval: "0x0400"
+ { bits: "1",
+ name: "ES_TYPE",
+ desc: '''Setting this bit will bypass the conditioning logic and bring raw entropy
+ data to the ENTROPY_DATA register. When zero, FIPS compliant entropy
+ will be brought the ENTROPY_DATA register, after being conditioned.
+ '''
}
]
},
- { name: "ES_ENTROPY",
- desc: "ENTROPY_SRC entropy source",
+ { name: "ENTROPY_DATA",
+ desc: "Entropy data bits",
swaccess: "ro",
hwaccess: "hrw",
hwext: "true",
hwre: "true",
fields: [
{ bits: "31:0",
- desc: "A read of this register provides entropy needed for an entropy source."
+ desc: "A read of this register provides generated entropy bits to firmware."
+
}
]
},
- { name: "ES_FIFO_STATUS",
- desc: "ENTROPY_SRC fifo depth status register",
+ { name: "HEALTH_TEST_WINDOWS",
+ desc: "Health test windows register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_WINDOW",
+ desc: '''This is the window size for all health tests. This is value used in normal mode
+ when entropy is being tested in FIPS/CC compliance mode.
+ The default value is (1024 bits * 1 clock/4 bits);
+ '''
+ resval: "0x0100"
+ }
+ { bits: "31:16",
+ name: "BYPASS_WINDOW",
+ desc: '''This is the window size for all health tests when running is bypass mode. This mode
+ is active after reset for the first and only test run, or when this mode is
+ programmed by firmware.
+ The default value is (384 bits * 1 clock/4 bits);
+ '''
+ resval: "0x0060"
+ }
+ ]
+ },
+ { name: "REPCNT_THRESHOLDS",
+ desc: "Repetition count test thresholds register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_REPCNT_THRESH",
+ desc: '''This is the threshold size for the repetition count health test.
+ This is value used in normal mode when entropy is being tested in
+ FIPS/CC compliance mode.
+ The default value is 32
+ '''
+ resval: "0x0020"
+ }
+ { bits: "31:16",
+ name: "BYPASS_REPCNT_THRESH",
+ desc: '''This is the threshold size for the repetition count health test
+ running is bypass mode. This mode is active after reset for the
+ first and only test run, or when this mode is programmed by firmware.
+ The default value is 32
+ '''
+ resval: "0x0020"
+ }
+ ]
+ },
+ { name: "ADAPTP_HI_THRESHOLDS",
+ desc: "Adaptive proportion test high thresholds register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_ADAPTP_HI_THRESH",
+ desc: '''This is the threshold size for the adaptive proportion health test.
+ This is value used in normal mode when entropy is being tested in
+ FIPS/CC compliance mode.
+ The default value is 598.
+ '''
+ resval: "0x0256"
+ }
+ { bits: "31:16",
+ name: "BYPASS_ADAPTP_HI_THRESH",
+ desc: '''This is the threshold size for the adaptive proportion health test
+ running is bypass mode. This mode is active after reset for the
+ first and only test run, or when this mode is programmed by firmware.
+ The default value is .375 of the FIPS threshold.
+ '''
+ resval: "0x00e0"
+ }
+ ]
+ },
+ { name: "ADAPTP_LO_THRESHOLDS",
+ desc: "Adaptive proportion test low thresholds register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_ADAPTP_LO_THRESH",
+ desc: '''This is the threshold size for the adaptive proportion health test.
+ This is value used in normal mode when entropy is being tested in
+ FIPS/CC compliance mode.
+ The default value is 426.
+ '''
+ resval: "0x01aa"
+ }
+ { bits: "31:16",
+ name: "BYPASS_ADAPTP_LO_THRESH",
+ desc: '''This is the threshold size for the adaptive proportion health test
+ running is bypass mode. This mode is active after reset for the
+ first and only test run, or when this mode is programmed by firmware.
+ The default value is .375 of the FIPS threshold.
+ '''
+ resval: "0x00a0"
+ }
+ ]
+ },
+ { name: "BUCKET_THRESHOLDS",
+ desc: "Bucket test thresholds register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_BUCKET_THRESH",
+ desc: '''This is the threshold size for the bucket health test.
+ This is value used in normal mode when entropy is being tested in
+ FIPS/CC compliance mode.
+ The default value is 32.
+ '''
+ resval: "0x0020"
+ }
+ { bits: "31:16",
+ name: "BYPASS_BUCKET_THRESH",
+ desc: '''This is the threshold size for the bucket health test
+ running is bypass mode. This mode is active after reset for the
+ first and only test run, or when this mode is programmed by firmware.
+ The default value is 32.
+ '''
+ resval: "0x0020"
+ }
+ ]
+ },
+ { name: "MARKOV_THRESHOLDS",
+ desc: "Markov test thresholds register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_MARKOV_THRESH",
+ desc: '''This is the threshold size for the Markov health test.
+ This is value used in normal mode when entropy is being tested in
+ FIPS/CC compliance mode.
+ The default value is 256.
+ '''
+ resval: "0x0100"
+ }
+ { bits: "31:16",
+ name: "BYPASS_MARKOV_THRESH",
+ desc: '''This is the threshold size for the Markov health test
+ running is bypass mode. This mode is active after reset for the
+ first and only test run, or when this mode is programmed by firmware.
+ The default value is .375 of the FIPS threshold.
+ '''
+ resval: "0x0060"
+ }
+ ]
+ },
+ { name: "REPCNT_HI_WATERMARKS",
+ desc: "Repetition count test high watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
fields: [
- { bits: "2:0",
- name: "DIG_SRC_DEPTH",
- desc: "This is the depth of the digital source FIFO."
+ { bits: "15:0",
+ name: "FIPS_REPCNT_HI_WATERMARK",
+ desc: "High watermark value of the REPCNT test in FIPS mode."
}
- { bits: "6:4",
- name: "HWIF_DEPTH",
- desc: "This is the depth of the hardware interface FIFO."
+ { bits: "31:16",
+ name: "BYPASS_REPCNT_HI_WATERMARK",
+ desc: "High watermark value of the REPCNT test in bypass mode."
}
- { bits: "16:12",
- name: "ES_DEPTH",
- desc: "This is the depth of the ES FIFO."
+ ]
+ },
+ { name: "ADAPTP_HI_WATERMARKS",
+ desc: "Adaptive proportion test high watermarks register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_ADAPTP_HI_WATERMARK",
+ desc: "High watermark value of the adaptive proportion test in FIPS mode."
+ }
+ { bits: "31:16",
+ name: "BYPASS_ADAPTP_HI_WATERMARK",
+ desc: "High watermark value of the adaptive proportion test in bypass mode."
+ }
+ ]
+ },
+ { name: "ADAPTP_LO_WATERMARKS",
+ desc: "Adaptive proportion test low watermarks register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_ADAPTP_LO_WATERMARK",
+ desc: "Low watermark value of the adaptive proportion test in FIPS mode."
+ }
+ { bits: "31:16",
+ name: "BYPASS_ADAPTP_LO_WATERMARK",
+ desc: "Low watermark value of the adaptive proportion test in bypass mode."
+ }
+ ]
+ },
+ { name: "BUCKET_HI_WATERMARKS",
+ desc: "Bucket test high watermarks register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_BUCKET_HI_WATERMARK",
+ desc: "High watermark value of the bucket test in FIPS mode."
+ }
+ { bits: "31:16",
+ name: "BYPASS_BUCKET_HI_WATERMARK",
+ desc: "High watermark value of the bucket test in bypass mode."
+ }
+ ]
+ },
+ { name: "MARKOV_HI_WATERMARKS",
+ desc: "Markov test high watermarks register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_MARKOV_HI_WATERMARK",
+ desc: "High watermark value of the Markov test in FIPS mode."
+ }
+ { bits: "31:16",
+ name: "BYPASS_MARKOV_HI_WATERMARK",
+ desc: "High watermark value of the Markov test in bypass mode."
+ }
+ ]
+ },
+ { name: "REPCNT_TOTAL_FAILS",
+ desc: "Repetition count test failure counter register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ name: "REPCNT_TOTAL_FAILS",
+ desc: '''This register will hold a running count of test failures observed
+ during normal operation. It will persist until cleared.
+ '''
+ }
+ ]
+ },
+ { name: "ADAPTP_HI_TOTAL_FAILS",
+ desc: "Adaptive proportion high test failure counter register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ name: "ADAPTP_HI_TOTAL_FAILS",
+ desc: '''This register will hold a running count of test failures observed
+ during normal operation. It will persist until cleared.
+ '''
+ }
+ ]
+ },
+ { name: "ADAPTP_LO_TOTAL_FAILS",
+ desc: "Adaptive proportion low test failure counter register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ name: "ADAPTP_LO_TOTAL_FAILS",
+ desc: '''This register will hold a running count of test failures observed
+ during normal operation. It will persist until cleared.
+ '''
+ }
+ ]
+ },
+ { name: "BUCKET_TOTAL_FAILS",
+ desc: "Bucket test failure counter register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ name: "BUCKET_TOTAL_FAILS",
+ desc: '''This register will hold a running count of test failures observed
+ during normal operation. It will persist until cleared.
+ '''
+ }
+ ]
+ },
+ { name: "MARKOV_TOTAL_FAILS",
+ desc: "Markov test failure counter register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ name: "MARKOV_TOTAL_FAILS",
+ desc: '''This register will hold a running count of test failures observed
+ during normal operation. It will persist until cleared.
+ '''
+ }
+ ]
+ },
+ { name: "ALERT_THRESHOLD",
+ desc: "Alert threshold register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "3:0",
+ name: "ALERT_THRESHOLD",
+ desc: '''This is the threshold size that will signal an alert when
+ value is reached. A value of zero will disable alerts.
+ The default value is 2.
+ '''
+ resval: "0x0002"
+ }
+ ]
+ },
+ { name: "ALERT_FAIL_COUNTS",
+ desc: "Alert failure counts register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "3:0",
+ name: "ANY_FAIL_COUNT",
+ desc: '''This field will hold a running count of
+ the total alert count, which is a sum of all of the other
+ counters in this register. It is intended to only hold
+ a maximum count of 16 fails, even though the addition of
+ all possible fails will easily overflow this field.
+ It will be reset after every
+ passing test sequence. If an alert is signaled, this value
+ will persist until it is cleared.
+ '''
+ }
+ { bits: "7:4",
+ name: "REPCNT_FAIL_COUNT",
+ desc: '''This field will hold a running count of test failures that
+ contribute to the total alert count. It will be reset after every
+ passing test sequence. If an alert is signaled, this value
+ will persist until it is cleared.
+ '''
+ }
+ { bits: "11:8",
+ name: "ADAPTP_HI_FAIL_COUNT",
+ desc: '''This field will hold a running count of test failures that
+ contribute to the total alert count. It will be reset after every
+ passing test sequence. If an alert is signaled, this value
+ will persist until it is cleared.
+ '''
+ }
+ { bits: "15:12",
+ name: "ADAPTP_LO_FAIL_COUNT",
+ desc: '''This field will hold a running count of test failures that
+ contribute to the total alert count. It will be reset after every
+ passing test sequence. If an alert is signaled, this value
+ will persist until it is cleared.
+ '''
+ }
+ { bits: "19:16",
+ name: "BUCKET_FAIL_COUNT",
+ desc: '''This field will hold a running count of test failures that
+ contribute to the total alert count. It will be reset after every
+ passing test sequence. If an alert is signaled, this value
+ will persist until it is cleared.
+ '''
+ }
+ { bits: "23:20",
+ name: "MARKOV_FAIL_COUNT",
+ desc: '''This field will hold a running count of test failures that
+ contribute to the total alert count. It will be reset after every
+ passing test sequence. If an alert is signaled, this value
+ will persist until it is cleared.
+ '''
+ }
+ ]
+ },
+ { name: "DEBUG_STATUS",
+ desc: "Debug status register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "1:0",
+ name: "ENTROPY_FIFO_DEPTH",
+ desc: "This is the depth of the entropy source FIFO."
}
{ bits: "31",
name: "DIAG",
@@ -204,55 +599,17 @@
}
]
},
- { name: "ES_FDEPTHST",
- desc: "ENTROPY_SRC FIFO depth status register",
- swaccess: "ro",
- hwaccess: "hwo",
- hwext: "true",
- fields: [
- { bits: "2:0",
- name: "ENTROPY_FIFO_DEPTH",
- desc: "This register will reflect the current depth of the software entropy delivery or TLUL FIFO."
- }
- ]
- },
- { name: "ES_THRESH",
- desc: "ENTROPY_SRC threshold register",
- swaccess: "rw",
- fields: [
- { bits: "2:0",
- name: "FIFO_THRESHOLD",
- desc: "The entropy FIFO depth will be compared against this register value when setting the es_entropy_valid interrupt signal."
- }
- ]
- }
- { name: "ES_RATE",
- desc: "ENTROPY_SRC entropy rate register",
- swaccess: "rw",
- fields: [
- { bits: "15:0",
- name: "ENTROPY_RATE",
- desc: '''This register determines the rate that entropy bits will be supplied. Its purpose to is simulate slow entropy sources.
- A value of 1 will deliver full rate entropy. A value of 2 will cut a full entropy source in half. A value of 8 will cut
- the rate by 1/8th. The precise equation for entropy delivery is one clock cycle of entropy is generated
- every 1/(ENTROPY_RATE) equal to one. A value of 0 disables all entropy generation.
- '''
- resval: "0x00000004"
- }
- ]
- }
- { name: "ES_SEED",
+ { name: "SEED",
desc: "ENTROPY_SRC seed register",
swaccess: "rw",
- regwen: "ES_REGEN",
+ regwen: "REGEN",
fields: [
{ bits: "3:0",
name: "LFSR_SEED",
- desc: "Seed used to load into the LFSR for the initial state. This field will not update if the ES_REGEN bit 0 is cleared.",
+ desc: "Seed used to load into the LFSR for the initial state. This field will not update if the REGEN bit 0 is cleared.",
resval: "0xb"
}
]
- }
+ },
]
}
-
diff --git a/hw/ip/entropy_src/doc/_index.md b/hw/ip/entropy_src/doc/_index.md
index b71142a..0167d4c 100755
--- a/hw/ip/entropy_src/doc/_index.md
+++ b/hw/ip/entropy_src/doc/_index.md
@@ -10,83 +10,149 @@
## Features
-- This revision supports a LFSR (linear feedback shift register) digital source, and provides an interface to an external rng (random noise generator) source.
-The LFSR is used as a digital, pseudo-random type of entropy source, while the rng external source is a true entropy source.
-A noise source and its relation to an entropy source are defined by [SP 800-90B](https://csrc.nist.gov/publications/detail/sp/800-90b/final).
-- A set of registers is provided for firmware to manage and obtain entropy bits.
-- The set of registers is designed such that firmware can select between a digital or an rng entropy source.
+
+- This revision provides an interface to an external physical random noise generator (also referred to as a physical true random number generator or PTRNG) source, and an LFSR (linear feedback shift register) digital source.
+The LFSR is used as a digital, pseudo-random type of entropy source, while the PTRNG external source is a physical true random noise source.
+A noise source and its relation to an entropy source are defined by [SP 800-90B.](https://csrc.nist.gov/publications/detail/sp/800-90b/final)
+- A set of registers is provided for firmware to obtain entropy bits.
+- The set of registers is designed such that firmware can select between an LFSR or a PTRNG noise source.
- Interrupts are supported:
- Entropy bits are available for firmware consumption.
- - The external rng entropy source is available.
- - The internal health tests have detected a repetitive count test fail.
- - The internal health tests have detected an adaptive proportion test fail.
+ - The internal health tests have detected a test failure.
- An internal FIFO error has occurred.
-- Two health checks that are defined by SP 800-90B are performed by this revision: Repetition Count and Adaptive Proportion tests.
-- No alerts are supported by this revision.
-
+- Two health checks that are defined by SP 800-90B are performed by this revision: Repetition Count and Adaptive Proportion tests.
+- Two additional hardware health checks are performed by this revision: Bucket and Markov tests.
+- Firmware-defined (mailbox-based) and vendor-defined health checks are also supported.
+- A health check failure alert is supported by this revision.
## Description
-This IP block provides an entropy source that is part of a larger solution to generate true random numbers (a TRNG mechanism).
-The general solution for TRNG relies on either hardware or firmware to implement this function, depending which functions are enabled by firmware or e-fuses.
-For purposes of reference in this document, the NIST term "noise" will be synonymous with the term "entropy".
-Likewise, no conditioning function will be performed in this block.
-For the generation of entropy, this block provides the entropy bits needed for the entropy source solution as required by the RNG mechanism.
+This IP block provides an entropy source that is capable of using a PTRNG noise source to generate random values in a manner that is compliant both with FIPS (though NIST SP 800-90B) and CC (AIS31) recommendations.
-At a high-level, this ENTROPY_SRC block, when enabled, will continuously collect entropy bits from the entropy source into a FIFO that can be read from the TLUL bus, or sent out through a hardware interface.
-The rng source will generate a relative slow set of bit streams, in the tens of kilohertz range.
-The digital source can be programmed to be faster, or much slower if desired.
-A digital source rate of flexiable speed might be useful in demonstrating how the downstream applications use the entropy.
+<!-- URLS for the following pages not upstream yet, but coming -->
+The random values generated by this block serve as non-deterministic seeds for the CSRNG block.
+The outputs of the CSRNG are then used either directly by firmware or are distributed to other hardware blocks through the Entropy Distribution Network.
-Once the threshold has been reached for collected entropy bits, the firmware has two options of notification: an interrupt, or polling.
-The `es_entropy_valid` bit will be set when the {{< regref "ES_THRESH" >}} register value is equal or less than the number of elements in the TLUL FIFO.
-Optionally, an interrupt may be a better use of CPU cycles.
+In the terms of AIS31 classes, this block is meant to satisfy the requirements for a PTG.2 class physical entropy source, with "internal" entropy (an AIS31 term, meaning the min-entropy as measured just *before the output pins*) exceeding 0.997 entropy-bits/output-bit.
+In NIST terms, this block satisfies the requirements for a "full-entropy" source, which requires even smaller deviations from ideal entropy, at the level of less than one part in 2<sup>64</sup>.
+When operating in full-compliance mode, raw outputs from a PTRNG noise source (external to this block) are passed through a conditioning function based on a suitable secure hash function (SHA-2 or SHA-3) which has been vetted by NIST to meet these stringent requirements.
+
+These raw noise bits are subjected to a sequence of health-checks to screen the raw signals for statistical defects which would cause any significant deviations from ideal entropy at the output of the conditioning block.
+These tests include:
+- The Repetition Count test, which screens for stuck-bits, or a complete failure of the PTRNG noise source,
+- The Adaptive Proportion test, which screens for statistical bias in the number of 1's or 0's output by the noise source,
+- The "Bucket Test", which looks for correlations between the individual noise channels that the external noise source concatenates together to produce the raw noise sequence,
+- The "Markov Test", which looks for unexpected first-order temporal correlations between bits output by the individual noise channels,
+- The "Mailbox Test", in which raw-noise data is transferred to firmware in contiguous 2kbit-blocks, so that firmware can perform custom tests, and signal a failure through the same path as the other tests, and
+- Optional Vendor Specific tests, which allow silicon creators to extend the health checks by adding a top-level block external to this IP.
+
+The Repetition Count and Adaptive Proportion test are specifically recommended by SP 800-90B, and are implemented in accordance with those recommendations.
+In FIPS/CC-compliance mode, all checks except the Repetition Count test are performed on fixed window of data, typically consisting of 1024 bits each.
+Per the definition in SP 800-90B, the Repetition Count test does not operate on a fixed window.
+The repetition count test fails if any sequence of bits continuously asserts the same value for too many samples, as determined by the programmable threshold, regardless of whether that sequence crosses any window boundaries.
+The thresholds for these tests should be chosen to achieve a low false-positive rate (α) given a conservative estimate of the manufacturing tolerances of the PTRNG noise source.
+The combined choice of threshold and window size then determine the false-negative rate (β), or the probability of missing statistical defects at any particular magnitude.
+
+When the IP is disabled by clearing the `ENABLE` bit in {{< regref "CONF" >}}, all heath checks are disabled and all counters internal to the health checks are reset.
+
+In order to compensate for the fact our tests (like *all* realistic statistical tests) have finite resolution for detecting defects, we conservatively use 1024 bits of PTRNG noise source to construct each 384 bit conditioned entropy sample.
+When passed through the conditioning block, the resultant entropy stream will be full entropy unless the PTRNG noise source has encountered some statistical defect serious enough to reduce the raw min-entropy to a level below 0.375 bits of entropy per output bit.
+We choose this level as our definition of "non-tolerable statistical defects" for the purposes of evaluating this system under AIS31.
+Given this definition of "non-tolerable defects", the health-checks as implemented for this block will almost certainly detect any of the previously mentioned defects in a single iteration of the health checks (i.e. such serious defects will be detected with very low β).
+
+In addition to the brief, low-latency health checks, various long-term statistics are accumulated in registers for additional diagnostic purposes or for in-depth analysis.
For the hardware interface, entropy bits will be transferred whenever the downstream consumer is ready to receive them.
+At a high-level, this ENTROPY_SRC block, when enabled, will continuously collect entropy bits from the entropy source into a FIFO that can be read from the TL-UL bus, or sent out through a hardware interface.
+The PTRNG noise source will generate a relatively slow set of bit streams, with a total bit rate on the order of 50 kbps.
+The digital source can be programmed to be faster, or much slower if desired.
+A digital source rate of flexible speed might be useful in demonstrating how the downstream applications use the entropy.
+
+Once a noise source has been selected through configuration, the raw noise data processing begins.
+This ENTROPY_SRC block will do health checks, collect and pack bits, and finally send them through a conditioning unit.
+There are two modes in which entropy bits are delivered, boot-time and FIPS/CC mode.
+Boot-time mode will deliver bits sooner for specific on-boot obfuscation applications, though the bits may not yet have been subjected to the same level of startup health checks required for FIPS or CC compliance.
+
+In boot-time mode health checks only operate on a window of 384 bits.
+The boot-time health checks are the same as the FIPS/CC health-checks, though with different thresholds.
+They are sensitive to the same types of statistical defects, though at reduced statistical resolution.
+With suitable thresholds, the boot-time health checks can be operate both with low false-alarm rates (low α), while still confirming with low β that the total entropy of the first seed contains at least 80 bits of total entropy.
+During start up the initial 384 bits are held in a buffer until the boot-time start-up health checks are performed.
+Storing the seed in this buffer, allows this seed to released to the CSRNG immediately after the entropy has been confirmed.
+
+Boot-time mode also has the feature that it bypasses the SHA conditioning function, as only 384 bits are used in the initial boot-time seed.
+
+For maximal flexibility in normal operation, the conditioning function can also be implemented by firmware.
+When this firmware conditioning feature is activated, data read directly out of the noise source can be reinjected into the entropy pipeline via a TL-UL register after it has been processed by firmware.
+It should be noted that this firmware algorithm must be vetted by NIST to satisfy the requirements for a full-entropy source.
+This feature can also be disabled for security purposes, either by locking the feature via the {{< regref "REGEN" >}} register at boot, or by a write to one-time programmable (OTP) memory.
+
## Compatibility
This IP block does not have any direct hardware compatibility requirements.
-The firmware routines, as described by SP 800-90B, must be supported.
-However, as long as the function provided by the register set supports all of the call parameters, any compatibility requirements will be met.
+However, the general design of this block follows the overall NIST recommendations, as described by SP 800-90B.
# Theory of Operations
As already described, this IP block will collect bits of entropy for firmware or hardware consumption.
-This revision supports both an LFSR for the digital implementation, and an external interface for the rng implementation.
-For the LRSR implementation, any polynomial may be used so long as it is primitive in Galois Field of order 2, or GF(2).
-However, preference should be given to polynomials with the fewest number of terms.
+This revision supports both an LFSR for the pseudo-random digital implementation, and an external interface for the PTRNG noise source implementation.
The first step is initialization and enabling.
-Before setting the `ENABLE` field, the LFSR seed input should be initialized, using the {{< regref "ES_SEED" >}} register.
-The {{< regref "ES_SEED" >}} register will transfer its value according to the initialization sequence.
+Normally PTRNG noise source mode is selected, and the `ENABLE` field will be set to enable PTRNG noise source mode.
+If using LFSR mode, before setting the `ENABLE` field, the LFSR seed input should be initialized, using the {{< regref "SEED" >}} register.
+The {{< regref "ENTROPY_RATE" >}} register will default to a sample rate of 20 microseconds, assuming a system clock rate of 100 nanoseconds.
+The {{< regref "SEED" >}} register will transfer its value to the LFSR block, but the LFSR block is locked once the `ENABLE` field is set.
After the block is enabled and initialized, entropy bits will be collected up indefinitely until disabled.
-If rng mode is desired, the `RNG_SRC_EN` bit can be set at the same time as the `ENABLE` field can be set to enable rng mode.
-It is assumed that any entropy source will drop bits.
-This means that the FIFO used to collect up the entropy bits will fill, and until the firmware or hardware starts pulling out bits, continuously generated entropy source bits may be dropped from usage.
-The process of filling and draining the FIFOs is the same, independent of what speed the entropy generation rate is at.
-Once the `es_entropy_valid` status bit is set, the firmware will read the {{< regref "ES_ENTROPY" >}} register as many times as needed to get the required entropy bits, typically 128 bits or 256 bits at a time.
-For ease of firmware operation, the status bit does not need to be reset.
-A read of the {{< regref "ES_THRESH" >}} register could be done to verify how many entries are in the FIFO at the current time.
-The {{< regref "ES_THRESH" >}} register will determine when the status bit is set, or when the interrupt will assert if enabled.
-For this revision, this same {{< regref "ES_THRESH" >}} register has a range of between 1 and 4 entries in the TLUL FIFO.
+After a reset, the ENTROPY_SRC block will start up in boot-time mode by default.
+This feature is designed to provide an initial seed's worth of entropy with lower latency than the normal FIPS/CC compliant health check process.
+Health testing will still be performed on boot-time mode entropy, but the window of checking is, by default, 384 bits instead of 1024 bits.
+When entropy is delivered to the downstream hardware block, a signal will indicate what type of entropy it is - FIPS compliant or not.
+Boot-time mode can be completely disabled in the {{< regref "CONF" >}} register.
-For hardware consumption of entropy, if the HWIF FIFO is not empty, and the entropy consuming hardware is ready, then entropy bits will be transferred over the hardware entropy interface.
+Once the initial boot-time mode phase has completed, the ENTROPY_SRC block will switch to FIPS compliant mode.
+In this mode, once the raw entropy has been health checked, it will be passed into a conditioner block.
+This block will compress the bits such that the entropy bits/physical bits, or min-entropy value, should be improved over the raw data source min-entropy value.
+The compression operation, by default, will compress every 1024 tested bits into 384 full-entropy bits.
-Health tests, when enabled in the {{< regref "ES_CONF" >}} register, will run continuously.
-Two tests are implemented in hardware, the repetition count test (RCT), and the adaptive proportion test (APT).
+The hardware conditioning can also be bypassed and replaced in normal operation with a firmware-defined conditioning algorithm.
+This firmware conditioning algorithm, can be disabled on boot for security purposes.
+The exact mechanism for this functionality will be described in a future update to this document (TBD).
-There are four health test blocks, one per inbound rng bus bit.
-Each health test block works independently from one another.
-The checks are done on the serial stream input, and an optional feature allows for passing entropy from a single bit stream source.
-Once the streams have passed the health tests, it becomes available for downstream consumption.
-If the health tests ever fail, the ES FIFO is prevented from receiving additional entropy bits up.
-The entropy health tests will continue until a clean stream is detected, at which time the ES FIFO will start collecting bits again.
-The {{< regref "ES_RCT_HEALTH" >}} register and the {{< regref "ES_APT_HEALTH" >}} register set the cutoff limits for the health tests.
+Health checks are performed on the input raw data from the PTRNG noise source when in that mode.
+There are four health tests that will be performed: repetitive count, adaptive proportion, bucket, and Markov tests.
+Each test has a pair of threshold values that determine that pass/fail of the test, one threshold for boot-time mode, and one for normal mode.
+By default, all tests are enabled, but can be turn off in the {{< regref "CONF" >}} register.
+Because of the variability of the PTRNG noise source, there are several registers that log statistics associated with the health tests.
+For example, the adaptive proportion test has a high watermark register that logs the highest measured number of ones.
+The {{< regref "ADAPTP_HI_WATERMARKS" >}} register has an entry for both normal and boot-time modes.
+This register allows for determining how close the threshold value should be set to the fail over value.
+Specific to the adaptive proportion test, there is also the {{< regref "ADAPTP_LO_WATERMARKS" >}} register, which will hold the lowest number of ones measured.
+To help understand how well the thresholds work through time, a running count of test fails is kept in the {{< regref "ADAPTP_HI_TOTAL_FAILS" >}} register.
+The above example for the adaptive proportion test also applies to the other health tests, with the exception of the low watermark registers.
+See the timing diagrams below for more details on how the health tests work.
+It should be noted that for all error counter registers, they are sized for 16 bits, which prevents any case where counters might wrap.
-The above process will be repeated for as long as entropy bits are to be collected.
-At any time, the enable bit can be cleared, and the entropy generation will halt immediately.
+The Mailbox test and Vendor-specific tests are planned, but not yet implemented.
+The theory of operation for these tests will therefore be described in a future update.
+
+The {{< regref "ALERT_THRESHOLD" >}} register determines how many fails can occur before an alert is issued.
+By default, the current threshold is set to two, such that the occurrence of two failing test cycles back-to-back would provide a very low α value.
+The {{< regref "ALERT_FAIL_COUNTS" >}} register holds the total number of fails, plus all of the individual contributing failing tests.
+Setting the {{< regref "ALERT_THRESHOLD" >}} register to zero will disable alert generation.
+
+Firmware has a path to read entropy from the ENTROPY_SRC block.
+The {{< regref "ENTROPY_CONTROL" >}} register allows firmware to set the internal multiplexers to steer entropy data to the {{< regref "ENTROPY_DATA" >}} register.
+The control bit `ES_TYPE` sets whether the entropy will come from the conditioning block or be sourced through the bypass path.
+A status bit will be set that can either be polled or generate an interrupt when the entropy bits are available to be read from the {{< regref "ENTROPY_DATA" >}} register.
+The firmware needs to read the {{< regref "ENTROPY_DATA" >}} register twelve times in order to cleanly evacuate the 384-bit seed from the hardware path (12*32bits=384bits total).
+The firmware will directly read out of the main entropy FIFO, and when the control bit `ES_ROUTE` is set, no entropy is being passed to the block hardware interface.
+If the main entropy FIFO fills up, additional entropy that has been health checked and conditioned will be dropped at that point.
+
+The above process will be repeated for as long as entropy bits are to be collected and processed.
+
+At any time, the `ENABLE` field can be cleared to halt the entropy generation (and health check testing) immediately.
## Block Diagram
@@ -104,70 +170,45 @@
In this state, the seed register will continuously be loaded into the LFSR.
The seed register can be written without restriction, regardless of any state of any control bits.
-A configuration/control register locking function is performed by the {{< regref "ES_REGEN" >}} register.
-Clearing the bit in this register will prevent future modification of the {{< regref "ES_CONF" >}} register or the {{< regref "ES_SEED" >}} by firmware.
+For simplicity of initialization, only a single register write is needed to start functional operation of the ENTROPY_SRC block.
+This assumes that proper defaults are chosen for thresholds, sampling rate, and other registers.
-The {{< regref "ES_SEED" >}} register can be updated at any time while the digital source FIFO is in operational mode.
-As long as the update sequence is followed by firmware, there will be no timing hazards when accessing these registers by the firmware.
+For security reasons, a configuration and control register locking function is performed by the {{< regref "REGEN" >}} register.
+Clearing the bit in this register will prevent future modification of the {{< regref "CONF" >}} register or other writeable registers by firmware.
### Entropy Processing
When enabled, the ENTROPY_SRC block will generate entropy bits continuously.
-The `es_entropy_valid` bit signal to the firmware when entropy bits should read from the {{< regref "ES_ENTROPY" >}} register.
-While the firmware is reading the TLUL FIFO, additional entropy bits could be captured by the TLUL FIFO as long as the TLUL FIFO is not full.
-The firmware will do 32-bit register reads of the {{< regref "ES_ENTROPY" >}} register to retrieve the entropy bits.
-Each read will automatically pop an entry off the head of the TLUL FIFO.
-New entropy bits can enter the TLUL FIFO at the tail concurrently.
+The `es_entropy_valid` bit in the `ENTROPY_SRC_INTR_STATE` register will indicate to the firmware when entropy bits can read from the {{< regref "ENTROPY_DATA" >}} register.
+The firmware will do 32-bit register reads of the {{< regref "ENTROPY_DATA" >}} register to retrieve the entropy bits.
+Each read will automatically pop an entry from the entropy unpacker block.
+A full twelve 32-bit words need to be read at a time.
-The hardware entropy interface will move entropy bits out of the HWIF FIFO when it is not empty and the downstream hardware is ready.
-The HWIF FIFO has lower priority than the TLUL FIFO, but is expected to have higher bandwidth demands.
-Because of this, higher priority is given to the TLUL FIFO so that it does not starve when the hardware entropy interface is consuming a high level of entropy bits.
+The hardware entropy interface will move entropy bits out of the ENTROPY FIFO when it is not empty, and the downstream hardware is ready.
+If firmware is not currently reading entropy bits, all processed entropy bits will flow to the hardware entropy interface.
-The {{< regref "ES_THRESH" >}} register is used to set the point of notification to the firmware.
-Notification can be either by polling or by an interrupt.
-For debug, the {{< regref "ES_FDEPTHST" >}} register can be read to find out the current state of the TLUL FIFO at any time.
-
-An additional feature is the {{< regref "ES_RATE" >}} register.
-The purpose of this register is to simulate faster or slower entropy generation sources when is digial source mode.
+An additional feature is the {{< regref "RATE" >}} register.
+The purpose of this register is to simulate faster or slower entropy generation sources than when the digital source is selected.
This will aid firmware design and debug when trying to handle all entropy source types and rates.
-When in rng mode, this register must exactly match the sample rate required by the rng source, expected to be in the range of about 25 to 50 kilohertz.
+When in PTRNG mode, this register must exactly match the sample rate required by the PTRNG source, expected to be in the range of about 25 to 50 kilohertz.
### Interrupts
-The ENTROPY_SRC module has several interrupts: `es_entropy_valid`, `es_rng_src_ok`, es_rct_failed, es_apt_failed`, and `es_fifo_err`.
+The ENTROPY_SRC module has several interrupts: `es_entropy_valid`, es_health_test_failed`, and `es_fifo_err`.
-The `es_entropy_valid` interrupt should be used when a entropy source has been implemented that is relatively slow.
+The `es_entropy_valid` interrupt should be asserted when an entropy source has been implemented that is relatively slow.
-The `es_rng_src_ok` interrupt should be used when rng entropy mode has been selected.
-Once the external entropy source is operational, this interrupt will be triggered.
+The `es_health_test_failed` interrupt will trigger when the internal health test fails and exceeds the alert threshold.
-The `es_rct_failed` interrupt will trigger when the internal health test fails the repetitive count test.
-
-The `es_apt_failed` interrupt will trigger when the internal health test fails the adaptive proportion test.
-
-The `es_fifo_err` interrupt will fire when a non-rng FIFO has a malfunction.
+The `es_fifo_err` interrupt will fire when an internal FIFO has a malfunction.
The conditions that cause this to happen are either when there is a push to a full FIFO or a pull from an empty FIFO.
-### TLUL FIFO Operational Sequence
-The following waveform shows an example of how the entropy source is collected into the TLUL FIFO.
-In this example, the TLUL FIFO parameter is fixed to a depth of 4. The {{< regref "ES_THRESH" >}} register is set to a value of 2, and will trigger an interrupt when the FIFO has met this value.
-The FIFO in this example will fill quickly, then will drain as the firmware reads the {{< regref "ES_ENTROPY" >}} register. As the entropy bits are read out, new entropy bits, if available and valid, will immediately enter the FIFO.
+## Future Features
-{{< wavejson >}}
-{signal: [
- {name: 'clk' , wave: 'p.......|............'},
- {name: 'es_enable' , wave: '01......|............'},
- {name: 'fifo_push_capt_entropy', wave: '0..1...0|.10.10.10.10', data: ['ph0','ph1','ph2','ph3']},
- {name: 'entropy_bits' , wave: 'x..3453x|.4x.5x.3x.4x', data: ['es0','es1','es2','es3','es4','es5','es6','es7']},
- {name: 'fifo_full' , wave: '0......1|.01.01.01.01'},
- {name: 'fifo_empty' , wave: '1..0....|............'},
- {name: 'fifo_pop_read_entropy' , wave: '0.......|10.10.10.10.'},
- {name: 'threshold reg' , wave: '4.......|............', data: ['2']},
- {name: 'interrupt/status' , wave: '0....1..|............'},
- {},
-]}{{< /wavejson >}}
-
+- Timer to pace health checks only when there is no demand for entropy seeds
+- One-way threshold values if regen register cannot be used
+- Support for golden test pattern
### Entropy Source Hardware Interface
The following waveform shows an example of how the entropy source hardware interface works, which is much like a FIFO.
@@ -177,15 +218,17 @@
{signal: [
{name: 'clk' , wave: 'p...................'},
{name: 'es_enable' , wave: '01..................'},
- {name: 'entropy_src_rdy_i' , wave: '0..1...0.10.101.....'},
- {name: 'entropy_src_vld_o' , wave: '0.....1...0.10.1.0..'},
- {name: 'entropy_src_bits_o' , wave: 'x.....3xx4xx5xx34x..', data: ['es0','es1','es2','es3','es4','es5','es6','es7']},
+ {name: 'es_req' , wave: '0..1...0.10.101.....'},
+ {name: 'es_ack' , wave: '0.....1...0.10.1.0..'},
+ {name: 'es_bits' , wave: 'x.....3xx4xx5xx34x..', data: ['es0','es1','es2','es3','es4','es5','es6','es7']},
+ {name: 'es_fips' , wave: '0........10.10.1.0..'},
{},
-]}{{< /wavejson >}}
+]}
+{{< /wavejson >}}
-### RNG Hardware Interface
-The following waveform shows an example of what the RNG timing looks like.
+### PTRNG Hardware Interface
+The following waveform shows an example of what the PTRNG timing looks like.
{{< wavejson >}}
@@ -193,9 +236,115 @@
{name: 'clk' , wave: 'p.|......|......|......'},
{name: 'rng_en' , wave: '01|......|......|......'},
{name: 'rng_ok' , wave: '0.|1.....|......|......'},
- {name: 'es_bit_sample' , wave: '0.|..10..|..10..|..10....'},
- {name: 'rng_b' , wave: 'x.|3.....|4.....|5.....', data: ['es0','es1','es2','es3','es4','es5','es6','es7']},
-]}{{< /wavejson >}}
+ {name: 'es_bit_sample' , wave: '0.|..10..|..10..|..10..'},
+ {name: 'rng_b' , wave: 'x.|3.....|4.....|5.....', data: ['es0','es1','es2']},
+]}
+{{< /wavejson >}}
+
+### Repetition Count Test
+The following waveform shows how a sampling of the LFSR data pattern will be tested by the Repetition Count test.
+Operating on each bit stream, this test will count when a signal is at a stuck level.
+This NIST test is intended to signal a catastrophic failure with the PTRNG noise source.
+
+
+{{< wavejson >}}
+{signal: [
+ {name: 'rng_valid' , wave: 'p...............'},
+ ['rng bits',
+ {name: 'rng_bus[3]' , wave: '1.0.10..1...0101'},
+ {name: 'rng_bus[2]' , wave: '01.0.10..1...010'},
+ {name: 'rng_bus[1]' , wave: '101.0.10..1...01'},
+ {name: 'rng_bus[0]' , wave: '10.10..1...0101.'},
+ ],
+ {name: 'thresh_i (hex)' , wave: '3...............',data: ['3']},
+ {name: 'rep_cntr_q[3] (hex)' , wave: '4444444444444444',data: ['0','0','1','0','1','0','0','1','2','0','1','2','3','0','0','0']},
+ {name: 'rep_cntr_q[2] (hex)' , wave: '4444444444444444',data: ['0','1','0','1','0','1','0','0','1','2','0','1','2','3','0','0']},
+ {name: 'rep_cntr_q[1] (hex)' , wave: '4444444444444444',data: ['0','0','0','0','1','0','1','0','0','1','2','0','1','2','3','0']},
+ {name: 'rep_cntr_q[0] (hex)' , wave: '4444444444444444',data: ['0','0','0','1','0','0','1','2','0','1','2','3','0','0','0','0']},
+ {name: 'test_cnt_q (hex)' , wave: '4444444444444444',data: ['0','0','0','0','0','0','0','0','0','0','0','1','2','3','4','0']},
+ {name: 'window_cnt_q (hex)' , wave: '5555555555555555',data: ['0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f']},
+], head:{
+ text:'Repetition Count Test',
+ tick:0,
+ },}
+{{< /wavejson >}}
+
+### Adaptive Proportion Test
+The following waveform shows how a sampling of the LFSR data pattern will be tested by the Adaptive Proportion test.
+Operating on all four bit streams, this test will count how many ones are present in the full sample period.
+This NIST test is intended to find bias when either too many or too few ones are present.
+
+{{< wavejson >}}
+{signal: [
+ {name: 'rng_valid' , wave: 'p...............'},
+ ['rng bits',
+ {name: 'rng_bus[3]' , wave: '1.0.10..1...0101'},
+ {name: 'rng_bus[2]' , wave: '01.0.10..1...010'},
+ {name: 'rng_bus[1]' , wave: '101.0.10..1...01'},
+ {name: 'rng_bus[0]' , wave: '10.10..1...0101.'},
+ ],
+ {name: 'column_cnt (hex)' , wave: '3333333333333333',data: ['3','2','2','2','1','1','1','1','2','3', '4', '3', '3', '2', '2','3']},
+ {name: 'test_cnt_q (hex)' , wave: '4444444444444444',data: ['0','3','5','7','9','a','b','c','d','f','12','16','19','1c','1e','20']},
+ {name: 'window_cnt_q (hex)' , wave: '5555555555555555',data: ['0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f']},
+], head:{
+ text:'Adaptive Proportion Test',
+ tick:0,
+ },}
+{{< /wavejson >}}
+
+### Bucket Test
+The following waveform shows how a sampling of the LFSR data pattern will be tested by the Bucket test.
+Operating on all four bit streams, this test will identify the symbol and sort it into bin counters, or "buckets".
+This test is intended to find bias with a symbol or symbols.
+
+{{< wavejson >}}
+{signal: [
+ {name: 'rng_valid' , wave: 'p...............'},
+ ['rng bits',
+ {name: 'rng_bus[3]' , wave: '1.0.10..1...0101'},
+ {name: 'rng_bus[2]' , wave: '01.0.10..1...010'},
+ {name: 'rng_bus[1]' , wave: '101.0.10..1...01'},
+ {name: 'rng_bus[0]' , wave: '10.10..1...0101.'},
+ ],
+ {name: 'thresh_i (hex)' , wave: '3...............',data: ['3']},
+ {name: 'bin_cntr_q[0] (hex)' , wave: '4...............',data: ['0']},
+ {name: 'bin_cntr_q[1] (hex)' , wave: '4........4......',data: ['0','1']},
+ {name: 'bin_cntr_q[2] (hex)' , wave: '4.......4.......',data: ['0','1']},
+ {name: 'bin_cntr_q[13] (hex)' , wave: '4..........4....',data: ['0','1']},
+ {name: 'bin_cntr_q[14] (hex)' , wave: '4............4..',data: ['0','1']},
+ {name: 'bin_cntr_q[15] (hex)' , wave: '4...........4...',data: ['0','1']},
+ {name: 'test_cnt_q (hex)' , wave: '4...............',data: ['0']},
+ {name: 'window_cnt_q (hex)' , wave: '5555555555555555',data: ['0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f']},
+], head:{
+ text:'Bucket Test',
+ tick:0,
+ },}
+{{< /wavejson >}}
+
+### Markov Test
+The following waveform shows how a sampling of the LFSR data pattern will be tested by the Markov test.
+Operating on all four bit streams, this test will identify pairs of transitions in time per bit stream.
+Specifically, only pairs of `0b01` and `0b10` will be counted.
+
+{{< wavejson >}}
+{signal: [
+ {name: 'rng_valid' , wave: 'p...............'},
+ ['rng bits',
+ {name: 'rng_bus[3]' , wave: '1.0.10..1...0101'},
+ {name: 'rng_bus[2]' , wave: '01.0.10..1...010'},
+ {name: 'rng_bus[1]' , wave: '101.0.10..1...01'},
+ {name: 'rng_bus[0]' , wave: '10.10..1...0101.'},
+ ],
+ {name: 'pair_cntr_q[3] (hex)', wave: '4.4.4.4.4.4.4.4.',data: ['0','0','0','1','1','1','1','2']},
+ {name: 'pair_cntr_q[2] (hex)', wave: '4.4.4.4.4.4.4.4.',data: ['0','1','2','3','3','4','4','5']},
+ {name: 'pair_cntr_q[1] (hex)', wave: '4.4.4.4.4.4.4.4.',data: ['0','1','1','1','2','2','2','2']},
+ {name: 'pair_cntr_q[0] (hex)', wave: '4.4.4.4.4.4.4.4.',data: ['0','1','2','2','3','3','4','5']},
+ {name: 'window_cnt_q (hex)' , wave: '5555555555555555',data: ['0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f']},
+], head:{
+ text:'Markov Test',
+ tick:0,
+ },}
+{{< /wavejson >}}
# Programmers Guide
@@ -206,19 +355,13 @@
```cpp
-void entropy_src_init(unsigned int seed, unsigned int thresh) {
+void entropy_src_init(unsigned int rate) {
- // set the seed value
- *ES_SEED_REG = seed;
+ // set the rate value (optional)
+ *SEED_REG = rate;
- // set the threshold value
- *ES_THRESH_REG = thresh;
-
- // set the configuration enable bits (digial mode)
- *ES_CONF_REG = 0x1;
-
- // or set the configuration enable bits (rng mode)
- *ES_CONF_REG = 0x2;
+ // set the configuration enable bits (rng mode, all health tests enabled)
+ *CONF_REG = 0x1;
// the ENTROPY_SRC interrupts can optionally be enabled
}
@@ -232,8 +375,8 @@
int entropy_src_entropy(unsigned int numEntropyBits) {
- // read numEntropyBits, check for ENTROPY_SRC_INTR_STATE bit 0
- return *ES_ENTROPY_REG;
+ // read numEntropyBits, check for ENTROPY_SRC_INTR_STATE bit 0
+ return *ENTROPY_DATA_REG;
}
```
@@ -243,8 +386,6 @@
Need to alert the system of a FIFO overflow condition.
-
## Register Table
-
{{< registers "hw/ip/entropy_src/data/entropy_src.hjson" >}}
diff --git a/hw/ip/entropy_src/doc/entsrc_blk_diag.svg b/hw/ip/entropy_src/doc/entsrc_blk_diag.svg
index 049e6c8..3f20239 100755
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+++ b/hw/ip/entropy_src/doc/entsrc_blk_diag.svg
@@ -3,7 +3,7 @@
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+ <g id="shape480-1" v:mID="480" v:groupContext="shape" transform="translate(73.8258,-324)">
<title>Sheet.480</title>
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+ <v:ud v:nameU="VertexCount" v:prompt="" v:val="VT0(4):26"/>
+ <v:ud v:nameU="SegmentType" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="DrawType" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="StartWidth" v:prompt="" v:val="VT0(0.15):0"/>
+ <v:ud v:nameU="EndWidth" v:prompt="" v:val="VT0(0.1):0"/>
+ <v:ud v:nameU="LastAngle" v:prompt="" v:val="VT0(0.31445460881394):32"/>
+ <v:ud v:nameU="CtrlAngle" v:prompt="" v:val="VT0(-1.6821373411359):32"/>
+ <v:ud v:nameU="ArrowFeatherAngle" v:prompt="" v:val="VT0(8.5942318659433):32"/>
+ <v:ud v:nameU="ArrowFeatherDist" v:prompt="" v:val="VT0(0.20124611797498):0"/>
+ <v:ud v:nameU="Joint1_2Pcnt" v:prompt="" v:val="VT0(0.36115492854311):26"/>
+ <v:ud v:nameU="Joint1_2Angle" v:prompt="" v:val="VT0(1.4583288317516):32"/>
+ <v:ud v:nameU="Joint2_3Pcnt" v:prompt="" v:val="VT0(0.737773973763):26"/>
+ <v:ud v:nameU="Joint2_3Angle" v:prompt="" v:val="VT0(1.4437657331855):32"/>
+ <v:ud v:nameU="Joint3_4Pcnt" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="Joint3_4Angle" v:prompt="" v:val="VT0(1.8852509356088):32"/>
+ <v:ud v:nameU="Joint4_5Pcnt" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="Joint4_5Angle" v:prompt="" v:val="VT0(1.8852509356088):32"/>
+ <v:ud v:nameU="Joint5_6Pcnt" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="Joint5_6Angle" v:prompt="" v:val="VT0(1.8852509356088):32"/>
+ <v:ud v:nameU="Joint6_7Pcnt" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="Joint6_7Angle" v:prompt="" v:val="VT0(1.8852509356088):32"/>
+ <v:ud v:nameU="Joint7_8Pcnt" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="Joint7_8Angle" v:prompt="" v:val="VT0(1.8852509356088):32"/>
+ <v:ud v:nameU="Joint8_9Pcnt" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="Joint8_9Angle" v:prompt="" v:val="VT0(1.8852509356088):32"/>
+ <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+ <v:ud v:nameU="VertexCount" v:prompt="" v:val="VT0(2):26"/>
+ <v:ud v:nameU="LastAngle" v:prompt="" v:val="VT0(0):26"/>
+ <v:ud v:nameU="CtrlAngle" v:prompt="" v:val="VT0(-1.6098339366519):32"/>
+ <v:ud v:nameU="ArrowFeatherAngle" v:prompt="" v:val="VT0(7.8930192438315):32"/>
+ <v:ud v:nameU="ArrowFeatherDist" v:prompt="" v:val="VT0(0.20015249032408):0"/>
+ <v:ud v:nameU="Joint1_2Pcnt" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="Joint1_2Angle" v:prompt="" v:val="VT0(1.5707963267949):37"/>
+ <v:ud v:nameU="Joint2_3Pcnt" v:prompt="" v:val="VT0(1):26"/>
+ <v:ud v:nameU="Joint2_3Angle" v:prompt="" v:val="VT0(1.5707963267949):37"/>
+ <v:ud v:nameU="Joint3_4Angle" v:prompt="" v:val="VT0(1.5707963267949):37"/>
+ <v:ud v:nameU="Joint4_5Angle" v:prompt="" v:val="VT0(1.5707963267949):37"/>
+ <v:ud v:nameU="Joint5_6Angle" v:prompt="" v:val="VT0(1.5707963267949):37"/>
+ <v:ud v:nameU="Joint6_7Angle" v:prompt="" v:val="VT0(1.5707963267949):37"/>
+ <v:ud v:nameU="Joint7_8Angle" v:prompt="" v:val="VT0(1.5707963267949):37"/>
+ <v:ud v:nameU="Joint8_9Angle" v:prompt="" v:val="VT0(1.5707963267949):37"/>
+ </v:userDefs>
+ <path d="M0 612 L22.4 612" class="st12"/>
</g>
</g>
</svg>
diff --git a/hw/ip/entropy_src/entropy_src.core b/hw/ip/entropy_src/entropy_src.core
index 732c42f..981953d 100644
--- a/hw/ip/entropy_src/entropy_src.core
+++ b/hw/ip/entropy_src/entropy_src.core
@@ -15,7 +15,13 @@
- rtl/entropy_src_pkg.sv
- rtl/entropy_src_reg_pkg.sv
- rtl/entropy_src_reg_top.sv
- - rtl/entropy_src_shtests.sv
+ - rtl/entropy_src_watermark_reg.sv
+ - rtl/entropy_src_cntr_reg.sv
+ - rtl/entropy_src_main_sm.sv
+ - rtl/entropy_src_repcnt_ht.sv
+ - rtl/entropy_src_adaptp_ht.sv
+ - rtl/entropy_src_bucket_ht.sv
+ - rtl/entropy_src_markov_ht.sv
- rtl/entropy_src_core.sv
- rtl/entropy_src.sv
file_type: systemVerilogSource
diff --git a/hw/ip/entropy_src/rtl/entropy_src.sv b/hw/ip/entropy_src/rtl/entropy_src.sv
index 1269dd1..c731016 100755
--- a/hw/ip/entropy_src/rtl/entropy_src.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src.sv
@@ -6,7 +6,7 @@
module entropy_src import entropy_src_pkg::*; #(
- parameter int unsigned EsFifoDepth = 16
+ parameter int unsigned EsFifoDepth = 2
) (
input clk_i,
input rst_ni,
@@ -26,10 +26,13 @@
output entropy_src_rng_req_t entropy_src_rng_o,
input entropy_src_rng_rsp_t entropy_src_rng_i,
+ // Alerts
+ input prim_alert_pkg::alert_rx_t alert_rx_i,
+ output prim_alert_pkg::alert_tx_t alert_tx_o,
+
// Interrupts
output logic es_entropy_valid_o,
- output logic es_rct_failed_o,
- output logic es_apt_failed_o,
+ output logic es_health_test_failed_o,
output logic es_fifo_err_o
);
@@ -38,6 +41,8 @@
entropy_src_reg2hw_t reg2hw;
entropy_src_hw2reg_t hw2reg;
+ logic alert_event;
+
entropy_src_reg_top u_reg (
.clk_i,
.rst_ni,
@@ -65,10 +70,24 @@
.entropy_src_rng_o,
.entropy_src_rng_i,
+ .alert_event_o(alert_event),
+
.es_entropy_valid_o,
- .es_rct_failed_o,
- .es_apt_failed_o,
+ .es_health_test_failed_o,
.es_fifo_err_o
);
+ prim_alert_sender #(
+ .AsyncOn(1'b0) // TODO: does this need to be AsyncOn
+ ) u_alert_sender_i (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
+ .alert_i ( alert_event ),
+ .alert_rx_i ( alert_rx_i ),
+ .alert_tx_o ( alert_tx_o )
+ );
+
+ // Outputs should have a known value after reset
+ `ASSERT_KNOWN(AlertTxKnown, alert_tx_o)
+
endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv
new file mode 100755
index 0000000..e89c17d
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv
@@ -0,0 +1,83 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src adaptive proportion health test module
+//
+
+module entropy_src_adaptp_ht #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned RngBusWidth = 4
+) (
+ input clk_i,
+ input rst_ni,
+
+ // ins req interface
+ input logic [RngBusWidth-1:0] entropy_bit_i,
+ input logic entropy_bit_vld_i,
+ input logic clear_i,
+ input logic active_i,
+ input logic [RegWidth-1:0] thresh_hi_i,
+ input logic [RegWidth-1:0] thresh_lo_i,
+ input logic [RegWidth-1:0] window_i,
+ output logic [RegWidth-1:0] test_cnt_o,
+ output logic test_done_pulse_o,
+ output logic test_fail_hi_pulse_o,
+ output logic test_fail_lo_pulse_o
+);
+
+ // signals
+ logic [RegWidth-1:0] column_cnt;
+ logic window_cntr_wrap;
+
+ // flops
+ logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
+ logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ window_cntr_q <= '0;
+ test_cnt_q <= '0;
+ end else begin
+ window_cntr_q <= window_cntr_d;
+ test_cnt_q <= test_cnt_d;
+ end
+
+
+ // Adaptive Proportion Test
+ //
+ // Test operation
+ // This is an approved modification of the NIST Adaptive Proportion test in that
+ // instead of counting the first sampled value (1'b1 or 1'b0), it will count
+ // only the 1's on all four bit streams and accumulate for the during of the
+ // window size (W) of the test.
+
+
+ // Number of ones per column
+ assign column_cnt = entropy_bit_i[3]+entropy_bit_i[2]+entropy_bit_i[1]+entropy_bit_i[0];
+
+ // Window wrap condition
+ assign window_cntr_wrap = (window_cntr_q == window_i);
+
+ // Window counter
+ assign window_cntr_d =
+ clear_i ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (window_cntr_q+1) :
+ window_cntr_q;
+
+ // Test event counter
+ assign test_cnt_d =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (test_cnt_q+column_cnt) :
+ test_cnt_q;
+
+ // the pulses will be only one clock in length
+ assign test_fail_hi_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > thresh_hi_i);
+ assign test_fail_lo_pulse_o = active_i && window_cntr_wrap && (test_cnt_q < thresh_lo_i);
+ assign test_done_pulse_o = window_cntr_wrap;
+ assign test_cnt_o = test_cnt_q;
+
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_align_sm.sv b/hw/ip/entropy_src/rtl/entropy_src_align_sm.sv
deleted file mode 100755
index 0a93d4f..0000000
--- a/hw/ip/entropy_src/rtl/entropy_src_align_sm.sv
+++ /dev/null
@@ -1,140 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: entropy_src byte allignment of entropy bits state machine module
-//
-
-module entropy_src_align_sm (
- input clk_i,
- input rst_ni,
-
- // ins req interface
- input logic es_enable_i,
- input logic es_health_fail_i,
- input logic upstr_fifo_vld_i,
- input logic dwstr_fifo_not_full_i,
- output logic dwstr_fifo_push_o,
- output logic es_load_byte0_o,
- output logic es_load_byte1_o,
- output logic es_load_byte2_o,
- output logic es_load_byte3_o,
- input logic other_dwstr_fifo_empty_i,
- output logic dwstr_fifo_swap_o,
- output logic dwstr_fifo_clr_o
-);
-
-
- typedef enum logic [3:0] {
- IDLE = 4'h0,
- BYTE0 = 4'h1,
- BYTE1 = 4'h2,
- BYTE2 = 4'h3,
- BYTE3 = 4'h4,
- PUSH = 4'h5,
- FCHK = 4'h6,
- SWAP = 4'h7,
- BAIL = 4'h8
- } state_e;
-
- state_e state_q, state_d;
-
-
- always_ff @(posedge clk_i or negedge rst_ni)
- if (!rst_ni) begin
- state_q <= IDLE;
- end else begin
- state_q <= state_d;
- end
-
-
- always_comb begin
- state_d = state_q;
- dwstr_fifo_push_o = 1'b0;
- es_load_byte0_o = 1'b0;
- es_load_byte1_o = 1'b0;
- es_load_byte2_o = 1'b0;
- es_load_byte3_o = 1'b0;
- dwstr_fifo_clr_o = 1'b0;
- dwstr_fifo_swap_o = 1'b0;
- unique case (state_q)
-// case (state_q)
- IDLE: begin
- if (es_enable_i) begin
- state_d = BYTE0;
- end
- end
- BYTE0: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (upstr_fifo_vld_i) begin
- es_load_byte0_o = 1'b1;
- state_d = BYTE1;
- end else begin
- state_d = BYTE0;
- end
- end
- BYTE1: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (upstr_fifo_vld_i) begin
- es_load_byte1_o = 1'b1;
- state_d = BYTE2;
- end else begin
- state_d = BYTE1;
- end
- end
- BYTE2: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (upstr_fifo_vld_i) begin
- es_load_byte2_o = 1'b1;
- state_d = BYTE3;
- end else begin
- state_d = BYTE2;
- end
- end
- BYTE3: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (upstr_fifo_vld_i) begin
- es_load_byte3_o = 1'b1;
- state_d = PUSH;
- end else begin
- state_d = BYTE3;
- end
- end
- PUSH: begin
- if (es_health_fail_i) begin
- state_d = BAIL;
- end else if (dwstr_fifo_not_full_i) begin
- dwstr_fifo_push_o = 1'b1;
- state_d = FCHK;
- end else begin
- state_d = PUSH;
- end
- end
- FCHK: begin
- if (!dwstr_fifo_not_full_i) begin
- state_d = SWAP;
- end else begin
- state_d = IDLE;
- end
- end
- SWAP: begin
- if (other_dwstr_fifo_empty_i) begin
- dwstr_fifo_swap_o = 1'b1;
- state_d = IDLE;
- end else begin
- state_d = SWAP;
- end
- end
- BAIL: begin
- dwstr_fifo_clr_o = 1'b1;
- state_d = IDLE;
- end
- default: state_d = IDLE;
- endcase
- end
-
-endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv
new file mode 100755
index 0000000..bb29249
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv
@@ -0,0 +1,100 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src bucket health test module
+//
+
+module entropy_src_bucket_ht #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned RngBusWidth = 4
+) (
+ input clk_i,
+ input rst_ni,
+
+ // ins req interface
+ input logic [RngBusWidth-1:0] entropy_bit_i,
+ input logic entropy_bit_vld_i,
+ input logic clear_i,
+ input logic active_i,
+ input logic [RegWidth-1:0] thresh_i,
+ input logic [RegWidth-1:0] window_i,
+ output logic [RegWidth-1:0] test_cnt_o,
+ output logic test_done_pulse_o,
+ output logic test_fail_pulse_o
+);
+
+ localparam int NUM_BINS = 2**RngBusWidth;
+
+ // signals
+ logic window_cntr_wrap;
+ logic [NUM_BINS-1:0] bin_incr;
+ logic [NUM_BINS-1:0] bin_cnt_exceeds_thresh;
+
+ // flops
+ logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
+ logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
+ logic [RegWidth-1:0] bin_cntr_q[NUM_BINS], bin_cntr_d[NUM_BINS];
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ window_cntr_q <= '0;
+ test_cnt_q <= '0;
+ bin_cntr_q <= {10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,
+ 10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,10'b0,10'b0};
+ end else begin
+ window_cntr_q <= window_cntr_d;
+ test_cnt_q <= test_cnt_d;
+ bin_cntr_q <= bin_cntr_d;
+ end
+
+
+ // Bucket Test
+ //
+ // Test operation
+ // This test will look at 4 bit symbols and increment one of sixteen
+ // counters, or buckets, to show a histogram of the data stream.
+ // An error will occur if one of the counters reaches the thresh
+ // value.
+
+
+ // Analyze the incoming symbols
+
+ genvar i;
+ generate
+ for (i = 0; i < NUM_BINS; i = i + 1) begin : g_symbol_match
+ // set the bin incrementer if the symbol matches that bin
+ assign bin_incr[i] = entropy_bit_vld_i && (entropy_bit_i == i);
+ // use the bin incrementer to increase the bin total count
+ assign bin_cntr_d[i] = window_cntr_wrap ? '0 :
+ ((active_i && bin_incr[i]) ? (bin_cntr_q[i]+1) : bin_cntr_q[i]);
+ // use the bin incrementer to increase the bin total count
+ assign bin_cnt_exceeds_thresh[i] = (bin_cntr_q[i] > thresh_i);
+ end
+ endgenerate
+
+
+ // Window wrap condition
+ assign window_cntr_wrap = (window_cntr_q == window_i);
+
+ // Window counter
+ assign window_cntr_d =
+ clear_i ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (window_cntr_q+1) :
+ window_cntr_q;
+
+ // Test event counter
+ assign test_cnt_d =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i && (|bin_cnt_exceeds_thresh) ? (test_cnt_q+1) :
+ test_cnt_q;
+
+ // the pulses will be only one clock in length
+ assign test_fail_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > '0);
+ assign test_done_pulse_o = window_cntr_wrap;
+ assign test_cnt_o = test_cnt_q;
+
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv b/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv
new file mode 100755
index 0000000..4846829
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv
@@ -0,0 +1,40 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src counter register module
+//
+
+module entropy_src_cntr_reg #(
+ parameter int unsigned RegWidth = 16
+) (
+ input logic clk_i,
+ input logic rst_ni,
+
+ // functional interface
+ input logic clear_i,
+ input logic active_i,
+ input logic event_i,
+ output logic [RegWidth-1:0] value_o
+);
+
+ // signals
+
+ // flops
+ logic [RegWidth-1:0] event_cntr_q, event_cntr_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ event_cntr_q <= '0;
+ end else begin
+ event_cntr_q <= event_cntr_d;
+ end
+
+ // counter will not wrap when full value is reached
+ assign event_cntr_d = (!active_i || clear_i) ? '0 :
+ (event_i && (~event_cntr_q != '0)) ? event_cntr_q+1 :
+ event_cntr_q;
+
+ assign value_o = event_cntr_q;
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv
index 8c8d601..c144bca 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_core.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -6,7 +6,7 @@
//
module entropy_src_core import entropy_src_pkg::*; #(
- parameter int unsigned EsFifoDepth = 16
+ parameter int unsigned EsFifoDepth = 2
) (
input clk_i,
input rst_ni,
@@ -26,124 +26,213 @@
output entropy_src_rng_req_t entropy_src_rng_o,
input entropy_src_rng_rsp_t entropy_src_rng_i,
+ output logic alert_event_o,
+
output logic es_entropy_valid_o,
- output logic es_rct_failed_o,
- output logic es_apt_failed_o,
+ output logic es_health_test_failed_o,
output logic es_fifo_err_o
);
import entropy_src_reg_pkg::*;
- localparam int unsigned PostHTDepth = $clog2(EsFifoDepth);
+ localparam int unsigned Clog2EsFifoDepth = $clog2(EsFifoDepth);
+ localparam int unsigned PostHTWidth = 64;
localparam int unsigned RngBusWidth = 4;
+ localparam int unsigned HalfRegWidth = 16;
+ localparam int unsigned FullRegWidth = 32;
+ localparam int unsigned EigthRegWidth = 4;
+ localparam int unsigned SeedLen = 384;
// signals
logic [RngBusWidth-1:0] lfsr_value;
logic [RngBusWidth-1:0] seed_value;
logic load_seed;
logic es_enable;
- logic es_enable_dig;
+ logic es_enable_lfsr;
logic es_enable_rng;
logic rng_bit_en;
logic [1:0] rng_bit_sel;
- logic lfsr_enable;
- logic esentropy_rd_pls;
+ logic lfsr_incr;
+ logic sw_es_rd_pulse;
logic event_es_entropy_valid;
- logic event_es_apt_failed;
- logic event_es_rct_failed;
-// logic event_es_rng_bits_err;
+ logic event_es_health_test_failed;
logic event_es_fifo_err;
logic [15:0] es_rate;
- logic es_rate_entropy_valid;
- logic es_rate_entropy_valid_en;
- logic [2:0] es_fifo_thresh;
- logic es_rng_src_ok;
+ logic es_rate_entropy_pulse;
+ logic es_rng_src_ok;
+ logic [RngBusWidth-1:0] es_rng_bus;
- logic sfifo_esdig_push;
- logic sfifo_esdig_pop;
- logic sfifo_esdig_clr;
- logic [RngBusWidth-1:0] sfifo_esdig_wdata;
- logic [RngBusWidth-1:0] sfifo_esdig_rdata;
- logic [2:0] sfifo_esdig_depth;
- logic sfifo_esdig_not_full;
- logic sfifo_esdig_not_empty;
- logic sfifo_esdig_err;
+ logic [RngBusWidth-1:0] sfifo_esrng_wdata;
+ logic [RngBusWidth-1:0] sfifo_esrng_rdata;
+ logic sfifo_esrng_push;
+ logic sfifo_esrng_pop;
+ logic sfifo_esrng_clr;
+ logic sfifo_esrng_not_empty;
+ logic sfifo_esrng_err;
- logic sfifo_postht_push;
- logic sfifo_postht_pop;
- logic sfifo_postht_clr;
- logic [31:0] sfifo_postht_wdata;
- logic [31:0] sfifo_postht_rdata;
- logic [PostHTDepth:0] sfifo_postht_depth;
- logic sfifo_postht_not_full;
- logic sfifo_postht_not_empty;
- logic sfifo_postht_err;
- logic sfifo_postht_avail;
+ logic [Clog2EsFifoDepth:0] sfifo_esfinal_depth;
+ logic [(1+SeedLen)-1:0] sfifo_esfinal_wdata;
+ logic [(1+SeedLen)-1:0] sfifo_esfinal_rdata;
+ logic sfifo_esfinal_push;
+ logic sfifo_esfinal_pop;
+ logic sfifo_esfinal_clr;
+ logic sfifo_esfinal_not_full;
+ logic sfifo_esfinal_not_empty;
+ logic sfifo_esfinal_err;
+ logic [SeedLen-1:0] esfinal_data;
+ logic esfinal_fips_flag;
- logic sfifo_essw_push;
- logic sfifo_essw_pop;
- logic sfifo_essw_clr;
- logic [31:0] sfifo_essw_wdata;
- logic [31:0] sfifo_essw_rdata;
- logic [2:0 ] sfifo_essw_depth;
- logic sfifo_essw_not_full;
- logic sfifo_essw_not_empty;
- logic sfifo_essw_err;
+ logic any_active;
+ logic any_fail_pulse;
+ logic main_stage_pop;
+ logic bypass_stage_pop;
+ logic [EigthRegWidth-1:0] any_fail_count;
+ logic [EigthRegWidth-1:0] alert_threshold;
+ logic alert_event;
+ logic repcnt_active;
+ logic adaptp_active;
+ logic bucket_active;
+ logic markov_active;
+ logic alert_cntrs_clr;
+ logic health_test_clr;
+ logic health_test_done_pulse;
+ logic [RngBusWidth-1:0] health_test_esbus;
+ logic health_test_esbus_vld;
+ logic es_route_to_sw;
+ logic es_bypass_to_sw;
+ logic es_bypass_mode;
+ logic rst_bypass_mode;
+ logic rst_alert_cntr;
+ logic boot_bypass_disable;
+ logic fips_compliance;
- logic sfifo_eshw_push;
- logic sfifo_eshw_pop;
- logic sfifo_eshw_clr;
- logic [31:0] sfifo_eshw_wdata;
- logic [31:0] sfifo_eshw_rdata;
- logic [2:0] sfifo_eshw_depth;
- logic sfifo_eshw_not_full;
- logic sfifo_eshw_not_empty;
- logic sfifo_eshw_err;
+ logic [HalfRegWidth-1:0] health_test_fips_window;
+ logic [HalfRegWidth-1:0] health_test_bypass_window;
+ logic [HalfRegWidth-1:0] health_test_window;
+ logic [HalfRegWidth-1:0] repcnt_fips_threshold;
+ logic [HalfRegWidth-1:0] repcnt_bypass_threshold;
+ logic [HalfRegWidth-1:0] repcnt_threshold;
+ logic [HalfRegWidth-1:0] repcnt_event_cnt;
+ logic [HalfRegWidth-1:0] repcnt_event_hwm_fips;
+ logic [HalfRegWidth-1:0] repcnt_event_hwm_bypass;
+ logic [FullRegWidth-1:0] repcnt_total_fails;
+ logic [EigthRegWidth-1:0] repcnt_fail_count;
+ logic repcnt_fail_pulse;
-// logic [RngBusWidth-1:0] rng_bits_err;
- logic [RngBusWidth-1:0] rct_active;
- logic [15:0] rct_max_cnt;
- logic [RngBusWidth-1:0] apt_active;
- logic [15:0] apt_max_cnt;
- logic [15:0] apt_window;
- logic [RngBusWidth-1:0] apt_fail_pls;
- logic [RngBusWidth-1:0] rct_fail_pls;
- logic [RngBusWidth-1:0] shtests_passing;
- logic [RngBusWidth-1:0] packer_esbus_wdata;
- logic [31:0] packer_esbus_rdata;
- logic packer_esbus_push;
- logic packer_esbus_clr;
- logic packer_esbus_valid;
- logic packer_esbit_wdata;
- logic [31:0] packer_esbit_rdata;
- logic packer_esbit_push;
- logic packer_esbit_clr;
- logic packer_esbit_valid;
- logic packer_valid;
- logic fill_sfifo_essw;
+ logic [HalfRegWidth-1:0] adaptp_hi_fips_threshold;
+ logic [HalfRegWidth-1:0] adaptp_hi_bypass_threshold;
+ logic [HalfRegWidth-1:0] adaptp_hi_threshold;
+ logic [HalfRegWidth-1:0] adaptp_lo_fips_threshold;
+ logic [HalfRegWidth-1:0] adaptp_lo_bypass_threshold;
+ logic [HalfRegWidth-1:0] adaptp_lo_threshold;
+ logic [HalfRegWidth-1:0] adaptp_event_cnt;
+ logic [HalfRegWidth-1:0] adaptp_hi_event_hwm_fips;
+ logic [HalfRegWidth-1:0] adaptp_hi_event_hwm_bypass;
+ logic [HalfRegWidth-1:0] adaptp_lo_event_hwm_fips;
+ logic [HalfRegWidth-1:0] adaptp_lo_event_hwm_bypass;
+ logic [FullRegWidth-1:0] adaptp_hi_total_fails;
+ logic [FullRegWidth-1:0] adaptp_lo_total_fails;
+ logic [EigthRegWidth-1:0] adaptp_hi_fail_count;
+ logic [EigthRegWidth-1:0] adaptp_lo_fail_count;
+ logic adaptp_hi_fail_pulse;
+ logic adaptp_lo_fail_pulse;
+
+ logic [HalfRegWidth-1:0] bucket_fips_threshold;
+ logic [HalfRegWidth-1:0] bucket_bypass_threshold;
+ logic [HalfRegWidth-1:0] bucket_threshold;
+ logic [HalfRegWidth-1:0] bucket_event_cnt;
+ logic [HalfRegWidth-1:0] bucket_event_hwm_fips;
+ logic [HalfRegWidth-1:0] bucket_event_hwm_bypass;
+ logic [FullRegWidth-1:0] bucket_total_fails;
+ logic [EigthRegWidth-1:0] bucket_fail_count;
+ logic bucket_fail_pulse;
+
+ logic [HalfRegWidth-1:0] markov_fips_threshold;
+ logic [HalfRegWidth-1:0] markov_bypass_threshold;
+ logic [HalfRegWidth-1:0] markov_threshold;
+ logic [HalfRegWidth-1:0] markov_event_cnt;
+ logic [HalfRegWidth-1:0] markov_event_hwm_fips;
+ logic [HalfRegWidth-1:0] markov_event_hwm_bypass;
+ logic [FullRegWidth-1:0] markov_total_fails;
+ logic [EigthRegWidth-1:0] markov_fail_count;
+ logic markov_fail_pulse;
+
+ logic pfifo_esbit_wdata;
+ logic [RngBusWidth-1:0] pfifo_esbit_rdata;
+ logic pfifo_esbit_not_empty;
+ logic pfifo_esbit_push;
+ logic pfifo_esbit_clr;
+ logic pfifo_esbit_pop;
+
+ logic [RngBusWidth-1:0] pfifo_postht_wdata;
+ logic [PostHTWidth-1:0] pfifo_postht_rdata;
+ logic pfifo_postht_not_empty;
+ logic pfifo_postht_push;
+ logic pfifo_postht_clr;
+ logic pfifo_postht_pop;
+
+ logic [PostHTWidth-1:0] pfifo_cond_wdata;
+ logic [SeedLen-1:0] pfifo_cond_rdata;
+ logic pfifo_cond_not_empty;
+ logic pfifo_cond_push;
+ logic pfifo_cond_clr;
+ logic pfifo_cond_pop;
+
+ logic [PostHTWidth-1:0] pfifo_bypass_wdata;
+ logic [SeedLen-1:0] pfifo_bypass_rdata;
+ logic pfifo_bypass_not_empty;
+ logic pfifo_bypass_push;
+ logic pfifo_bypass_clr;
+ logic pfifo_bypass_pop;
+
+ logic [SeedLen-1:0] pfifo_swread_wdata;
+ logic pfifo_swread_not_full;
+ logic [FullRegWidth-1:0] pfifo_swread_rdata;
+ logic pfifo_swread_not_empty;
+ logic pfifo_swread_push;
+ logic pfifo_swread_clr;
+ logic pfifo_swread_pop;
+
+ logic [SeedLen-1:0] final_es_data;
+
// flops
- logic entropy_val_q, entropy_val_d;
logic [15:0] es_rate_cntr_q, es_rate_cntr_d;
-// logic rng_bits_err_q, rng_bits_err_d;
+ logic lfsr_incr_dly_q, lfsr_incr_dly_d;
+ logic [RngBusWidth-1:0] ht_esbus_dly_q, ht_esbus_dly_d;
+ logic ht_esbus_vld_dly_q, ht_esbus_vld_dly_d;
+ logic ht_esbus_vld_dly2_q, ht_esbus_vld_dly2_d;
+ logic boot_bypass_q, boot_bypass_d;
+ logic ht_failed_q, ht_failed_d;
always_ff @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
- entropy_val_q <= '0;
es_rate_cntr_q <= 16'h0001;
-// rng_bits_err_q <= '0;
+ lfsr_incr_dly_q <= '0;
+ boot_bypass_q <= 1'b1;
+ ht_failed_q <= '0;
+ ht_esbus_dly_q <= '0;
+ ht_esbus_vld_dly_q <= '0;
+ ht_esbus_vld_dly2_q <= '0;
end else begin
- entropy_val_q <= entropy_val_d;
es_rate_cntr_q <= es_rate_cntr_d;
-// rng_bits_err_q <= rng_bits_err_d;
+ lfsr_incr_dly_q <= lfsr_incr_dly_d;
+ boot_bypass_q <= boot_bypass_d;
+ ht_failed_q <= ht_failed_d;
+ ht_esbus_dly_q <= ht_esbus_dly_d;
+ ht_esbus_vld_dly_q <= ht_esbus_vld_dly_d;
+ ht_esbus_vld_dly2_q <= ht_esbus_vld_dly2_d;
end
- assign es_enable = (|reg2hw.es_conf.enable.q);
- assign es_enable_dig = reg2hw.es_conf.enable.q[0];
- assign es_enable_rng = reg2hw.es_conf.enable.q[1];
- assign load_seed = ~es_enable;
+ assign es_enable = (|reg2hw.conf.enable.q);
+ assign es_enable_lfsr = reg2hw.conf.enable.q[1];
+ assign es_enable_rng = reg2hw.conf.enable.q[0];
+ assign load_seed = !es_enable;
- assign entropy_src_rng_o.rng_enable = reg2hw.es_conf.rng_src_en.q;
+ assign entropy_src_rng_o.rng_enable = es_enable_rng;
+
+ assign es_rng_src_ok = entropy_src_rng_i.rng_ok;
+ assign es_rng_bus = entropy_src_rng_i.rng_b;
//--------------------------------------------
@@ -151,8 +240,8 @@
//--------------------------------------------
prim_intr_hw #(.Width(1)) intr_hw_es_entropy_valid (
- .clk_i,
- .rst_ni,
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
.event_intr_i (event_es_entropy_valid),
.reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_entropy_valid.q),
.reg2hw_intr_test_q_i (reg2hw.intr_test.es_entropy_valid.q),
@@ -163,36 +252,22 @@
.intr_o (es_entropy_valid_o)
);
- prim_intr_hw #(.Width(1)) intr_hw_es_rct_failed (
- .clk_i,
- .rst_ni,
- .event_intr_i (event_es_rct_failed),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_rct_failed.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.es_rct_failed.q),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.es_rct_failed.qe),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.es_rct_failed.q),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.es_rct_failed.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.es_rct_failed.d),
- .intr_o (es_rct_failed_o)
+ prim_intr_hw #(.Width(1)) intr_hw_es_health_test_failed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .event_intr_i (event_es_health_test_failed),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_health_test_failed.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.es_health_test_failed.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.es_health_test_failed.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.es_health_test_failed.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.es_health_test_failed.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.es_health_test_failed.d),
+ .intr_o (es_health_test_failed_o)
);
- prim_intr_hw #(.Width(1)) intr_hw_es_apt_failed (
- .clk_i,
- .rst_ni,
- .event_intr_i (event_es_apt_failed),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_apt_failed.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.es_apt_failed.q),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.es_apt_failed.qe),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.es_apt_failed.q),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.es_apt_failed.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.es_apt_failed.d),
- .intr_o (es_apt_failed_o)
- );
-
-
prim_intr_hw #(.Width(1)) intr_hw_es_fifo_err (
- .clk_i,
- .rst_ni,
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
.event_intr_i (event_es_fifo_err),
.reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_fifo_err.q),
.reg2hw_intr_test_q_i (reg2hw.intr_test.es_fifo_err.q),
@@ -207,7 +282,8 @@
// lfsr - a version of a entropy source
//--------------------------------------------
- assign lfsr_enable = es_enable_dig && es_rate_entropy_valid;
+ assign lfsr_incr = es_enable_lfsr && es_rate_entropy_pulse;
+ assign lfsr_incr_dly_d = lfsr_incr;
prim_lfsr #(.LfsrDw(RngBusWidth),
.EntropyDw(RngBusWidth),
@@ -219,7 +295,7 @@
.rst_ni (rst_ni),
.seed_en_i (load_seed),
.seed_i (seed_value),
- .lfsr_en_i (lfsr_enable),
+ .lfsr_en_i (lfsr_incr_dly_q),
.entropy_i ('0),
.state_o (lfsr_value)
);
@@ -227,295 +303,713 @@
// entropy rate limiter
assign es_rate_cntr_d =
- ~es_rate_entropy_valid_en ? 16'h0001 :
+ !es_enable ? 16'h0001 :
(es_rate == '0) ? 16'h0000 :
- es_rate_entropy_valid ? es_rate :
+ es_rate_entropy_pulse ? es_rate :
(es_rate_cntr_q - 1);
- assign es_rate_entropy_valid =
- ~es_rate_entropy_valid_en ? 1'b0 :
+ assign es_rate_entropy_pulse =
+ !es_enable ? 1'b0 :
(es_rate == '0) ? 1'b0 :
(es_rate_cntr_q == 16'h0001);
- assign es_rate_entropy_valid_en = (es_enable_rng & es_rng_src_ok) | es_enable_dig;
-
//--------------------------------------------
// tlul register settings
//--------------------------------------------
// seed register
- assign seed_value = reg2hw.es_seed.q;
+ assign seed_value = reg2hw.seed.q;
// es rate register
- assign es_rate = reg2hw.es_rate.q;
+ assign es_rate = reg2hw.rate.q;
// set the interrupt event when enabled
- assign event_es_entropy_valid = entropy_val_q;
+ assign event_es_entropy_valid = pfifo_swread_not_empty;
// set the interrupt sources
- assign event_es_fifo_err =
- sfifo_esdig_err |
- sfifo_postht_err |
- sfifo_essw_err |
- sfifo_eshw_err;
+ assign event_es_fifo_err = sfifo_esrng_err || sfifo_esfinal_err;
// set the debug status reg
- assign hw2reg.es_fifo_status.dig_src_depth.d = sfifo_esdig_depth;
- assign hw2reg.es_fifo_status.hwif_depth.d = sfifo_eshw_depth;
- assign hw2reg.es_fifo_status.es_depth.d = sfifo_postht_depth;
-
+ assign hw2reg.debug_status.entropy_fifo_depth.d = sfifo_esfinal_depth;
//--------------------------------------------
- // basic checks for RNG bus input
+ // receive in RNG bus input
//--------------------------------------------
- assign rng_bit_en = reg2hw.es_conf.rng_bit_en.q;
- assign rng_bit_sel = reg2hw.es_conf.rng_bit_sel.q;
-
- assign es_rng_src_ok = entropy_src_rng_i.rng_ok;
-
-
- prim_fifo_sync # (.Width(RngBusWidth),.Pass(0),.Depth(4))
- u_prim_fifo_sync_esdig (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .clr_i (sfifo_esdig_clr),
- .wvalid_i (sfifo_esdig_push),
- .wready_o (sfifo_esdig_not_full),
- .wdata_i (sfifo_esdig_wdata),
- .rvalid_o (sfifo_esdig_not_empty),
- .rready_i (sfifo_esdig_pop),
- .rdata_o (sfifo_esdig_rdata),
- .depth_o (sfifo_esdig_depth)
+ prim_fifo_sync # (.Width(RngBusWidth),.Pass(0),.Depth(2))
+ u_prim_fifo_sync_esrng (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (sfifo_esrng_clr),
+ .wvalid_i (sfifo_esrng_push),
+ .wdata_i (sfifo_esrng_wdata),
+ .wready_o (),
+ .rvalid_o (sfifo_esrng_not_empty),
+ .rdata_o (sfifo_esrng_rdata),
+ .rready_i (sfifo_esrng_pop),
+ .depth_o ()
);
// fifo controls
- assign sfifo_esdig_push = es_enable & es_rate_entropy_valid & sfifo_esdig_not_full;
- assign sfifo_esdig_clr = ~es_enable;
- assign sfifo_esdig_wdata = es_enable_dig ? lfsr_value : entropy_src_rng_i.rng_b;
- assign sfifo_esdig_pop = es_enable & sfifo_esdig_not_empty & sfifo_postht_avail;
+ assign sfifo_esrng_push = es_enable_rng && es_rng_src_ok && es_rate_entropy_pulse;
+ assign sfifo_esrng_clr = !es_enable;
+ assign sfifo_esrng_wdata = es_rng_bus;
+ assign sfifo_esrng_pop = es_enable && es_rate_entropy_pulse && sfifo_esrng_not_empty;
- // note: allow input lfsr entropy to drop
+ // note: allow input rng raw entropy to drop
// fifo err
- assign sfifo_esdig_err =
- (sfifo_esdig_pop & ~sfifo_esdig_not_empty );
+ assign sfifo_esrng_err =
+ (sfifo_esrng_pop && !sfifo_esrng_not_empty );
- // pack esbus before moving to a 32 bit bus
- prim_packer # (.InW(RngBusWidth),.OutW(32))
- u_prim_packer_esbus (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .valid_i (packer_esbus_push),
- .data_i (packer_esbus_wdata),
- .mask_i ({RngBusWidth{1'b1}}),
- .ready_o (),
- .valid_o (packer_esbus_valid),
- .data_o (packer_esbus_rdata),
- .mask_o (),
- .ready_i (1'b1),
- .flush_i (packer_esbus_clr),
- .flush_done_o ()
+ // pack esrng bus into signal bit packer
+
+ assign rng_bit_en = reg2hw.conf.rng_bit_en.q;
+ assign rng_bit_sel = reg2hw.conf.rng_bit_sel.q;
+
+ prim_packer_fifo # (.InW(1),.OutW(RngBusWidth))
+ u_prim_packer_fifo_esbit (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_esbit_clr),
+ .wvalid_i (pfifo_esbit_push),
+ .wdata_i (pfifo_esbit_wdata),
+ .wready_o (),
+ .rvalid_o (pfifo_esbit_not_empty),
+ .rdata_o (pfifo_esbit_rdata),
+ .rready_i (pfifo_esbit_pop),
+ .depth_o ()
);
- assign packer_esbus_push = ~rng_bit_en & sfifo_esdig_pop;
- assign packer_esbus_wdata = sfifo_esdig_rdata;
- assign packer_esbus_clr = ~es_enable;
-
- // pack esbit before moving to a 32 bit bus
-
- prim_packer # (.InW(1),.OutW(32))
- u_prim_packer_esbit (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .valid_i (packer_esbit_push),
- .data_i (packer_esbit_wdata),
- .mask_i (1'b1),
- .ready_o (),
- .valid_o (packer_esbit_valid),
- .data_o (packer_esbit_rdata),
- .mask_o (),
- .ready_i (1'b1),
- .flush_i (packer_esbit_clr),
- .flush_done_o ()
- );
-
- assign packer_esbit_push = rng_bit_en & sfifo_esdig_pop;
- assign packer_esbit_clr = ~es_enable;
- assign packer_esbit_wdata =
- (rng_bit_sel == 2'h0) ? sfifo_esdig_rdata[0] :
- (rng_bit_sel == 2'h1) ? sfifo_esdig_rdata[1] :
- (rng_bit_sel == 2'h2) ? sfifo_esdig_rdata[2] :
- sfifo_esdig_rdata[3];
+ assign pfifo_esbit_push = rng_bit_en && sfifo_esrng_pop && es_rate_entropy_pulse;
+ assign pfifo_esbit_clr = !es_enable;
+ assign pfifo_esbit_pop = es_rate_entropy_pulse && pfifo_esbit_not_empty;
+ assign pfifo_esbit_wdata =
+ (rng_bit_sel == 2'h0) ? sfifo_esrng_rdata[0] :
+ (rng_bit_sel == 2'h1) ? sfifo_esrng_rdata[1] :
+ (rng_bit_sel == 2'h2) ? sfifo_esrng_rdata[2] :
+ sfifo_esrng_rdata[3];
- // combine packers
- assign packer_valid = packer_esbus_valid | packer_esbit_valid;
+ // select source for health testing
+ assign health_test_esbus = es_enable_lfsr ? lfsr_value :
+ (es_enable_rng && rng_bit_en) ? pfifo_esbit_rdata :
+ sfifo_esrng_rdata;
- prim_fifo_sync # (.Width(32),.Pass(0),.Depth(EsFifoDepth))
- u_prim_fifo_sync_postht (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .clr_i (sfifo_postht_clr),
- .wvalid_i (sfifo_postht_push),
- .wready_o (sfifo_postht_not_full),
- .wdata_i (sfifo_postht_wdata),
- .rvalid_o (sfifo_postht_not_empty),
- .rready_i (sfifo_postht_pop),
- .rdata_o (sfifo_postht_rdata),
- .depth_o (sfifo_postht_depth)
- );
+ assign health_test_esbus_vld = es_enable_lfsr ? es_rate_entropy_pulse :
+ (es_enable_rng && rng_bit_en) ? pfifo_esbit_pop :
+ sfifo_esrng_pop;
- // fifo controls
- assign sfifo_postht_push = es_enable & packer_valid & (&shtests_passing);
- assign sfifo_postht_clr = ~es_enable;
- assign sfifo_postht_wdata = rng_bit_en ? packer_esbit_rdata : packer_esbus_rdata;
- assign sfifo_postht_pop = es_enable & sfifo_postht_not_empty &
- (fill_sfifo_essw | sfifo_eshw_not_full);
+ assign ht_esbus_vld_dly_d = health_test_esbus_vld;
+ assign ht_esbus_dly_d = health_test_esbus;
+ assign ht_esbus_vld_dly2_d = ht_esbus_vld_dly_q;
- // allow one extra location because of packer
- assign sfifo_postht_avail = (sfifo_postht_depth < (EsFifoDepth-1));
+ assign repcnt_active = !reg2hw.conf.repcnt_disable.q;
+ assign adaptp_active = !reg2hw.conf.adaptp_disable.q;
+ assign bucket_active = !reg2hw.conf.bucket_disable.q;
+ assign markov_active = !reg2hw.conf.markov_disable.q;
- // fifo err
- assign sfifo_postht_err =
- (sfifo_postht_push & ~sfifo_postht_not_full) |
- (sfifo_postht_pop & ~sfifo_postht_not_empty );
+ assign health_test_clr = reg2hw.conf.health_test_clr.q;
+ assign health_test_fips_window = reg2hw.health_test_windows.fips_window.q;
+ assign health_test_bypass_window = reg2hw.health_test_windows.bypass_window.q;
+ assign repcnt_fips_threshold = reg2hw.repcnt_thresholds.fips_repcnt_thresh.q;
+ assign repcnt_bypass_threshold = reg2hw.repcnt_thresholds.bypass_repcnt_thresh.q;
+
+ assign adaptp_hi_fips_threshold = reg2hw.adaptp_hi_thresholds.fips_adaptp_hi_thresh.q;
+ assign adaptp_hi_bypass_threshold = reg2hw.adaptp_hi_thresholds.bypass_adaptp_hi_thresh.q;
+
+ assign adaptp_lo_fips_threshold = reg2hw.adaptp_lo_thresholds.fips_adaptp_lo_thresh.q;
+ assign adaptp_lo_bypass_threshold = reg2hw.adaptp_lo_thresholds.bypass_adaptp_lo_thresh.q;
+
+ assign bucket_fips_threshold = reg2hw.bucket_thresholds.fips_bucket_thresh.q;
+ assign bucket_bypass_threshold = reg2hw.bucket_thresholds.bypass_bucket_thresh.q;
+
+ assign markov_fips_threshold = reg2hw.markov_thresholds.fips_markov_thresh.q;
+ assign markov_bypass_threshold = reg2hw.markov_thresholds.bypass_markov_thresh.q;
+ assign health_test_window = es_bypass_mode ? health_test_bypass_window : health_test_fips_window;
+ assign repcnt_threshold = es_bypass_mode ? repcnt_bypass_threshold : repcnt_fips_threshold;
+ assign adaptp_hi_threshold = es_bypass_mode ? adaptp_hi_bypass_threshold :
+ adaptp_hi_fips_threshold;
+ assign adaptp_lo_threshold = es_bypass_mode ? adaptp_lo_bypass_threshold :
+ adaptp_lo_fips_threshold;
+ assign bucket_threshold = es_bypass_mode ? bucket_bypass_threshold : bucket_fips_threshold;
+ assign markov_threshold = es_bypass_mode ? markov_bypass_threshold : markov_fips_threshold;
+
+ assign event_es_health_test_failed = alert_event;
+
+ assign es_route_to_sw = reg2hw.entropy_control.es_route.q;
+ assign es_bypass_to_sw = reg2hw.entropy_control.es_type.q;
+ assign boot_bypass_disable = reg2hw.conf.boot_bypass_disable.q;
+
+ assign boot_bypass_d =
+ boot_bypass_disable ? 1'b0 :
+ rst_bypass_mode ? 1'b0 :
+ boot_bypass_q;
+
+ assign es_bypass_mode = boot_bypass_q || es_bypass_to_sw;
//--------------------------------------------
- // health tests
+ // repetitive count test
//--------------------------------------------
- genvar ta;
- generate
- for (ta = 0; ta < RngBusWidth; ta = ta+1) begin : gen_test_act
- assign rct_active[ta] = rng_bit_en ? ((rng_bit_sel == ta) & reg2hw.es_conf.rct_en.q) :
- reg2hw.es_conf.rct_en.q;
- assign apt_active[ta] = rng_bit_en ? ((rng_bit_sel == ta) & reg2hw.es_conf.apt_en.q) :
- reg2hw.es_conf.apt_en.q;
- end
- endgenerate
-
- assign rct_max_cnt = reg2hw.es_rct_health.q;
-
- assign apt_max_cnt = reg2hw.es_apt_health.apt_max.q;
- assign apt_window = reg2hw.es_apt_health.apt_win.q;
-
- genvar sh;
- generate
- for (sh = 0; sh < RngBusWidth; sh = sh+1) begin : gen_shtests
- entropy_src_shtests
- u_entropy_src_shtests (
+ entropy_src_repcnt_ht # (.RegWidth(HalfRegWidth),.RngBusWidth(RngBusWidth))
+ u_entropy_src_repcnt_ht
+ (
.clk_i (clk_i),
.rst_ni (rst_ni),
- .entropy_bit_i (sfifo_esdig_rdata[sh]),
- .entropy_bit_vld_i (sfifo_esdig_pop),
- .rct_active_i (rct_active[sh]),
- .rct_max_cnt_i (rct_max_cnt),
- .apt_active_i (apt_active[sh]),
- .apt_max_cnt_i (apt_max_cnt),
- .apt_window_i (apt_window),
- .rct_fail_pls_o (rct_fail_pls[sh]),
- .apt_fail_pls_o (apt_fail_pls[sh]),
- .shtests_passing_o (shtests_passing[sh])
- );
- end
- endgenerate
+ .entropy_bit_i (health_test_esbus),
+ .entropy_bit_vld_i (health_test_esbus_vld),
+ .clear_i (health_test_clr),
+ .active_i (repcnt_active),
+ .thresh_i (repcnt_threshold),
+ .window_i (health_test_window),
+ .test_cnt_o (repcnt_event_cnt),
+ .test_done_pulse_o (health_test_done_pulse),
+ .test_fail_pulse_o (repcnt_fail_pulse)
+ );
- assign event_es_rct_failed = |rct_fail_pls;
- assign event_es_apt_failed = |apt_fail_pls;
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_repcnt_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (repcnt_active),
+ .event_i (repcnt_fail_pulse && !es_bypass_mode),
+ .value_i (repcnt_event_cnt),
+ .value_o (repcnt_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_repcnt_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (repcnt_active),
+ .event_i (repcnt_fail_pulse && es_bypass_mode),
+ .value_i (repcnt_event_cnt),
+ .value_o (repcnt_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_repcnt
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (repcnt_active),
+ .event_i (repcnt_fail_pulse),
+ .value_o (repcnt_total_fails)
+ );
+
+ assign hw2reg.repcnt_hi_watermarks.fips_repcnt_hi_watermark.d = repcnt_event_hwm_fips;
+ assign hw2reg.repcnt_hi_watermarks.bypass_repcnt_hi_watermark.d = repcnt_event_hwm_bypass;
+ assign hw2reg.repcnt_total_fails.d = repcnt_total_fails;
+
+ //--------------------------------------------
+ // adaptive proportion test
+ //--------------------------------------------
+
+ entropy_src_adaptp_ht # (.RegWidth(HalfRegWidth),.RngBusWidth(RngBusWidth))
+ u_entropy_src_adaptp_ht
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .entropy_bit_i (health_test_esbus),
+ .entropy_bit_vld_i (health_test_esbus_vld),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .thresh_hi_i (adaptp_hi_threshold),
+ .thresh_lo_i (adaptp_lo_threshold),
+ .window_i (health_test_window),
+ .test_cnt_o (adaptp_event_cnt),
+ .test_done_pulse_o (), // NC
+ .test_fail_hi_pulse_o(adaptp_hi_fail_pulse),
+ .test_fail_lo_pulse_o(adaptp_lo_fail_pulse)
+ );
+
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_adaptp_hi_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_hi_fail_pulse && !es_bypass_mode),
+ .value_i (adaptp_event_cnt),
+ .value_o (adaptp_hi_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_adaptp_hi_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_hi_fail_pulse && es_bypass_mode),
+ .value_i (adaptp_event_cnt),
+ .value_o (adaptp_hi_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_adaptp_hi
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_hi_fail_pulse),
+ .value_o (adaptp_hi_total_fails)
+ );
+
+
+ assign hw2reg.adaptp_hi_watermarks.fips_adaptp_hi_watermark.d = adaptp_hi_event_hwm_fips;
+ assign hw2reg.adaptp_hi_watermarks.bypass_adaptp_hi_watermark.d = adaptp_hi_event_hwm_bypass;
+ assign hw2reg.adaptp_hi_total_fails.d = adaptp_hi_total_fails;
+
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(0))
+ u_entropy_src_watermark_reg_adaptp_lo_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_lo_fail_pulse && !es_bypass_mode),
+ .value_i (adaptp_event_cnt),
+ .value_o (adaptp_lo_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(0))
+ u_entropy_src_watermark_reg_adaptp_lo_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_lo_fail_pulse && es_bypass_mode),
+ .value_i (adaptp_event_cnt),
+ .value_o (adaptp_lo_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_adaptp_lo
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_lo_fail_pulse),
+ .value_o (adaptp_lo_total_fails)
+ );
+
+ assign hw2reg.adaptp_lo_watermarks.fips_adaptp_lo_watermark.d = adaptp_lo_event_hwm_fips;
+ assign hw2reg.adaptp_lo_watermarks.bypass_adaptp_lo_watermark.d = adaptp_lo_event_hwm_bypass;
+ assign hw2reg.adaptp_lo_total_fails.d = adaptp_lo_total_fails;
//--------------------------------------------
- // fifos for final distribution
+ // bucket test
//--------------------------------------------
- assign fill_sfifo_essw = es_enable & sfifo_essw_not_full & efuse_es_sw_reg_en_i;
+ entropy_src_bucket_ht # (.RegWidth(HalfRegWidth),.RngBusWidth(RngBusWidth))
+ u_entropy_src_bucket_ht
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .entropy_bit_i (health_test_esbus),
+ .entropy_bit_vld_i (health_test_esbus_vld),
+ .clear_i (health_test_clr),
+ .active_i (bucket_active),
+ .thresh_i (bucket_threshold),
+ .window_i (health_test_window),
+ .test_cnt_o (bucket_event_cnt),
+ .test_done_pulse_o (), // NC
+ .test_fail_pulse_o (bucket_fail_pulse)
+ );
- // this fifo feeds the sw register interface
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_bucket_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (bucket_active),
+ .event_i (bucket_fail_pulse && !es_bypass_mode),
+ .value_i (bucket_event_cnt),
+ .value_o (bucket_event_hwm_fips)
+ );
- prim_fifo_sync # (.Width(32),.Pass(0),.Depth(4))
- u_prim_fifo_sync_essw (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .clr_i (sfifo_essw_clr),
- .wvalid_i (sfifo_essw_push),
- .wready_o (sfifo_essw_not_full),
- .wdata_i (sfifo_essw_wdata),
- .rvalid_o (sfifo_essw_not_empty),
- .rready_i (sfifo_essw_pop),
- .rdata_o (sfifo_essw_rdata),
- .depth_o (sfifo_essw_depth)
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_bucket_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (bucket_active),
+ .event_i (bucket_fail_pulse && es_bypass_mode),
+ .value_i (bucket_event_cnt),
+ .value_o (bucket_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_bucket
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (bucket_active),
+ .event_i (bucket_fail_pulse),
+ .value_o (bucket_total_fails)
+ );
+
+ assign hw2reg.bucket_hi_watermarks.fips_bucket_hi_watermark.d = bucket_event_hwm_fips;
+ assign hw2reg.bucket_hi_watermarks.bypass_bucket_hi_watermark.d = bucket_event_hwm_bypass;
+ assign hw2reg.bucket_total_fails.d = bucket_total_fails;
+
+
+ //--------------------------------------------
+ // Markov test
+ //--------------------------------------------
+
+ entropy_src_markov_ht # (.RegWidth(HalfRegWidth),.RngBusWidth(RngBusWidth))
+ u_entropy_src_markov_ht
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .entropy_bit_i (health_test_esbus),
+ .entropy_bit_vld_i (health_test_esbus_vld),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .thresh_i (markov_threshold),
+ .window_i (health_test_window),
+ .test_cnt_o (markov_event_cnt),
+ .test_done_pulse_o (),// NC
+ .test_fail_pulse_o (markov_fail_pulse)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_markov_fips
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .event_i (markov_fail_pulse && !es_bypass_mode),
+ .value_i (markov_event_cnt),
+ .value_o (markov_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg # (.RegWidth(HalfRegWidth),.HighWatermark(1))
+ u_entropy_src_watermark_reg_markov_bypass
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .event_i (markov_fail_pulse && es_bypass_mode),
+ .value_i (markov_event_cnt),
+ .value_o (markov_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg # (.RegWidth(FullRegWidth))
+ u_entropy_src_cntr_reg_markov
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .event_i (markov_fail_pulse),
+ .value_o (markov_total_fails)
+ );
+
+ assign hw2reg.markov_hi_watermarks.fips_markov_hi_watermark.d = markov_event_hwm_fips;
+ assign hw2reg.markov_hi_watermarks.bypass_markov_hi_watermark.d = markov_event_hwm_bypass;
+ assign hw2reg.markov_total_fails.d = markov_total_fails;
+
+ //--------------------------------------------
+ // summary and alert registers
+ //--------------------------------------------
+
+ assign alert_cntrs_clr = health_test_clr || rst_alert_cntr;
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_any_alert_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (any_active),
+ .event_i (any_fail_pulse),
+ .value_o (any_fail_count)
+ );
+
+ assign any_active = repcnt_active || adaptp_active || bucket_active || markov_active;
+ assign any_fail_pulse = repcnt_fail_pulse || adaptp_hi_fail_pulse || adaptp_lo_fail_pulse ||
+ bucket_fail_pulse || markov_fail_pulse;
+
+
+ assign ht_failed_d = sfifo_esfinal_push ? 1'b0 :
+ (any_fail_pulse && health_test_done_pulse) ? 1'b1 :
+ ht_failed_q;
+
+ assign hw2reg.alert_fail_counts.any_fail_count.d = any_fail_count;
+
+ // signal an alert
+ assign alert_threshold = reg2hw.alert_threshold.q;
+
+ assign alert_event = (any_fail_count >= alert_threshold) && (alert_threshold != '0);
+ assign alert_event_o = alert_event;
+
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_repcnt_alert_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (repcnt_active),
+ .event_i (repcnt_fail_pulse),
+ .value_o (repcnt_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.repcnt_fail_count.d = repcnt_fail_count;
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_adaptp_alert_hi_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_hi_fail_pulse),
+ .value_o (adaptp_hi_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.adaptp_hi_fail_count.d = adaptp_hi_fail_count;
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_adaptp_alert_lo_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (adaptp_active),
+ .event_i (adaptp_lo_fail_pulse),
+ .value_o (adaptp_lo_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.adaptp_lo_fail_count.d = adaptp_lo_fail_count;
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_bucket_alert_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (bucket_active),
+ .event_i (bucket_fail_pulse),
+ .value_o (bucket_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.bucket_fail_count.d = bucket_fail_count;
+
+
+ entropy_src_cntr_reg # (.RegWidth(EigthRegWidth))
+ u_entropy_src_cntr_reg_markov_alert_fails
+ (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (markov_active),
+ .event_i (markov_fail_pulse),
+ .value_o (markov_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.markov_fail_count.d = markov_fail_count;
+
+ //--------------------------------------------
+ // pack tested entropy into pre-conditioning packer
+ //--------------------------------------------
+
+ prim_packer_fifo # (.InW(RngBusWidth),.OutW(PostHTWidth))
+ u_prim_packer_fifo_postht (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_postht_clr),
+ .wvalid_i (pfifo_postht_push),
+ .wdata_i (pfifo_postht_wdata),
+ .wready_o (),
+ .rvalid_o (pfifo_postht_not_empty),
+ .rdata_o (pfifo_postht_rdata),
+ .rready_i (pfifo_postht_pop),
+ .depth_o ()
);
- // fifo controls
- assign sfifo_essw_push = es_enable & sfifo_postht_pop & fill_sfifo_essw;
- assign sfifo_essw_clr = ~es_enable;
- assign sfifo_essw_wdata = sfifo_postht_rdata;
- assign sfifo_essw_pop = es_enable & esentropy_rd_pls & efuse_es_sw_reg_en_i;
+ assign pfifo_postht_push = ht_esbus_vld_dly_q;
+ assign pfifo_postht_wdata = ht_esbus_dly_q;
- // fifo err
- assign sfifo_essw_err =
- (sfifo_essw_push & ~sfifo_essw_not_full) |
- (sfifo_essw_pop & ~sfifo_essw_not_empty );
-
- // set the es entropy to the read reg
- assign hw2reg.es_entropy.d = es_enable ? sfifo_essw_rdata : '0;
- assign esentropy_rd_pls = reg2hw.es_entropy.re;
-
- // threshold
- assign es_fifo_thresh = reg2hw.es_thresh.q;
-
- // entropy valid
- assign entropy_val_d = ~es_enable ? 1'b0 : (sfifo_essw_depth >= es_fifo_thresh);
-
- // set the es fifo depth to the read reg
- assign hw2reg.es_fdepthst.d = sfifo_essw_depth;
+ assign pfifo_postht_clr = !es_enable;
+ assign pfifo_postht_pop = ht_esbus_vld_dly2_q && pfifo_postht_not_empty;
+ //--------------------------------------------
+ // TODO: replace standin block with SHA conditioner
+ //--------------------------------------------
- // this fifo feeds the hw bus interface
- prim_fifo_sync # (.Width(32),.Pass(0),.Depth(4))
- u_prim_fifo_sync_eshw (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .clr_i (sfifo_eshw_clr),
- .wvalid_i (sfifo_eshw_push),
- .wready_o (sfifo_eshw_not_full),
- .wdata_i (sfifo_eshw_wdata),
- .rvalid_o (sfifo_eshw_not_empty),
- .rready_i (sfifo_eshw_pop),
- .rdata_o (sfifo_eshw_rdata),
- .depth_o (sfifo_eshw_depth)
+ prim_packer_fifo # (.InW(PostHTWidth),.OutW(SeedLen))
+ u_prim_packer_fifo_cond (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_cond_clr),
+ .wvalid_i (pfifo_cond_push),
+ .wdata_i (pfifo_cond_wdata),
+ .wready_o (),
+ .rvalid_o (pfifo_cond_not_empty),
+ .rdata_o (pfifo_cond_rdata),
+ .rready_i (pfifo_cond_pop),
+ .depth_o ()
);
+ assign pfifo_cond_push = pfifo_postht_pop && !es_bypass_mode;
+ assign pfifo_cond_wdata = pfifo_postht_rdata;
+
+ assign pfifo_cond_clr = !es_enable;
+ assign pfifo_cond_pop = main_stage_pop;
+
+ //--------------------------------------------
+ // bypass SHA conditioner path
+ //--------------------------------------------
+
+ prim_packer_fifo # (.InW(PostHTWidth),.OutW(SeedLen))
+ u_prim_packer_fifo_bypass (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_bypass_clr),
+ .wvalid_i (pfifo_bypass_push),
+ .wdata_i (pfifo_bypass_wdata),
+ .wready_o (),
+ .rvalid_o (pfifo_bypass_not_empty),
+ .rdata_o (pfifo_bypass_rdata),
+ .rready_i (pfifo_bypass_pop),
+ .depth_o ()
+ );
+
+ assign pfifo_bypass_push = pfifo_postht_pop && es_bypass_mode;
+ assign pfifo_bypass_wdata = pfifo_postht_rdata;
+
+ assign pfifo_bypass_clr = !es_enable;
+ assign pfifo_bypass_pop = bypass_stage_pop;
+
+
+// mux to select between fips and bypass mode
+
+ assign final_es_data = es_bypass_mode ? pfifo_bypass_rdata : pfifo_cond_rdata;
+
+
+ //--------------------------------------------
+ // state machine to coordinate fifo flow
+ //--------------------------------------------
+
+ entropy_src_main_sm
+ u_entropy_src_main_sm (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .enable_i (es_enable),
+ .ht_done_pulse_i (health_test_done_pulse),
+ .ht_fail_pulse_i (any_fail_pulse),
+ .postht_not_empty_i (pfifo_postht_not_empty),
+ .rst_alert_cntr_o (rst_alert_cntr),
+ .bypass_mode_i (es_bypass_mode),
+ .rst_bypass_mode_o (rst_bypass_mode),
+ .main_stage_rdy_i (pfifo_cond_not_empty),
+ .bypass_stage_rdy_i (pfifo_bypass_not_empty),
+ .main_stage_pop_o (main_stage_pop),
+ .bypass_stage_pop_o (bypass_stage_pop)
+ );
+
+
+ //--------------------------------------------
+ // send processed entropy to final fifo
+ //--------------------------------------------
+
+ prim_fifo_sync # (.Width(1+SeedLen),.Pass(0),.Depth(EsFifoDepth))
+ u_prim_fifo_sync_esfinal (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (sfifo_esfinal_clr),
+ .wvalid_i (sfifo_esfinal_push),
+ .wready_o (sfifo_esfinal_not_full),
+ .wdata_i (sfifo_esfinal_wdata),
+ .rvalid_o (sfifo_esfinal_not_empty),
+ .rready_i (sfifo_esfinal_pop),
+ .rdata_o (sfifo_esfinal_rdata),
+ .depth_o (sfifo_esfinal_depth)
+ );
+
+ assign fips_compliance = !es_bypass_mode && es_enable_rng && !es_enable_lfsr && !rng_bit_en;
+
// fifo controls
- assign sfifo_eshw_push = es_enable & sfifo_postht_pop & ~fill_sfifo_essw;
- assign sfifo_eshw_clr = ~es_enable;
- assign sfifo_eshw_wdata = sfifo_postht_rdata;
- assign sfifo_eshw_pop = es_enable & entropy_src_hw_if_i.entropy_src_rdy
- & sfifo_eshw_not_empty;
+ assign sfifo_esfinal_push = sfifo_esfinal_not_full &&
+ ((main_stage_pop || bypass_stage_pop) && !ht_failed_q);
+ assign sfifo_esfinal_clr = ~es_enable;
+ assign sfifo_esfinal_wdata = {fips_compliance,final_es_data};
+ assign sfifo_esfinal_pop = es_route_to_sw ? pfifo_swread_not_full :
+ (es_enable && entropy_src_hw_if_i.es_req);
+ assign {esfinal_fips_flag,esfinal_data} = sfifo_esfinal_rdata;
// fifo err
- assign sfifo_eshw_err =
- (sfifo_eshw_push & ~sfifo_eshw_not_full) |
- (sfifo_eshw_pop & ~sfifo_eshw_not_empty );
+ assign sfifo_esfinal_err =
+ (sfifo_esfinal_push && !sfifo_esfinal_not_full) |
+ (sfifo_esfinal_pop && !sfifo_esfinal_not_empty );
// drive out hw interface
- assign entropy_src_hw_if_o.entropy_src_vld = sfifo_eshw_not_empty;
- assign entropy_src_hw_if_o.entropy_src_bits = sfifo_eshw_rdata;
+ assign entropy_src_hw_if_o.es_ack = sfifo_esfinal_not_empty && !es_route_to_sw;
+ assign entropy_src_hw_if_o.es_bits = esfinal_data;
+ assign entropy_src_hw_if_o.es_fips = esfinal_fips_flag;
//--------------------------------------------
+ // software es read path
+ //--------------------------------------------
+
+ prim_packer_fifo # (.InW(SeedLen),.OutW(FullRegWidth))
+ u_prim_packer_fifo_swread (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clr_i (pfifo_swread_clr),
+ .wvalid_i (pfifo_swread_push),
+ .wdata_i (pfifo_swread_wdata),
+ .wready_o (pfifo_swread_not_full),
+ .rvalid_o (pfifo_swread_not_empty),
+ .rdata_o (pfifo_swread_rdata),
+ .rready_i (pfifo_swread_pop),
+ .depth_o ()
+ );
+
+ assign pfifo_swread_push = sfifo_esfinal_pop;
+ assign pfifo_swread_wdata = esfinal_data;
+
+ assign pfifo_swread_clr = !es_enable;
+ assign pfifo_swread_pop = es_enable && sw_es_rd_pulse;
+
+ // set the es entropy to the read reg
+ assign hw2reg.entropy_data.d = es_enable ? pfifo_swread_rdata : '0;
+ assign sw_es_rd_pulse = efuse_es_sw_reg_en_i && reg2hw.entropy_data.re;
+ //--------------------------------------------
// diag settings
//--------------------------------------------
- assign hw2reg.es_fifo_status.diag.d =
- reg2hw.es_regen.q &
- (®2hw.es_entropy.q);
+ assign hw2reg.debug_status.diag.d =
+ reg2hw.regen.q &&
+ (®2hw.entropy_data.q);
endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
new file mode 100755
index 0000000..5e4ea67
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
@@ -0,0 +1,96 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src main state machine module
+//
+// determines when new entropy is ready to be forwarded
+
+module entropy_src_main_sm (
+ input logic clk_i,
+ input logic rst_ni,
+
+ input logic enable_i,
+ input logic ht_done_pulse_i,
+ input logic ht_fail_pulse_i,
+ input logic postht_not_empty_i,
+ output logic rst_alert_cntr_o,
+ input logic bypass_mode_i,
+ output logic rst_bypass_mode_o,
+ input logic main_stage_rdy_i,
+ input logic bypass_stage_rdy_i,
+ output logic main_stage_pop_o,
+ output logic bypass_stage_pop_o
+);
+
+ // TODO: consider hamming-distance expansion of state encoding
+ typedef enum logic [2:0] {
+ IDLE = 3'h0, // idle
+ HTDP = 3'h1, // wait for health test done pulse
+ PNMT = 3'h2, // wait for post health test packer not empty state
+ MODE = 3'h3, // determine what mode the flow is in
+ BYPS = 3'h4, // in bypass mode
+ NORM = 3'h5 // in normal mode
+ } state_e;
+
+ state_e state_q, state_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ state_q <= IDLE;
+ end else begin
+ state_q <= state_d;
+ end
+
+ always_comb begin
+ state_d = state_q;
+ rst_bypass_mode_o = 1'b0;
+ rst_alert_cntr_o = 1'b0;
+ main_stage_pop_o = 1'b0;
+ bypass_stage_pop_o = 1'b0;
+ unique case (state_q)
+ IDLE: begin
+ if (enable_i) begin
+ state_d = HTDP;
+ end
+ end
+ HTDP: begin
+ if (ht_done_pulse_i) begin
+ if (ht_fail_pulse_i) begin
+ state_d = IDLE;
+ end else begin
+ state_d = PNMT;
+ end
+ end
+ end
+ PNMT: begin
+ rst_alert_cntr_o = 1'b1;
+ if (postht_not_empty_i) begin
+ state_d = MODE;
+ end
+ end
+ MODE: begin
+ if (bypass_mode_i) begin
+ state_d = BYPS;
+ end else begin
+ state_d = NORM;
+ end
+ end
+ BYPS: begin
+ if (bypass_stage_rdy_i) begin
+ rst_bypass_mode_o = 1'b1;
+ bypass_stage_pop_o = 1'b1;
+ state_d = IDLE;
+ end
+ end
+ NORM: begin
+ if (main_stage_rdy_i) begin
+ main_stage_pop_o = 1'b1;
+ state_d = IDLE;
+ end
+ end
+ default: state_d = IDLE;
+ endcase
+ end
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv
new file mode 100755
index 0000000..f8b8f3e
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv
@@ -0,0 +1,111 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src Markov health test module
+//
+
+module entropy_src_markov_ht #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned RngBusWidth = 4
+) (
+ input clk_i,
+ input rst_ni,
+
+ // ins req interface
+ input logic [RngBusWidth-1:0] entropy_bit_i,
+ input logic entropy_bit_vld_i,
+ input logic clear_i,
+ input logic active_i,
+ input logic [RegWidth-1:0] thresh_i,
+ input logic [RegWidth-1:0] window_i,
+ output logic [RegWidth-1:0] test_cnt_o,
+ output logic test_done_pulse_o,
+ output logic test_fail_pulse_o
+);
+
+ // signals
+ logic window_cntr_wrap;
+ logic [RngBusWidth-1:0] samples_no_match_pulse;
+ logic [RngBusWidth-1:0] pair_cnt_fail;
+
+ // flops
+ logic [RngBusWidth-1:0] prev_sample_q, prev_sample_d;
+ logic [RegWidth-1:0] pair_cntr_q[RngBusWidth], pair_cntr_d[RngBusWidth];
+ logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
+ logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ prev_sample_q <= '0;
+ pair_cntr_q <= {{RegWidth{1'b0}},{RegWidth{1'b0}},
+ {RegWidth{1'b0}},{RegWidth{1'b0}}};
+ window_cntr_q <= '0;
+ test_cnt_q <= '0;
+ end else begin
+ prev_sample_q <= prev_sample_d;
+ pair_cntr_q <= pair_cntr_d;
+ window_cntr_q <= window_cntr_d;
+ test_cnt_q <= test_cnt_d;
+ end
+
+
+ // Markov Test
+ //
+ // Test operation
+ // This test will look at pairs of bit levels per bitstream. A counter for
+ // stream will only count when the pair equals 0b01 or 0b10.
+
+
+ genvar sh;
+ generate
+ for (sh = 0; sh < RngBusWidth; sh = sh+1) begin : gen_cntrs
+
+ // bit sampler
+ assign prev_sample_d[sh] =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? entropy_bit_i[sh] :
+ prev_sample_q[sh];
+
+ // pair check
+ assign samples_no_match_pulse[sh] = entropy_bit_vld_i && window_cntr_q[0] &&
+ (prev_sample_q[sh] == !entropy_bit_i[sh]);
+
+ // pair counter
+ assign pair_cntr_d[sh] =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ samples_no_match_pulse[sh] ? (pair_cntr_q[sh]+1) :
+ pair_cntr_q[sh];
+
+ assign pair_cnt_fail[sh] = (pair_cntr_q[sh] >= thresh_i);
+
+ end
+ endgenerate
+
+
+ // Window wrap condition
+ assign window_cntr_wrap = (window_cntr_q == window_i);
+
+ // Window counter
+ assign window_cntr_d =
+ clear_i ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (window_cntr_q+1) :
+ window_cntr_q;
+
+ // Test event counter
+ assign test_cnt_d =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i && (|pair_cnt_fail) ? (test_cnt_q+1) :
+ test_cnt_q;
+
+ // the pulses will be only one clock in length
+ assign test_fail_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > '0);
+ assign test_done_pulse_o = window_cntr_wrap;
+ assign test_cnt_o = test_cnt_q;
+
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_pkg.sv
index cd45ab0..afa3320 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_pkg.sv
@@ -11,12 +11,13 @@
//-------------------------
typedef struct packed {
- logic entropy_src_vld;
- logic [31:0] entropy_src_bits;
+ logic es_ack;
+ logic [383:0] es_bits;
+ logic es_fips;
} entropy_src_hw_if_rsp_t;
typedef struct packed {
- logic entropy_src_rdy;
+ logic es_req;
} entropy_src_hw_if_req_t;
typedef struct packed {
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
index b4c9813..12116f2 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -8,6 +8,7 @@
// Param list
parameter int EsFifoDepth = 32;
+ parameter int NumAlerts = 1;
////////////////////////////
// Typedefs for registers //
@@ -18,10 +19,7 @@
} es_entropy_valid;
struct packed {
logic q;
- } es_rct_failed;
- struct packed {
- logic q;
- } es_apt_failed;
+ } es_health_test_failed;
struct packed {
logic q;
} es_fifo_err;
@@ -33,10 +31,7 @@
} es_entropy_valid;
struct packed {
logic q;
- } es_rct_failed;
- struct packed {
- logic q;
- } es_apt_failed;
+ } es_health_test_failed;
struct packed {
logic q;
} es_fifo_err;
@@ -50,11 +45,7 @@
struct packed {
logic q;
logic qe;
- } es_rct_failed;
- struct packed {
- logic q;
- logic qe;
- } es_apt_failed;
+ } es_health_test_failed;
struct packed {
logic q;
logic qe;
@@ -63,7 +54,7 @@
typedef struct packed {
logic q;
- } entropy_src_reg2hw_es_regen_reg_t;
+ } entropy_src_reg2hw_regen_reg_t;
typedef struct packed {
struct packed {
@@ -71,50 +62,109 @@
} enable;
struct packed {
logic q;
- } rng_src_en;
+ } boot_bypass_disable;
struct packed {
logic q;
- } rct_en;
+ } repcnt_disable;
struct packed {
logic q;
- } apt_en;
+ } adaptp_disable;
+ struct packed {
+ logic q;
+ } bucket_disable;
+ struct packed {
+ logic q;
+ } markov_disable;
+ struct packed {
+ logic q;
+ } health_test_clr;
struct packed {
logic q;
} rng_bit_en;
struct packed {
logic [1:0] q;
} rng_bit_sel;
- } entropy_src_reg2hw_es_conf_reg_t;
+ } entropy_src_reg2hw_conf_reg_t;
typedef struct packed {
logic [15:0] q;
- } entropy_src_reg2hw_es_rct_health_reg_t;
+ } entropy_src_reg2hw_rate_reg_t;
typedef struct packed {
struct packed {
- logic [15:0] q;
- } apt_max;
+ logic q;
+ } es_route;
struct packed {
- logic [15:0] q;
- } apt_win;
- } entropy_src_reg2hw_es_apt_health_reg_t;
+ logic q;
+ } es_type;
+ } entropy_src_reg2hw_entropy_control_reg_t;
typedef struct packed {
logic [31:0] q;
logic re;
- } entropy_src_reg2hw_es_entropy_reg_t;
+ } entropy_src_reg2hw_entropy_data_reg_t;
typedef struct packed {
- logic [2:0] q;
- } entropy_src_reg2hw_es_thresh_reg_t;
+ struct packed {
+ logic [15:0] q;
+ } fips_window;
+ struct packed {
+ logic [15:0] q;
+ } bypass_window;
+ } entropy_src_reg2hw_health_test_windows_reg_t;
typedef struct packed {
- logic [15:0] q;
- } entropy_src_reg2hw_es_rate_reg_t;
+ struct packed {
+ logic [15:0] q;
+ } fips_repcnt_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_repcnt_thresh;
+ } entropy_src_reg2hw_repcnt_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ } fips_adaptp_hi_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_adaptp_hi_thresh;
+ } entropy_src_reg2hw_adaptp_hi_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ } fips_adaptp_lo_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_adaptp_lo_thresh;
+ } entropy_src_reg2hw_adaptp_lo_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ } fips_bucket_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_bucket_thresh;
+ } entropy_src_reg2hw_bucket_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ } fips_markov_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_markov_thresh;
+ } entropy_src_reg2hw_markov_thresholds_reg_t;
typedef struct packed {
logic [3:0] q;
- } entropy_src_reg2hw_es_seed_reg_t;
+ } entropy_src_reg2hw_alert_threshold_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } entropy_src_reg2hw_seed_reg_t;
typedef struct packed {
@@ -125,11 +175,7 @@
struct packed {
logic d;
logic de;
- } es_rct_failed;
- struct packed {
- logic d;
- logic de;
- } es_apt_failed;
+ } es_health_test_failed;
struct packed {
logic d;
logic de;
@@ -138,70 +184,176 @@
typedef struct packed {
logic [31:0] d;
- } entropy_src_hw2reg_es_entropy_reg_t;
+ } entropy_src_hw2reg_entropy_data_reg_t;
typedef struct packed {
struct packed {
- logic [2:0] d;
- } dig_src_depth;
+ logic [15:0] d;
+ } fips_repcnt_hi_watermark;
struct packed {
- logic [2:0] d;
- } hwif_depth;
+ logic [15:0] d;
+ } bypass_repcnt_hi_watermark;
+ } entropy_src_hw2reg_repcnt_hi_watermarks_reg_t;
+
+ typedef struct packed {
struct packed {
- logic [4:0] d;
- } es_depth;
+ logic [15:0] d;
+ } fips_adaptp_hi_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_adaptp_hi_watermark;
+ } entropy_src_hw2reg_adaptp_hi_watermarks_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] d;
+ } fips_adaptp_lo_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_adaptp_lo_watermark;
+ } entropy_src_hw2reg_adaptp_lo_watermarks_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] d;
+ } fips_bucket_hi_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_bucket_hi_watermark;
+ } entropy_src_hw2reg_bucket_hi_watermarks_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] d;
+ } fips_markov_hi_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_markov_hi_watermark;
+ } entropy_src_hw2reg_markov_hi_watermarks_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_repcnt_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_adaptp_hi_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_adaptp_lo_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_bucket_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_markov_total_fails_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] d;
+ } any_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } repcnt_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } adaptp_hi_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } adaptp_lo_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } bucket_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } markov_fail_count;
+ } entropy_src_hw2reg_alert_fail_counts_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [1:0] d;
+ } entropy_fifo_depth;
struct packed {
logic d;
} diag;
- } entropy_src_hw2reg_es_fifo_status_reg_t;
-
- typedef struct packed {
- logic [2:0] d;
- } entropy_src_hw2reg_es_fdepthst_reg_t;
+ } entropy_src_hw2reg_debug_status_reg_t;
///////////////////////////////////////
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- entropy_src_reg2hw_intr_state_reg_t intr_state; // [128:125]
- entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [124:121]
- entropy_src_reg2hw_intr_test_reg_t intr_test; // [120:113]
- entropy_src_reg2hw_es_regen_reg_t es_regen; // [112:112]
- entropy_src_reg2hw_es_conf_reg_t es_conf; // [111:104]
- entropy_src_reg2hw_es_rct_health_reg_t es_rct_health; // [103:88]
- entropy_src_reg2hw_es_apt_health_reg_t es_apt_health; // [87:56]
- entropy_src_reg2hw_es_entropy_reg_t es_entropy; // [55:23]
- entropy_src_reg2hw_es_thresh_reg_t es_thresh; // [22:20]
- entropy_src_reg2hw_es_rate_reg_t es_rate; // [19:4]
- entropy_src_reg2hw_es_seed_reg_t es_seed; // [3:0]
+ entropy_src_reg2hw_intr_state_reg_t intr_state; // [274:272]
+ entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [271:269]
+ entropy_src_reg2hw_intr_test_reg_t intr_test; // [268:263]
+ entropy_src_reg2hw_regen_reg_t regen; // [262:262]
+ entropy_src_reg2hw_conf_reg_t conf; // [261:251]
+ entropy_src_reg2hw_rate_reg_t rate; // [250:235]
+ entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [234:233]
+ entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [232:200]
+ entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [199:168]
+ entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [167:136]
+ entropy_src_reg2hw_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [135:104]
+ entropy_src_reg2hw_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [103:72]
+ entropy_src_reg2hw_bucket_thresholds_reg_t bucket_thresholds; // [71:40]
+ entropy_src_reg2hw_markov_thresholds_reg_t markov_thresholds; // [39:8]
+ entropy_src_reg2hw_alert_threshold_reg_t alert_threshold; // [7:4]
+ entropy_src_reg2hw_seed_reg_t seed; // [3:0]
} entropy_src_reg2hw_t;
///////////////////////////////////////
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- entropy_src_hw2reg_intr_state_reg_t intr_state; // [54:51]
- entropy_src_hw2reg_es_entropy_reg_t es_entropy; // [50:18]
- entropy_src_hw2reg_es_fifo_status_reg_t es_fifo_status; // [17:18]
- entropy_src_hw2reg_es_fdepthst_reg_t es_fdepthst; // [17:18]
+ entropy_src_hw2reg_intr_state_reg_t intr_state; // [384:382]
+ entropy_src_hw2reg_entropy_data_reg_t entropy_data; // [381:349]
+ entropy_src_hw2reg_repcnt_hi_watermarks_reg_t repcnt_hi_watermarks; // [348:349]
+ entropy_src_hw2reg_adaptp_hi_watermarks_reg_t adaptp_hi_watermarks; // [348:349]
+ entropy_src_hw2reg_adaptp_lo_watermarks_reg_t adaptp_lo_watermarks; // [348:349]
+ entropy_src_hw2reg_bucket_hi_watermarks_reg_t bucket_hi_watermarks; // [348:349]
+ entropy_src_hw2reg_markov_hi_watermarks_reg_t markov_hi_watermarks; // [348:349]
+ entropy_src_hw2reg_repcnt_total_fails_reg_t repcnt_total_fails; // [348:349]
+ entropy_src_hw2reg_adaptp_hi_total_fails_reg_t adaptp_hi_total_fails; // [348:349]
+ entropy_src_hw2reg_adaptp_lo_total_fails_reg_t adaptp_lo_total_fails; // [348:349]
+ entropy_src_hw2reg_bucket_total_fails_reg_t bucket_total_fails; // [348:349]
+ entropy_src_hw2reg_markov_total_fails_reg_t markov_total_fails; // [348:349]
+ entropy_src_hw2reg_alert_fail_counts_reg_t alert_fail_counts; // [348:349]
+ entropy_src_hw2reg_debug_status_reg_t debug_status; // [348:349]
} entropy_src_hw2reg_t;
// Register Address
- parameter logic [5:0] ENTROPY_SRC_INTR_STATE_OFFSET = 6'h 0;
- parameter logic [5:0] ENTROPY_SRC_INTR_ENABLE_OFFSET = 6'h 4;
- parameter logic [5:0] ENTROPY_SRC_INTR_TEST_OFFSET = 6'h 8;
- parameter logic [5:0] ENTROPY_SRC_ES_REGEN_OFFSET = 6'h c;
- parameter logic [5:0] ENTROPY_SRC_ES_REV_OFFSET = 6'h 10;
- parameter logic [5:0] ENTROPY_SRC_ES_CONF_OFFSET = 6'h 14;
- parameter logic [5:0] ENTROPY_SRC_ES_RCT_HEALTH_OFFSET = 6'h 18;
- parameter logic [5:0] ENTROPY_SRC_ES_APT_HEALTH_OFFSET = 6'h 1c;
- parameter logic [5:0] ENTROPY_SRC_ES_ENTROPY_OFFSET = 6'h 20;
- parameter logic [5:0] ENTROPY_SRC_ES_FIFO_STATUS_OFFSET = 6'h 24;
- parameter logic [5:0] ENTROPY_SRC_ES_FDEPTHST_OFFSET = 6'h 28;
- parameter logic [5:0] ENTROPY_SRC_ES_THRESH_OFFSET = 6'h 2c;
- parameter logic [5:0] ENTROPY_SRC_ES_RATE_OFFSET = 6'h 30;
- parameter logic [5:0] ENTROPY_SRC_ES_SEED_OFFSET = 6'h 34;
+ parameter logic [6:0] ENTROPY_SRC_INTR_STATE_OFFSET = 7'h 0;
+ parameter logic [6:0] ENTROPY_SRC_INTR_ENABLE_OFFSET = 7'h 4;
+ parameter logic [6:0] ENTROPY_SRC_INTR_TEST_OFFSET = 7'h 8;
+ parameter logic [6:0] ENTROPY_SRC_REGEN_OFFSET = 7'h c;
+ parameter logic [6:0] ENTROPY_SRC_REV_OFFSET = 7'h 10;
+ parameter logic [6:0] ENTROPY_SRC_CONF_OFFSET = 7'h 14;
+ parameter logic [6:0] ENTROPY_SRC_RATE_OFFSET = 7'h 18;
+ parameter logic [6:0] ENTROPY_SRC_ENTROPY_CONTROL_OFFSET = 7'h 1c;
+ parameter logic [6:0] ENTROPY_SRC_ENTROPY_DATA_OFFSET = 7'h 20;
+ parameter logic [6:0] ENTROPY_SRC_HEALTH_TEST_WINDOWS_OFFSET = 7'h 24;
+ parameter logic [6:0] ENTROPY_SRC_REPCNT_THRESHOLDS_OFFSET = 7'h 28;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET = 7'h 2c;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET = 7'h 30;
+ parameter logic [6:0] ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET = 7'h 34;
+ parameter logic [6:0] ENTROPY_SRC_MARKOV_THRESHOLDS_OFFSET = 7'h 38;
+ parameter logic [6:0] ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET = 7'h 3c;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET = 7'h 40;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET = 7'h 44;
+ parameter logic [6:0] ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET = 7'h 48;
+ parameter logic [6:0] ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET = 7'h 4c;
+ parameter logic [6:0] ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET = 7'h 50;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET = 7'h 54;
+ parameter logic [6:0] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET = 7'h 58;
+ parameter logic [6:0] ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET = 7'h 5c;
+ parameter logic [6:0] ENTROPY_SRC_MARKOV_TOTAL_FAILS_OFFSET = 7'h 60;
+ parameter logic [6:0] ENTROPY_SRC_ALERT_THRESHOLD_OFFSET = 7'h 64;
+ parameter logic [6:0] ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET = 7'h 68;
+ parameter logic [6:0] ENTROPY_SRC_DEBUG_STATUS_OFFSET = 7'h 6c;
+ parameter logic [6:0] ENTROPY_SRC_SEED_OFFSET = 7'h 70;
// Register Index
@@ -209,35 +361,65 @@
ENTROPY_SRC_INTR_STATE,
ENTROPY_SRC_INTR_ENABLE,
ENTROPY_SRC_INTR_TEST,
- ENTROPY_SRC_ES_REGEN,
- ENTROPY_SRC_ES_REV,
- ENTROPY_SRC_ES_CONF,
- ENTROPY_SRC_ES_RCT_HEALTH,
- ENTROPY_SRC_ES_APT_HEALTH,
- ENTROPY_SRC_ES_ENTROPY,
- ENTROPY_SRC_ES_FIFO_STATUS,
- ENTROPY_SRC_ES_FDEPTHST,
- ENTROPY_SRC_ES_THRESH,
- ENTROPY_SRC_ES_RATE,
- ENTROPY_SRC_ES_SEED
+ ENTROPY_SRC_REGEN,
+ ENTROPY_SRC_REV,
+ ENTROPY_SRC_CONF,
+ ENTROPY_SRC_RATE,
+ ENTROPY_SRC_ENTROPY_CONTROL,
+ ENTROPY_SRC_ENTROPY_DATA,
+ ENTROPY_SRC_HEALTH_TEST_WINDOWS,
+ ENTROPY_SRC_REPCNT_THRESHOLDS,
+ ENTROPY_SRC_ADAPTP_HI_THRESHOLDS,
+ ENTROPY_SRC_ADAPTP_LO_THRESHOLDS,
+ ENTROPY_SRC_BUCKET_THRESHOLDS,
+ ENTROPY_SRC_MARKOV_THRESHOLDS,
+ ENTROPY_SRC_REPCNT_HI_WATERMARKS,
+ ENTROPY_SRC_ADAPTP_HI_WATERMARKS,
+ ENTROPY_SRC_ADAPTP_LO_WATERMARKS,
+ ENTROPY_SRC_BUCKET_HI_WATERMARKS,
+ ENTROPY_SRC_MARKOV_HI_WATERMARKS,
+ ENTROPY_SRC_REPCNT_TOTAL_FAILS,
+ ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS,
+ ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS,
+ ENTROPY_SRC_BUCKET_TOTAL_FAILS,
+ ENTROPY_SRC_MARKOV_TOTAL_FAILS,
+ ENTROPY_SRC_ALERT_THRESHOLD,
+ ENTROPY_SRC_ALERT_FAIL_COUNTS,
+ ENTROPY_SRC_DEBUG_STATUS,
+ ENTROPY_SRC_SEED
} entropy_src_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ENTROPY_SRC_PERMIT [14] = '{
+ parameter logic [3:0] ENTROPY_SRC_PERMIT [29] = '{
4'b 0001, // index[ 0] ENTROPY_SRC_INTR_STATE
4'b 0001, // index[ 1] ENTROPY_SRC_INTR_ENABLE
4'b 0001, // index[ 2] ENTROPY_SRC_INTR_TEST
- 4'b 0001, // index[ 3] ENTROPY_SRC_ES_REGEN
- 4'b 0111, // index[ 4] ENTROPY_SRC_ES_REV
- 4'b 0011, // index[ 5] ENTROPY_SRC_ES_CONF
- 4'b 0011, // index[ 6] ENTROPY_SRC_ES_RCT_HEALTH
- 4'b 1111, // index[ 7] ENTROPY_SRC_ES_APT_HEALTH
- 4'b 1111, // index[ 8] ENTROPY_SRC_ES_ENTROPY
- 4'b 1111, // index[ 9] ENTROPY_SRC_ES_FIFO_STATUS
- 4'b 0001, // index[10] ENTROPY_SRC_ES_FDEPTHST
- 4'b 0001, // index[11] ENTROPY_SRC_ES_THRESH
- 4'b 0011, // index[12] ENTROPY_SRC_ES_RATE
- 4'b 0001 // index[13] ENTROPY_SRC_ES_SEED
+ 4'b 0001, // index[ 3] ENTROPY_SRC_REGEN
+ 4'b 0111, // index[ 4] ENTROPY_SRC_REV
+ 4'b 0011, // index[ 5] ENTROPY_SRC_CONF
+ 4'b 0011, // index[ 6] ENTROPY_SRC_RATE
+ 4'b 0001, // index[ 7] ENTROPY_SRC_ENTROPY_CONTROL
+ 4'b 1111, // index[ 8] ENTROPY_SRC_ENTROPY_DATA
+ 4'b 1111, // index[ 9] ENTROPY_SRC_HEALTH_TEST_WINDOWS
+ 4'b 1111, // index[10] ENTROPY_SRC_REPCNT_THRESHOLDS
+ 4'b 1111, // index[11] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS
+ 4'b 1111, // index[12] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS
+ 4'b 1111, // index[13] ENTROPY_SRC_BUCKET_THRESHOLDS
+ 4'b 1111, // index[14] ENTROPY_SRC_MARKOV_THRESHOLDS
+ 4'b 1111, // index[15] ENTROPY_SRC_REPCNT_HI_WATERMARKS
+ 4'b 1111, // index[16] ENTROPY_SRC_ADAPTP_HI_WATERMARKS
+ 4'b 1111, // index[17] ENTROPY_SRC_ADAPTP_LO_WATERMARKS
+ 4'b 1111, // index[18] ENTROPY_SRC_BUCKET_HI_WATERMARKS
+ 4'b 1111, // index[19] ENTROPY_SRC_MARKOV_HI_WATERMARKS
+ 4'b 1111, // index[20] ENTROPY_SRC_REPCNT_TOTAL_FAILS
+ 4'b 1111, // index[21] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS
+ 4'b 1111, // index[22] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS
+ 4'b 1111, // index[23] ENTROPY_SRC_BUCKET_TOTAL_FAILS
+ 4'b 1111, // index[24] ENTROPY_SRC_MARKOV_TOTAL_FAILS
+ 4'b 0001, // index[25] ENTROPY_SRC_ALERT_THRESHOLD
+ 4'b 0111, // index[26] ENTROPY_SRC_ALERT_FAIL_COUNTS
+ 4'b 1111, // index[27] ENTROPY_SRC_DEBUG_STATUS
+ 4'b 0001 // index[28] ENTROPY_SRC_SEED
};
endpackage
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
index bd27cc3..a49f03d 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
@@ -23,7 +23,7 @@
import entropy_src_reg_pkg::* ;
- localparam int AW = 6;
+ localparam int AW = 7;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
@@ -74,89 +74,159 @@
logic intr_state_es_entropy_valid_qs;
logic intr_state_es_entropy_valid_wd;
logic intr_state_es_entropy_valid_we;
- logic intr_state_es_rct_failed_qs;
- logic intr_state_es_rct_failed_wd;
- logic intr_state_es_rct_failed_we;
- logic intr_state_es_apt_failed_qs;
- logic intr_state_es_apt_failed_wd;
- logic intr_state_es_apt_failed_we;
+ logic intr_state_es_health_test_failed_qs;
+ logic intr_state_es_health_test_failed_wd;
+ logic intr_state_es_health_test_failed_we;
logic intr_state_es_fifo_err_qs;
logic intr_state_es_fifo_err_wd;
logic intr_state_es_fifo_err_we;
logic intr_enable_es_entropy_valid_qs;
logic intr_enable_es_entropy_valid_wd;
logic intr_enable_es_entropy_valid_we;
- logic intr_enable_es_rct_failed_qs;
- logic intr_enable_es_rct_failed_wd;
- logic intr_enable_es_rct_failed_we;
- logic intr_enable_es_apt_failed_qs;
- logic intr_enable_es_apt_failed_wd;
- logic intr_enable_es_apt_failed_we;
+ logic intr_enable_es_health_test_failed_qs;
+ logic intr_enable_es_health_test_failed_wd;
+ logic intr_enable_es_health_test_failed_we;
logic intr_enable_es_fifo_err_qs;
logic intr_enable_es_fifo_err_wd;
logic intr_enable_es_fifo_err_we;
logic intr_test_es_entropy_valid_wd;
logic intr_test_es_entropy_valid_we;
- logic intr_test_es_rct_failed_wd;
- logic intr_test_es_rct_failed_we;
- logic intr_test_es_apt_failed_wd;
- logic intr_test_es_apt_failed_we;
+ logic intr_test_es_health_test_failed_wd;
+ logic intr_test_es_health_test_failed_we;
logic intr_test_es_fifo_err_wd;
logic intr_test_es_fifo_err_we;
- logic es_regen_qs;
- logic es_regen_wd;
- logic es_regen_we;
- logic [7:0] es_rev_abi_revision_qs;
- logic [7:0] es_rev_hw_revision_qs;
- logic [7:0] es_rev_chip_type_qs;
- logic [1:0] es_conf_enable_qs;
- logic [1:0] es_conf_enable_wd;
- logic es_conf_enable_we;
- logic es_conf_rng_src_en_qs;
- logic es_conf_rng_src_en_wd;
- logic es_conf_rng_src_en_we;
- logic es_conf_rct_en_qs;
- logic es_conf_rct_en_wd;
- logic es_conf_rct_en_we;
- logic es_conf_apt_en_qs;
- logic es_conf_apt_en_wd;
- logic es_conf_apt_en_we;
- logic es_conf_rng_bit_en_qs;
- logic es_conf_rng_bit_en_wd;
- logic es_conf_rng_bit_en_we;
- logic [1:0] es_conf_rng_bit_sel_qs;
- logic [1:0] es_conf_rng_bit_sel_wd;
- logic es_conf_rng_bit_sel_we;
- logic [15:0] es_rct_health_qs;
- logic [15:0] es_rct_health_wd;
- logic es_rct_health_we;
- logic [15:0] es_apt_health_apt_max_qs;
- logic [15:0] es_apt_health_apt_max_wd;
- logic es_apt_health_apt_max_we;
- logic [15:0] es_apt_health_apt_win_qs;
- logic [15:0] es_apt_health_apt_win_wd;
- logic es_apt_health_apt_win_we;
- logic [31:0] es_entropy_qs;
- logic es_entropy_re;
- logic [2:0] es_fifo_status_dig_src_depth_qs;
- logic es_fifo_status_dig_src_depth_re;
- logic [2:0] es_fifo_status_hwif_depth_qs;
- logic es_fifo_status_hwif_depth_re;
- logic [4:0] es_fifo_status_es_depth_qs;
- logic es_fifo_status_es_depth_re;
- logic es_fifo_status_diag_qs;
- logic es_fifo_status_diag_re;
- logic [2:0] es_fdepthst_qs;
- logic es_fdepthst_re;
- logic [2:0] es_thresh_qs;
- logic [2:0] es_thresh_wd;
- logic es_thresh_we;
- logic [15:0] es_rate_qs;
- logic [15:0] es_rate_wd;
- logic es_rate_we;
- logic [3:0] es_seed_qs;
- logic [3:0] es_seed_wd;
- logic es_seed_we;
+ logic regen_qs;
+ logic regen_wd;
+ logic regen_we;
+ logic [7:0] rev_abi_revision_qs;
+ logic [7:0] rev_hw_revision_qs;
+ logic [7:0] rev_chip_type_qs;
+ logic [1:0] conf_enable_qs;
+ logic [1:0] conf_enable_wd;
+ logic conf_enable_we;
+ logic conf_boot_bypass_disable_qs;
+ logic conf_boot_bypass_disable_wd;
+ logic conf_boot_bypass_disable_we;
+ logic conf_repcnt_disable_qs;
+ logic conf_repcnt_disable_wd;
+ logic conf_repcnt_disable_we;
+ logic conf_adaptp_disable_qs;
+ logic conf_adaptp_disable_wd;
+ logic conf_adaptp_disable_we;
+ logic conf_bucket_disable_qs;
+ logic conf_bucket_disable_wd;
+ logic conf_bucket_disable_we;
+ logic conf_markov_disable_qs;
+ logic conf_markov_disable_wd;
+ logic conf_markov_disable_we;
+ logic conf_health_test_clr_qs;
+ logic conf_health_test_clr_wd;
+ logic conf_health_test_clr_we;
+ logic conf_rng_bit_en_qs;
+ logic conf_rng_bit_en_wd;
+ logic conf_rng_bit_en_we;
+ logic [1:0] conf_rng_bit_sel_qs;
+ logic [1:0] conf_rng_bit_sel_wd;
+ logic conf_rng_bit_sel_we;
+ logic [15:0] rate_qs;
+ logic [15:0] rate_wd;
+ logic rate_we;
+ logic entropy_control_es_route_qs;
+ logic entropy_control_es_route_wd;
+ logic entropy_control_es_route_we;
+ logic entropy_control_es_type_qs;
+ logic entropy_control_es_type_wd;
+ logic entropy_control_es_type_we;
+ logic [31:0] entropy_data_qs;
+ logic entropy_data_re;
+ logic [15:0] health_test_windows_fips_window_qs;
+ logic [15:0] health_test_windows_fips_window_wd;
+ logic health_test_windows_fips_window_we;
+ logic [15:0] health_test_windows_bypass_window_qs;
+ logic [15:0] health_test_windows_bypass_window_wd;
+ logic health_test_windows_bypass_window_we;
+ logic [15:0] repcnt_thresholds_fips_repcnt_thresh_qs;
+ logic [15:0] repcnt_thresholds_fips_repcnt_thresh_wd;
+ logic repcnt_thresholds_fips_repcnt_thresh_we;
+ logic [15:0] repcnt_thresholds_bypass_repcnt_thresh_qs;
+ logic [15:0] repcnt_thresholds_bypass_repcnt_thresh_wd;
+ logic repcnt_thresholds_bypass_repcnt_thresh_we;
+ logic [15:0] adaptp_hi_thresholds_fips_adaptp_hi_thresh_qs;
+ logic [15:0] adaptp_hi_thresholds_fips_adaptp_hi_thresh_wd;
+ logic adaptp_hi_thresholds_fips_adaptp_hi_thresh_we;
+ logic [15:0] adaptp_hi_thresholds_bypass_adaptp_hi_thresh_qs;
+ logic [15:0] adaptp_hi_thresholds_bypass_adaptp_hi_thresh_wd;
+ logic adaptp_hi_thresholds_bypass_adaptp_hi_thresh_we;
+ logic [15:0] adaptp_lo_thresholds_fips_adaptp_lo_thresh_qs;
+ logic [15:0] adaptp_lo_thresholds_fips_adaptp_lo_thresh_wd;
+ logic adaptp_lo_thresholds_fips_adaptp_lo_thresh_we;
+ logic [15:0] adaptp_lo_thresholds_bypass_adaptp_lo_thresh_qs;
+ logic [15:0] adaptp_lo_thresholds_bypass_adaptp_lo_thresh_wd;
+ logic adaptp_lo_thresholds_bypass_adaptp_lo_thresh_we;
+ logic [15:0] bucket_thresholds_fips_bucket_thresh_qs;
+ logic [15:0] bucket_thresholds_fips_bucket_thresh_wd;
+ logic bucket_thresholds_fips_bucket_thresh_we;
+ logic [15:0] bucket_thresholds_bypass_bucket_thresh_qs;
+ logic [15:0] bucket_thresholds_bypass_bucket_thresh_wd;
+ logic bucket_thresholds_bypass_bucket_thresh_we;
+ logic [15:0] markov_thresholds_fips_markov_thresh_qs;
+ logic [15:0] markov_thresholds_fips_markov_thresh_wd;
+ logic markov_thresholds_fips_markov_thresh_we;
+ logic [15:0] markov_thresholds_bypass_markov_thresh_qs;
+ logic [15:0] markov_thresholds_bypass_markov_thresh_wd;
+ logic markov_thresholds_bypass_markov_thresh_we;
+ logic [15:0] repcnt_hi_watermarks_fips_repcnt_hi_watermark_qs;
+ logic repcnt_hi_watermarks_fips_repcnt_hi_watermark_re;
+ logic [15:0] repcnt_hi_watermarks_bypass_repcnt_hi_watermark_qs;
+ logic repcnt_hi_watermarks_bypass_repcnt_hi_watermark_re;
+ logic [15:0] adaptp_hi_watermarks_fips_adaptp_hi_watermark_qs;
+ logic adaptp_hi_watermarks_fips_adaptp_hi_watermark_re;
+ logic [15:0] adaptp_hi_watermarks_bypass_adaptp_hi_watermark_qs;
+ logic adaptp_hi_watermarks_bypass_adaptp_hi_watermark_re;
+ logic [15:0] adaptp_lo_watermarks_fips_adaptp_lo_watermark_qs;
+ logic adaptp_lo_watermarks_fips_adaptp_lo_watermark_re;
+ logic [15:0] adaptp_lo_watermarks_bypass_adaptp_lo_watermark_qs;
+ logic adaptp_lo_watermarks_bypass_adaptp_lo_watermark_re;
+ logic [15:0] bucket_hi_watermarks_fips_bucket_hi_watermark_qs;
+ logic bucket_hi_watermarks_fips_bucket_hi_watermark_re;
+ logic [15:0] bucket_hi_watermarks_bypass_bucket_hi_watermark_qs;
+ logic bucket_hi_watermarks_bypass_bucket_hi_watermark_re;
+ logic [15:0] markov_hi_watermarks_fips_markov_hi_watermark_qs;
+ logic markov_hi_watermarks_fips_markov_hi_watermark_re;
+ logic [15:0] markov_hi_watermarks_bypass_markov_hi_watermark_qs;
+ logic markov_hi_watermarks_bypass_markov_hi_watermark_re;
+ logic [31:0] repcnt_total_fails_qs;
+ logic repcnt_total_fails_re;
+ logic [31:0] adaptp_hi_total_fails_qs;
+ logic adaptp_hi_total_fails_re;
+ logic [31:0] adaptp_lo_total_fails_qs;
+ logic adaptp_lo_total_fails_re;
+ logic [31:0] bucket_total_fails_qs;
+ logic bucket_total_fails_re;
+ logic [31:0] markov_total_fails_qs;
+ logic markov_total_fails_re;
+ logic [3:0] alert_threshold_qs;
+ logic [3:0] alert_threshold_wd;
+ logic alert_threshold_we;
+ logic [3:0] alert_fail_counts_any_fail_count_qs;
+ logic alert_fail_counts_any_fail_count_re;
+ logic [3:0] alert_fail_counts_repcnt_fail_count_qs;
+ logic alert_fail_counts_repcnt_fail_count_re;
+ logic [3:0] alert_fail_counts_adaptp_hi_fail_count_qs;
+ logic alert_fail_counts_adaptp_hi_fail_count_re;
+ logic [3:0] alert_fail_counts_adaptp_lo_fail_count_qs;
+ logic alert_fail_counts_adaptp_lo_fail_count_re;
+ logic [3:0] alert_fail_counts_bucket_fail_count_qs;
+ logic alert_fail_counts_bucket_fail_count_re;
+ logic [3:0] alert_fail_counts_markov_fail_count_qs;
+ logic alert_fail_counts_markov_fail_count_re;
+ logic [1:0] debug_status_entropy_fifo_depth_qs;
+ logic debug_status_entropy_fifo_depth_re;
+ logic debug_status_diag_qs;
+ logic debug_status_diag_re;
+ logic [3:0] seed_qs;
+ logic [3:0] seed_wd;
+ logic seed_we;
// Register instances
// R[intr_state]: V(False)
@@ -187,59 +257,33 @@
);
- // F[es_rct_failed]: 1:1
+ // F[es_health_test_failed]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
- ) u_intr_state_es_rct_failed (
+ ) u_intr_state_es_health_test_failed (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_state_es_rct_failed_we),
- .wd (intr_state_es_rct_failed_wd),
+ .we (intr_state_es_health_test_failed_we),
+ .wd (intr_state_es_health_test_failed_wd),
// from internal hardware
- .de (hw2reg.intr_state.es_rct_failed.de),
- .d (hw2reg.intr_state.es_rct_failed.d ),
+ .de (hw2reg.intr_state.es_health_test_failed.de),
+ .d (hw2reg.intr_state.es_health_test_failed.d ),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.es_rct_failed.q ),
+ .q (reg2hw.intr_state.es_health_test_failed.q ),
// to register interface (read)
- .qs (intr_state_es_rct_failed_qs)
+ .qs (intr_state_es_health_test_failed_qs)
);
- // F[es_apt_failed]: 2:2
- prim_subreg #(
- .DW (1),
- .SWACCESS("W1C"),
- .RESVAL (1'h0)
- ) u_intr_state_es_apt_failed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (intr_state_es_apt_failed_we),
- .wd (intr_state_es_apt_failed_wd),
-
- // from internal hardware
- .de (hw2reg.intr_state.es_apt_failed.de),
- .d (hw2reg.intr_state.es_apt_failed.d ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_state.es_apt_failed.q ),
-
- // to register interface (read)
- .qs (intr_state_es_apt_failed_qs)
- );
-
-
- // F[es_fifo_err]: 3:3
+ // F[es_fifo_err]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
@@ -293,18 +337,18 @@
);
- // F[es_rct_failed]: 1:1
+ // F[es_health_test_failed]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_intr_enable_es_rct_failed (
+ ) u_intr_enable_es_health_test_failed (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_enable_es_rct_failed_we),
- .wd (intr_enable_es_rct_failed_wd),
+ .we (intr_enable_es_health_test_failed_we),
+ .wd (intr_enable_es_health_test_failed_wd),
// from internal hardware
.de (1'b0),
@@ -312,40 +356,14 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.es_rct_failed.q ),
+ .q (reg2hw.intr_enable.es_health_test_failed.q ),
// to register interface (read)
- .qs (intr_enable_es_rct_failed_qs)
+ .qs (intr_enable_es_health_test_failed_qs)
);
- // F[es_apt_failed]: 2:2
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_intr_enable_es_apt_failed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (intr_enable_es_apt_failed_we),
- .wd (intr_enable_es_apt_failed_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_enable.es_apt_failed.q ),
-
- // to register interface (read)
- .qs (intr_enable_es_apt_failed_qs)
- );
-
-
- // F[es_fifo_err]: 3:3
+ // F[es_fifo_err]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -388,37 +406,22 @@
);
- // F[es_rct_failed]: 1:1
+ // F[es_health_test_failed]: 1:1
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_es_rct_failed (
+ ) u_intr_test_es_health_test_failed (
.re (1'b0),
- .we (intr_test_es_rct_failed_we),
- .wd (intr_test_es_rct_failed_wd),
+ .we (intr_test_es_health_test_failed_we),
+ .wd (intr_test_es_health_test_failed_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.es_rct_failed.qe),
- .q (reg2hw.intr_test.es_rct_failed.q ),
+ .qe (reg2hw.intr_test.es_health_test_failed.qe),
+ .q (reg2hw.intr_test.es_health_test_failed.q ),
.qs ()
);
- // F[es_apt_failed]: 2:2
- prim_subreg_ext #(
- .DW (1)
- ) u_intr_test_es_apt_failed (
- .re (1'b0),
- .we (intr_test_es_apt_failed_we),
- .wd (intr_test_es_apt_failed_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.intr_test.es_apt_failed.qe),
- .q (reg2hw.intr_test.es_apt_failed.q ),
- .qs ()
- );
-
-
- // F[es_fifo_err]: 3:3
+ // F[es_fifo_err]: 2:2
prim_subreg_ext #(
.DW (1)
) u_intr_test_es_fifo_err (
@@ -433,19 +436,19 @@
);
- // R[es_regen]: V(False)
+ // R[regen]: V(False)
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h1)
- ) u_es_regen (
+ ) u_regen (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (es_regen_we),
- .wd (es_regen_wd),
+ .we (regen_we),
+ .wd (regen_wd),
// from internal hardware
.de (1'b0),
@@ -453,44 +456,44 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_regen.q ),
+ .q (reg2hw.regen.q ),
// to register interface (read)
- .qs (es_regen_qs)
+ .qs (regen_qs)
);
- // R[es_rev]: V(False)
+ // R[rev]: V(False)
// F[abi_revision]: 7:0
// constant-only read
- assign es_rev_abi_revision_qs = 8'h1;
+ assign rev_abi_revision_qs = 8'h3;
// F[hw_revision]: 15:8
// constant-only read
- assign es_rev_hw_revision_qs = 8'h1;
+ assign rev_hw_revision_qs = 8'h3;
// F[chip_type]: 23:16
// constant-only read
- assign es_rev_chip_type_qs = 8'h1;
+ assign rev_chip_type_qs = 8'h1;
- // R[es_conf]: V(False)
+ // R[conf]: V(False)
// F[enable]: 1:0
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h0)
- ) u_es_conf_enable (
+ ) u_conf_enable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_enable_we & es_regen_qs),
- .wd (es_conf_enable_wd),
+ .we (conf_enable_we & regen_qs),
+ .wd (conf_enable_wd),
// from internal hardware
.de (1'b0),
@@ -498,25 +501,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.enable.q ),
+ .q (reg2hw.conf.enable.q ),
// to register interface (read)
- .qs (es_conf_enable_qs)
+ .qs (conf_enable_qs)
);
- // F[rng_src_en]: 4:4
+ // F[boot_bypass_disable]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_es_conf_rng_src_en (
+ ) u_conf_boot_bypass_disable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_rng_src_en_we & es_regen_qs),
- .wd (es_conf_rng_src_en_wd),
+ .we (conf_boot_bypass_disable_we & regen_qs),
+ .wd (conf_boot_bypass_disable_wd),
// from internal hardware
.de (1'b0),
@@ -524,25 +527,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.rng_src_en.q ),
+ .q (reg2hw.conf.boot_bypass_disable.q ),
// to register interface (read)
- .qs (es_conf_rng_src_en_qs)
+ .qs (conf_boot_bypass_disable_qs)
);
- // F[rct_en]: 5:5
+ // F[repcnt_disable]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_es_conf_rct_en (
+ ) u_conf_repcnt_disable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_rct_en_we & es_regen_qs),
- .wd (es_conf_rct_en_wd),
+ .we (conf_repcnt_disable_we & regen_qs),
+ .wd (conf_repcnt_disable_wd),
// from internal hardware
.de (1'b0),
@@ -550,25 +553,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.rct_en.q ),
+ .q (reg2hw.conf.repcnt_disable.q ),
// to register interface (read)
- .qs (es_conf_rct_en_qs)
+ .qs (conf_repcnt_disable_qs)
);
- // F[apt_en]: 6:6
+ // F[adaptp_disable]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_es_conf_apt_en (
+ ) u_conf_adaptp_disable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_apt_en_we & es_regen_qs),
- .wd (es_conf_apt_en_wd),
+ .we (conf_adaptp_disable_we & regen_qs),
+ .wd (conf_adaptp_disable_wd),
// from internal hardware
.de (1'b0),
@@ -576,25 +579,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.apt_en.q ),
+ .q (reg2hw.conf.adaptp_disable.q ),
// to register interface (read)
- .qs (es_conf_apt_en_qs)
+ .qs (conf_adaptp_disable_qs)
);
- // F[rng_bit_en]: 8:8
+ // F[bucket_disable]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_es_conf_rng_bit_en (
+ ) u_conf_bucket_disable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_rng_bit_en_we & es_regen_qs),
- .wd (es_conf_rng_bit_en_wd),
+ .we (conf_bucket_disable_we & regen_qs),
+ .wd (conf_bucket_disable_wd),
// from internal hardware
.de (1'b0),
@@ -602,25 +605,103 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.rng_bit_en.q ),
+ .q (reg2hw.conf.bucket_disable.q ),
// to register interface (read)
- .qs (es_conf_rng_bit_en_qs)
+ .qs (conf_bucket_disable_qs)
);
- // F[rng_bit_sel]: 10:9
+ // F[markov_disable]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_conf_markov_disable (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (conf_markov_disable_we & regen_qs),
+ .wd (conf_markov_disable_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.conf.markov_disable.q ),
+
+ // to register interface (read)
+ .qs (conf_markov_disable_qs)
+ );
+
+
+ // F[health_test_clr]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_conf_health_test_clr (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (conf_health_test_clr_we & regen_qs),
+ .wd (conf_health_test_clr_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.conf.health_test_clr.q ),
+
+ // to register interface (read)
+ .qs (conf_health_test_clr_qs)
+ );
+
+
+ // F[rng_bit_en]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_conf_rng_bit_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (conf_rng_bit_en_we & regen_qs),
+ .wd (conf_rng_bit_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.conf.rng_bit_en.q ),
+
+ // to register interface (read)
+ .qs (conf_rng_bit_en_qs)
+ );
+
+
+ // F[rng_bit_sel]: 11:10
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h0)
- ) u_es_conf_rng_bit_sel (
+ ) u_conf_rng_bit_sel (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_conf_rng_bit_sel_we & es_regen_qs),
- .wd (es_conf_rng_bit_sel_wd),
+ .we (conf_rng_bit_sel_we & regen_qs),
+ .wd (conf_rng_bit_sel_wd),
// from internal hardware
.de (1'b0),
@@ -628,26 +709,26 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_conf.rng_bit_sel.q ),
+ .q (reg2hw.conf.rng_bit_sel.q ),
// to register interface (read)
- .qs (es_conf_rng_bit_sel_qs)
+ .qs (conf_rng_bit_sel_qs)
);
- // R[es_rct_health]: V(False)
+ // R[rate]: V(False)
prim_subreg #(
.DW (16),
.SWACCESS("RW"),
- .RESVAL (16'hb)
- ) u_es_rct_health (
+ .RESVAL (16'h7d0)
+ ) u_rate (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface (qualified with register enable)
- .we (es_rct_health_we & es_regen_qs),
- .wd (es_rct_health_wd),
+ // from register interface
+ .we (rate_we),
+ .wd (rate_wd),
// from internal hardware
.de (1'b0),
@@ -655,27 +736,27 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_rct_health.q ),
+ .q (reg2hw.rate.q ),
// to register interface (read)
- .qs (es_rct_health_qs)
+ .qs (rate_qs)
);
- // R[es_apt_health]: V(False)
+ // R[entropy_control]: V(False)
- // F[apt_max]: 15:0
+ // F[es_route]: 0:0
prim_subreg #(
- .DW (16),
+ .DW (1),
.SWACCESS("RW"),
- .RESVAL (16'h298)
- ) u_es_apt_health_apt_max (
+ .RESVAL (1'h0)
+ ) u_entropy_control_es_route (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_apt_health_apt_max_we & es_regen_qs),
- .wd (es_apt_health_apt_max_wd),
+ .we (entropy_control_es_route_we & regen_qs),
+ .wd (entropy_control_es_route_wd),
// from internal hardware
.de (1'b0),
@@ -683,25 +764,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_apt_health.apt_max.q ),
+ .q (reg2hw.entropy_control.es_route.q ),
// to register interface (read)
- .qs (es_apt_health_apt_max_qs)
+ .qs (entropy_control_es_route_qs)
);
- // F[apt_win]: 31:16
+ // F[es_type]: 1:1
prim_subreg #(
- .DW (16),
+ .DW (1),
.SWACCESS("RW"),
- .RESVAL (16'h400)
- ) u_es_apt_health_apt_win (
+ .RESVAL (1'h0)
+ ) u_entropy_control_es_type (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_apt_health_apt_win_we & es_regen_qs),
- .wd (es_apt_health_apt_win_wd),
+ .we (entropy_control_es_type_we & regen_qs),
+ .wd (entropy_control_es_type_wd),
// from internal hardware
.de (1'b0),
@@ -709,174 +790,757 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_apt_health.apt_win.q ),
+ .q (reg2hw.entropy_control.es_type.q ),
// to register interface (read)
- .qs (es_apt_health_apt_win_qs)
+ .qs (entropy_control_es_type_qs)
);
- // R[es_entropy]: V(True)
+ // R[entropy_data]: V(True)
prim_subreg_ext #(
.DW (32)
- ) u_es_entropy (
- .re (es_entropy_re),
+ ) u_entropy_data (
+ .re (entropy_data_re),
.we (1'b0),
.wd ('0),
- .d (hw2reg.es_entropy.d),
- .qre (reg2hw.es_entropy.re),
+ .d (hw2reg.entropy_data.d),
+ .qre (reg2hw.entropy_data.re),
.qe (),
- .q (reg2hw.es_entropy.q ),
- .qs (es_entropy_qs)
+ .q (reg2hw.entropy_data.q ),
+ .qs (entropy_data_qs)
);
- // R[es_fifo_status]: V(True)
+ // R[health_test_windows]: V(False)
- // F[dig_src_depth]: 2:0
- prim_subreg_ext #(
- .DW (3)
- ) u_es_fifo_status_dig_src_depth (
- .re (es_fifo_status_dig_src_depth_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.es_fifo_status.dig_src_depth.d),
- .qre (),
+ // F[fips_window]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h100)
+ ) u_health_test_windows_fips_window (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (health_test_windows_fips_window_we & regen_qs),
+ .wd (health_test_windows_fips_window_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
.qe (),
- .q (),
- .qs (es_fifo_status_dig_src_depth_qs)
+ .q (reg2hw.health_test_windows.fips_window.q ),
+
+ // to register interface (read)
+ .qs (health_test_windows_fips_window_qs)
);
- // F[hwif_depth]: 6:4
- prim_subreg_ext #(
- .DW (3)
- ) u_es_fifo_status_hwif_depth (
- .re (es_fifo_status_hwif_depth_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.es_fifo_status.hwif_depth.d),
- .qre (),
+ // F[bypass_window]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h60)
+ ) u_health_test_windows_bypass_window (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (health_test_windows_bypass_window_we & regen_qs),
+ .wd (health_test_windows_bypass_window_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
.qe (),
- .q (),
- .qs (es_fifo_status_hwif_depth_qs)
+ .q (reg2hw.health_test_windows.bypass_window.q ),
+
+ // to register interface (read)
+ .qs (health_test_windows_bypass_window_qs)
);
- // F[es_depth]: 16:12
+ // R[repcnt_thresholds]: V(False)
+
+ // F[fips_repcnt_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h20)
+ ) u_repcnt_thresholds_fips_repcnt_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (repcnt_thresholds_fips_repcnt_thresh_we & regen_qs),
+ .wd (repcnt_thresholds_fips_repcnt_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.repcnt_thresholds.fips_repcnt_thresh.q ),
+
+ // to register interface (read)
+ .qs (repcnt_thresholds_fips_repcnt_thresh_qs)
+ );
+
+
+ // F[bypass_repcnt_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h20)
+ ) u_repcnt_thresholds_bypass_repcnt_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (repcnt_thresholds_bypass_repcnt_thresh_we & regen_qs),
+ .wd (repcnt_thresholds_bypass_repcnt_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.repcnt_thresholds.bypass_repcnt_thresh.q ),
+
+ // to register interface (read)
+ .qs (repcnt_thresholds_bypass_repcnt_thresh_qs)
+ );
+
+
+ // R[adaptp_hi_thresholds]: V(False)
+
+ // F[fips_adaptp_hi_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h256)
+ ) u_adaptp_hi_thresholds_fips_adaptp_hi_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (adaptp_hi_thresholds_fips_adaptp_hi_thresh_we & regen_qs),
+ .wd (adaptp_hi_thresholds_fips_adaptp_hi_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.adaptp_hi_thresholds.fips_adaptp_hi_thresh.q ),
+
+ // to register interface (read)
+ .qs (adaptp_hi_thresholds_fips_adaptp_hi_thresh_qs)
+ );
+
+
+ // F[bypass_adaptp_hi_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'he0)
+ ) u_adaptp_hi_thresholds_bypass_adaptp_hi_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (adaptp_hi_thresholds_bypass_adaptp_hi_thresh_we & regen_qs),
+ .wd (adaptp_hi_thresholds_bypass_adaptp_hi_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.adaptp_hi_thresholds.bypass_adaptp_hi_thresh.q ),
+
+ // to register interface (read)
+ .qs (adaptp_hi_thresholds_bypass_adaptp_hi_thresh_qs)
+ );
+
+
+ // R[adaptp_lo_thresholds]: V(False)
+
+ // F[fips_adaptp_lo_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h1aa)
+ ) u_adaptp_lo_thresholds_fips_adaptp_lo_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (adaptp_lo_thresholds_fips_adaptp_lo_thresh_we & regen_qs),
+ .wd (adaptp_lo_thresholds_fips_adaptp_lo_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.adaptp_lo_thresholds.fips_adaptp_lo_thresh.q ),
+
+ // to register interface (read)
+ .qs (adaptp_lo_thresholds_fips_adaptp_lo_thresh_qs)
+ );
+
+
+ // F[bypass_adaptp_lo_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'ha0)
+ ) u_adaptp_lo_thresholds_bypass_adaptp_lo_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (adaptp_lo_thresholds_bypass_adaptp_lo_thresh_we & regen_qs),
+ .wd (adaptp_lo_thresholds_bypass_adaptp_lo_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.adaptp_lo_thresholds.bypass_adaptp_lo_thresh.q ),
+
+ // to register interface (read)
+ .qs (adaptp_lo_thresholds_bypass_adaptp_lo_thresh_qs)
+ );
+
+
+ // R[bucket_thresholds]: V(False)
+
+ // F[fips_bucket_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h20)
+ ) u_bucket_thresholds_fips_bucket_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bucket_thresholds_fips_bucket_thresh_we & regen_qs),
+ .wd (bucket_thresholds_fips_bucket_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bucket_thresholds.fips_bucket_thresh.q ),
+
+ // to register interface (read)
+ .qs (bucket_thresholds_fips_bucket_thresh_qs)
+ );
+
+
+ // F[bypass_bucket_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h20)
+ ) u_bucket_thresholds_bypass_bucket_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bucket_thresholds_bypass_bucket_thresh_we & regen_qs),
+ .wd (bucket_thresholds_bypass_bucket_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bucket_thresholds.bypass_bucket_thresh.q ),
+
+ // to register interface (read)
+ .qs (bucket_thresholds_bypass_bucket_thresh_qs)
+ );
+
+
+ // R[markov_thresholds]: V(False)
+
+ // F[fips_markov_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h100)
+ ) u_markov_thresholds_fips_markov_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (markov_thresholds_fips_markov_thresh_we & regen_qs),
+ .wd (markov_thresholds_fips_markov_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.markov_thresholds.fips_markov_thresh.q ),
+
+ // to register interface (read)
+ .qs (markov_thresholds_fips_markov_thresh_qs)
+ );
+
+
+ // F[bypass_markov_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h60)
+ ) u_markov_thresholds_bypass_markov_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (markov_thresholds_bypass_markov_thresh_we & regen_qs),
+ .wd (markov_thresholds_bypass_markov_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.markov_thresholds.bypass_markov_thresh.q ),
+
+ // to register interface (read)
+ .qs (markov_thresholds_bypass_markov_thresh_qs)
+ );
+
+
+ // R[repcnt_hi_watermarks]: V(True)
+
+ // F[fips_repcnt_hi_watermark]: 15:0
prim_subreg_ext #(
- .DW (5)
- ) u_es_fifo_status_es_depth (
- .re (es_fifo_status_es_depth_re),
+ .DW (16)
+ ) u_repcnt_hi_watermarks_fips_repcnt_hi_watermark (
+ .re (repcnt_hi_watermarks_fips_repcnt_hi_watermark_re),
.we (1'b0),
.wd ('0),
- .d (hw2reg.es_fifo_status.es_depth.d),
+ .d (hw2reg.repcnt_hi_watermarks.fips_repcnt_hi_watermark.d),
.qre (),
.qe (),
.q (),
- .qs (es_fifo_status_es_depth_qs)
+ .qs (repcnt_hi_watermarks_fips_repcnt_hi_watermark_qs)
+ );
+
+
+ // F[bypass_repcnt_hi_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_repcnt_hi_watermarks_bypass_repcnt_hi_watermark (
+ .re (repcnt_hi_watermarks_bypass_repcnt_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.repcnt_hi_watermarks.bypass_repcnt_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (repcnt_hi_watermarks_bypass_repcnt_hi_watermark_qs)
+ );
+
+
+ // R[adaptp_hi_watermarks]: V(True)
+
+ // F[fips_adaptp_hi_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_adaptp_hi_watermarks_fips_adaptp_hi_watermark (
+ .re (adaptp_hi_watermarks_fips_adaptp_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_hi_watermarks.fips_adaptp_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_hi_watermarks_fips_adaptp_hi_watermark_qs)
+ );
+
+
+ // F[bypass_adaptp_hi_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_adaptp_hi_watermarks_bypass_adaptp_hi_watermark (
+ .re (adaptp_hi_watermarks_bypass_adaptp_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_hi_watermarks.bypass_adaptp_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_hi_watermarks_bypass_adaptp_hi_watermark_qs)
+ );
+
+
+ // R[adaptp_lo_watermarks]: V(True)
+
+ // F[fips_adaptp_lo_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_adaptp_lo_watermarks_fips_adaptp_lo_watermark (
+ .re (adaptp_lo_watermarks_fips_adaptp_lo_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_lo_watermarks.fips_adaptp_lo_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_lo_watermarks_fips_adaptp_lo_watermark_qs)
+ );
+
+
+ // F[bypass_adaptp_lo_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_adaptp_lo_watermarks_bypass_adaptp_lo_watermark (
+ .re (adaptp_lo_watermarks_bypass_adaptp_lo_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_lo_watermarks.bypass_adaptp_lo_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_lo_watermarks_bypass_adaptp_lo_watermark_qs)
+ );
+
+
+ // R[bucket_hi_watermarks]: V(True)
+
+ // F[fips_bucket_hi_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_bucket_hi_watermarks_fips_bucket_hi_watermark (
+ .re (bucket_hi_watermarks_fips_bucket_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.bucket_hi_watermarks.fips_bucket_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (bucket_hi_watermarks_fips_bucket_hi_watermark_qs)
+ );
+
+
+ // F[bypass_bucket_hi_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_bucket_hi_watermarks_bypass_bucket_hi_watermark (
+ .re (bucket_hi_watermarks_bypass_bucket_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.bucket_hi_watermarks.bypass_bucket_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (bucket_hi_watermarks_bypass_bucket_hi_watermark_qs)
+ );
+
+
+ // R[markov_hi_watermarks]: V(True)
+
+ // F[fips_markov_hi_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_markov_hi_watermarks_fips_markov_hi_watermark (
+ .re (markov_hi_watermarks_fips_markov_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.markov_hi_watermarks.fips_markov_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (markov_hi_watermarks_fips_markov_hi_watermark_qs)
+ );
+
+
+ // F[bypass_markov_hi_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_markov_hi_watermarks_bypass_markov_hi_watermark (
+ .re (markov_hi_watermarks_bypass_markov_hi_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.markov_hi_watermarks.bypass_markov_hi_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (markov_hi_watermarks_bypass_markov_hi_watermark_qs)
+ );
+
+
+ // R[repcnt_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_repcnt_total_fails (
+ .re (repcnt_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.repcnt_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (repcnt_total_fails_qs)
+ );
+
+
+ // R[adaptp_hi_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_adaptp_hi_total_fails (
+ .re (adaptp_hi_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_hi_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_hi_total_fails_qs)
+ );
+
+
+ // R[adaptp_lo_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_adaptp_lo_total_fails (
+ .re (adaptp_lo_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.adaptp_lo_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (adaptp_lo_total_fails_qs)
+ );
+
+
+ // R[bucket_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_bucket_total_fails (
+ .re (bucket_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.bucket_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (bucket_total_fails_qs)
+ );
+
+
+ // R[markov_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_markov_total_fails (
+ .re (markov_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.markov_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (markov_total_fails_qs)
+ );
+
+
+ // R[alert_threshold]: V(False)
+
+ prim_subreg #(
+ .DW (4),
+ .SWACCESS("RW"),
+ .RESVAL (4'h2)
+ ) u_alert_threshold (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_threshold_we & regen_qs),
+ .wd (alert_threshold_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_threshold.q ),
+
+ // to register interface (read)
+ .qs (alert_threshold_qs)
+ );
+
+
+ // R[alert_fail_counts]: V(True)
+
+ // F[any_fail_count]: 3:0
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_any_fail_count (
+ .re (alert_fail_counts_any_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.any_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_any_fail_count_qs)
+ );
+
+
+ // F[repcnt_fail_count]: 7:4
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_repcnt_fail_count (
+ .re (alert_fail_counts_repcnt_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.repcnt_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_repcnt_fail_count_qs)
+ );
+
+
+ // F[adaptp_hi_fail_count]: 11:8
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_adaptp_hi_fail_count (
+ .re (alert_fail_counts_adaptp_hi_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.adaptp_hi_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_adaptp_hi_fail_count_qs)
+ );
+
+
+ // F[adaptp_lo_fail_count]: 15:12
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_adaptp_lo_fail_count (
+ .re (alert_fail_counts_adaptp_lo_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.adaptp_lo_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_adaptp_lo_fail_count_qs)
+ );
+
+
+ // F[bucket_fail_count]: 19:16
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_bucket_fail_count (
+ .re (alert_fail_counts_bucket_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.bucket_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_bucket_fail_count_qs)
+ );
+
+
+ // F[markov_fail_count]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_markov_fail_count (
+ .re (alert_fail_counts_markov_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.markov_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_markov_fail_count_qs)
+ );
+
+
+ // R[debug_status]: V(True)
+
+ // F[entropy_fifo_depth]: 1:0
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_debug_status_entropy_fifo_depth (
+ .re (debug_status_entropy_fifo_depth_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.debug_status.entropy_fifo_depth.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (debug_status_entropy_fifo_depth_qs)
);
// F[diag]: 31:31
prim_subreg_ext #(
.DW (1)
- ) u_es_fifo_status_diag (
- .re (es_fifo_status_diag_re),
+ ) u_debug_status_diag (
+ .re (debug_status_diag_re),
.we (1'b0),
.wd ('0),
- .d (hw2reg.es_fifo_status.diag.d),
+ .d (hw2reg.debug_status.diag.d),
.qre (),
.qe (),
.q (),
- .qs (es_fifo_status_diag_qs)
+ .qs (debug_status_diag_qs)
);
- // R[es_fdepthst]: V(True)
-
- prim_subreg_ext #(
- .DW (3)
- ) u_es_fdepthst (
- .re (es_fdepthst_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.es_fdepthst.d),
- .qre (),
- .qe (),
- .q (),
- .qs (es_fdepthst_qs)
- );
-
-
- // R[es_thresh]: V(False)
-
- prim_subreg #(
- .DW (3),
- .SWACCESS("RW"),
- .RESVAL (3'h0)
- ) u_es_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (es_thresh_we),
- .wd (es_thresh_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.es_thresh.q ),
-
- // to register interface (read)
- .qs (es_thresh_qs)
- );
-
-
- // R[es_rate]: V(False)
-
- prim_subreg #(
- .DW (16),
- .SWACCESS("RW"),
- .RESVAL (16'h4)
- ) u_es_rate (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (es_rate_we),
- .wd (es_rate_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.es_rate.q ),
-
- // to register interface (read)
- .qs (es_rate_qs)
- );
-
-
- // R[es_seed]: V(False)
+ // R[seed]: V(False)
prim_subreg #(
.DW (4),
.SWACCESS("RW"),
.RESVAL (4'hb)
- ) u_es_seed (
+ ) u_seed (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (es_seed_we & es_regen_qs),
- .wd (es_seed_wd),
+ .we (seed_we & regen_qs),
+ .wd (seed_wd),
// from internal hardware
.de (1'b0),
@@ -884,32 +1548,47 @@
// to internal hardware
.qe (),
- .q (reg2hw.es_seed.q ),
+ .q (reg2hw.seed.q ),
// to register interface (read)
- .qs (es_seed_qs)
+ .qs (seed_qs)
);
- logic [13:0] addr_hit;
+ logic [28:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ENTROPY_SRC_INTR_STATE_OFFSET);
addr_hit[ 1] = (reg_addr == ENTROPY_SRC_INTR_ENABLE_OFFSET);
addr_hit[ 2] = (reg_addr == ENTROPY_SRC_INTR_TEST_OFFSET);
- addr_hit[ 3] = (reg_addr == ENTROPY_SRC_ES_REGEN_OFFSET);
- addr_hit[ 4] = (reg_addr == ENTROPY_SRC_ES_REV_OFFSET);
- addr_hit[ 5] = (reg_addr == ENTROPY_SRC_ES_CONF_OFFSET);
- addr_hit[ 6] = (reg_addr == ENTROPY_SRC_ES_RCT_HEALTH_OFFSET);
- addr_hit[ 7] = (reg_addr == ENTROPY_SRC_ES_APT_HEALTH_OFFSET);
- addr_hit[ 8] = (reg_addr == ENTROPY_SRC_ES_ENTROPY_OFFSET);
- addr_hit[ 9] = (reg_addr == ENTROPY_SRC_ES_FIFO_STATUS_OFFSET);
- addr_hit[10] = (reg_addr == ENTROPY_SRC_ES_FDEPTHST_OFFSET);
- addr_hit[11] = (reg_addr == ENTROPY_SRC_ES_THRESH_OFFSET);
- addr_hit[12] = (reg_addr == ENTROPY_SRC_ES_RATE_OFFSET);
- addr_hit[13] = (reg_addr == ENTROPY_SRC_ES_SEED_OFFSET);
+ addr_hit[ 3] = (reg_addr == ENTROPY_SRC_REGEN_OFFSET);
+ addr_hit[ 4] = (reg_addr == ENTROPY_SRC_REV_OFFSET);
+ addr_hit[ 5] = (reg_addr == ENTROPY_SRC_CONF_OFFSET);
+ addr_hit[ 6] = (reg_addr == ENTROPY_SRC_RATE_OFFSET);
+ addr_hit[ 7] = (reg_addr == ENTROPY_SRC_ENTROPY_CONTROL_OFFSET);
+ addr_hit[ 8] = (reg_addr == ENTROPY_SRC_ENTROPY_DATA_OFFSET);
+ addr_hit[ 9] = (reg_addr == ENTROPY_SRC_HEALTH_TEST_WINDOWS_OFFSET);
+ addr_hit[10] = (reg_addr == ENTROPY_SRC_REPCNT_THRESHOLDS_OFFSET);
+ addr_hit[11] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET);
+ addr_hit[12] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET);
+ addr_hit[13] = (reg_addr == ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET);
+ addr_hit[14] = (reg_addr == ENTROPY_SRC_MARKOV_THRESHOLDS_OFFSET);
+ addr_hit[15] = (reg_addr == ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET);
+ addr_hit[16] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET);
+ addr_hit[17] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET);
+ addr_hit[18] = (reg_addr == ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET);
+ addr_hit[19] = (reg_addr == ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET);
+ addr_hit[20] = (reg_addr == ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET);
+ addr_hit[21] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET);
+ addr_hit[22] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET);
+ addr_hit[23] = (reg_addr == ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET);
+ addr_hit[24] = (reg_addr == ENTROPY_SRC_MARKOV_TOTAL_FAILS_OFFSET);
+ addr_hit[25] = (reg_addr == ENTROPY_SRC_ALERT_THRESHOLD_OFFSET);
+ addr_hit[26] = (reg_addr == ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET);
+ addr_hit[27] = (reg_addr == ENTROPY_SRC_DEBUG_STATUS_OFFSET);
+ addr_hit[28] = (reg_addr == ENTROPY_SRC_SEED_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -931,97 +1610,181 @@
if (addr_hit[11] && reg_we && (ENTROPY_SRC_PERMIT[11] != (ENTROPY_SRC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[12] && reg_we && (ENTROPY_SRC_PERMIT[12] != (ENTROPY_SRC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[13] && reg_we && (ENTROPY_SRC_PERMIT[13] != (ENTROPY_SRC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (ENTROPY_SRC_PERMIT[14] != (ENTROPY_SRC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[15] && reg_we && (ENTROPY_SRC_PERMIT[15] != (ENTROPY_SRC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[16] && reg_we && (ENTROPY_SRC_PERMIT[16] != (ENTROPY_SRC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[17] && reg_we && (ENTROPY_SRC_PERMIT[17] != (ENTROPY_SRC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[18] && reg_we && (ENTROPY_SRC_PERMIT[18] != (ENTROPY_SRC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[19] && reg_we && (ENTROPY_SRC_PERMIT[19] != (ENTROPY_SRC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[20] && reg_we && (ENTROPY_SRC_PERMIT[20] != (ENTROPY_SRC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[21] && reg_we && (ENTROPY_SRC_PERMIT[21] != (ENTROPY_SRC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[22] && reg_we && (ENTROPY_SRC_PERMIT[22] != (ENTROPY_SRC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[23] && reg_we && (ENTROPY_SRC_PERMIT[23] != (ENTROPY_SRC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[24] && reg_we && (ENTROPY_SRC_PERMIT[24] != (ENTROPY_SRC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[25] && reg_we && (ENTROPY_SRC_PERMIT[25] != (ENTROPY_SRC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[26] && reg_we && (ENTROPY_SRC_PERMIT[26] != (ENTROPY_SRC_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[27] && reg_we && (ENTROPY_SRC_PERMIT[27] != (ENTROPY_SRC_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[28] && reg_we && (ENTROPY_SRC_PERMIT[28] != (ENTROPY_SRC_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_es_entropy_valid_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_es_entropy_valid_wd = reg_wdata[0];
- assign intr_state_es_rct_failed_we = addr_hit[0] & reg_we & ~wr_err;
- assign intr_state_es_rct_failed_wd = reg_wdata[1];
-
- assign intr_state_es_apt_failed_we = addr_hit[0] & reg_we & ~wr_err;
- assign intr_state_es_apt_failed_wd = reg_wdata[2];
+ assign intr_state_es_health_test_failed_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_es_health_test_failed_wd = reg_wdata[1];
assign intr_state_es_fifo_err_we = addr_hit[0] & reg_we & ~wr_err;
- assign intr_state_es_fifo_err_wd = reg_wdata[3];
+ assign intr_state_es_fifo_err_wd = reg_wdata[2];
assign intr_enable_es_entropy_valid_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_es_entropy_valid_wd = reg_wdata[0];
- assign intr_enable_es_rct_failed_we = addr_hit[1] & reg_we & ~wr_err;
- assign intr_enable_es_rct_failed_wd = reg_wdata[1];
-
- assign intr_enable_es_apt_failed_we = addr_hit[1] & reg_we & ~wr_err;
- assign intr_enable_es_apt_failed_wd = reg_wdata[2];
+ assign intr_enable_es_health_test_failed_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_es_health_test_failed_wd = reg_wdata[1];
assign intr_enable_es_fifo_err_we = addr_hit[1] & reg_we & ~wr_err;
- assign intr_enable_es_fifo_err_wd = reg_wdata[3];
+ assign intr_enable_es_fifo_err_wd = reg_wdata[2];
assign intr_test_es_entropy_valid_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_es_entropy_valid_wd = reg_wdata[0];
- assign intr_test_es_rct_failed_we = addr_hit[2] & reg_we & ~wr_err;
- assign intr_test_es_rct_failed_wd = reg_wdata[1];
-
- assign intr_test_es_apt_failed_we = addr_hit[2] & reg_we & ~wr_err;
- assign intr_test_es_apt_failed_wd = reg_wdata[2];
+ assign intr_test_es_health_test_failed_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_es_health_test_failed_wd = reg_wdata[1];
assign intr_test_es_fifo_err_we = addr_hit[2] & reg_we & ~wr_err;
- assign intr_test_es_fifo_err_wd = reg_wdata[3];
+ assign intr_test_es_fifo_err_wd = reg_wdata[2];
- assign es_regen_we = addr_hit[3] & reg_we & ~wr_err;
- assign es_regen_wd = reg_wdata[0];
+ assign regen_we = addr_hit[3] & reg_we & ~wr_err;
+ assign regen_wd = reg_wdata[0];
- assign es_conf_enable_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_enable_wd = reg_wdata[1:0];
+ assign conf_enable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_enable_wd = reg_wdata[1:0];
- assign es_conf_rng_src_en_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_rng_src_en_wd = reg_wdata[4];
+ assign conf_boot_bypass_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_boot_bypass_disable_wd = reg_wdata[3];
- assign es_conf_rct_en_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_rct_en_wd = reg_wdata[5];
+ assign conf_repcnt_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_repcnt_disable_wd = reg_wdata[4];
- assign es_conf_apt_en_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_apt_en_wd = reg_wdata[6];
+ assign conf_adaptp_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_adaptp_disable_wd = reg_wdata[5];
- assign es_conf_rng_bit_en_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_rng_bit_en_wd = reg_wdata[8];
+ assign conf_bucket_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_bucket_disable_wd = reg_wdata[6];
- assign es_conf_rng_bit_sel_we = addr_hit[5] & reg_we & ~wr_err;
- assign es_conf_rng_bit_sel_wd = reg_wdata[10:9];
+ assign conf_markov_disable_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_markov_disable_wd = reg_wdata[7];
- assign es_rct_health_we = addr_hit[6] & reg_we & ~wr_err;
- assign es_rct_health_wd = reg_wdata[15:0];
+ assign conf_health_test_clr_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_health_test_clr_wd = reg_wdata[8];
- assign es_apt_health_apt_max_we = addr_hit[7] & reg_we & ~wr_err;
- assign es_apt_health_apt_max_wd = reg_wdata[15:0];
+ assign conf_rng_bit_en_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_rng_bit_en_wd = reg_wdata[9];
- assign es_apt_health_apt_win_we = addr_hit[7] & reg_we & ~wr_err;
- assign es_apt_health_apt_win_wd = reg_wdata[31:16];
+ assign conf_rng_bit_sel_we = addr_hit[5] & reg_we & ~wr_err;
+ assign conf_rng_bit_sel_wd = reg_wdata[11:10];
- assign es_entropy_re = addr_hit[8] && reg_re;
+ assign rate_we = addr_hit[6] & reg_we & ~wr_err;
+ assign rate_wd = reg_wdata[15:0];
- assign es_fifo_status_dig_src_depth_re = addr_hit[9] && reg_re;
+ assign entropy_control_es_route_we = addr_hit[7] & reg_we & ~wr_err;
+ assign entropy_control_es_route_wd = reg_wdata[0];
- assign es_fifo_status_hwif_depth_re = addr_hit[9] && reg_re;
+ assign entropy_control_es_type_we = addr_hit[7] & reg_we & ~wr_err;
+ assign entropy_control_es_type_wd = reg_wdata[1];
- assign es_fifo_status_es_depth_re = addr_hit[9] && reg_re;
+ assign entropy_data_re = addr_hit[8] && reg_re;
- assign es_fifo_status_diag_re = addr_hit[9] && reg_re;
+ assign health_test_windows_fips_window_we = addr_hit[9] & reg_we & ~wr_err;
+ assign health_test_windows_fips_window_wd = reg_wdata[15:0];
- assign es_fdepthst_re = addr_hit[10] && reg_re;
+ assign health_test_windows_bypass_window_we = addr_hit[9] & reg_we & ~wr_err;
+ assign health_test_windows_bypass_window_wd = reg_wdata[31:16];
- assign es_thresh_we = addr_hit[11] & reg_we & ~wr_err;
- assign es_thresh_wd = reg_wdata[2:0];
+ assign repcnt_thresholds_fips_repcnt_thresh_we = addr_hit[10] & reg_we & ~wr_err;
+ assign repcnt_thresholds_fips_repcnt_thresh_wd = reg_wdata[15:0];
- assign es_rate_we = addr_hit[12] & reg_we & ~wr_err;
- assign es_rate_wd = reg_wdata[15:0];
+ assign repcnt_thresholds_bypass_repcnt_thresh_we = addr_hit[10] & reg_we & ~wr_err;
+ assign repcnt_thresholds_bypass_repcnt_thresh_wd = reg_wdata[31:16];
- assign es_seed_we = addr_hit[13] & reg_we & ~wr_err;
- assign es_seed_wd = reg_wdata[3:0];
+ assign adaptp_hi_thresholds_fips_adaptp_hi_thresh_we = addr_hit[11] & reg_we & ~wr_err;
+ assign adaptp_hi_thresholds_fips_adaptp_hi_thresh_wd = reg_wdata[15:0];
+
+ assign adaptp_hi_thresholds_bypass_adaptp_hi_thresh_we = addr_hit[11] & reg_we & ~wr_err;
+ assign adaptp_hi_thresholds_bypass_adaptp_hi_thresh_wd = reg_wdata[31:16];
+
+ assign adaptp_lo_thresholds_fips_adaptp_lo_thresh_we = addr_hit[12] & reg_we & ~wr_err;
+ assign adaptp_lo_thresholds_fips_adaptp_lo_thresh_wd = reg_wdata[15:0];
+
+ assign adaptp_lo_thresholds_bypass_adaptp_lo_thresh_we = addr_hit[12] & reg_we & ~wr_err;
+ assign adaptp_lo_thresholds_bypass_adaptp_lo_thresh_wd = reg_wdata[31:16];
+
+ assign bucket_thresholds_fips_bucket_thresh_we = addr_hit[13] & reg_we & ~wr_err;
+ assign bucket_thresholds_fips_bucket_thresh_wd = reg_wdata[15:0];
+
+ assign bucket_thresholds_bypass_bucket_thresh_we = addr_hit[13] & reg_we & ~wr_err;
+ assign bucket_thresholds_bypass_bucket_thresh_wd = reg_wdata[31:16];
+
+ assign markov_thresholds_fips_markov_thresh_we = addr_hit[14] & reg_we & ~wr_err;
+ assign markov_thresholds_fips_markov_thresh_wd = reg_wdata[15:0];
+
+ assign markov_thresholds_bypass_markov_thresh_we = addr_hit[14] & reg_we & ~wr_err;
+ assign markov_thresholds_bypass_markov_thresh_wd = reg_wdata[31:16];
+
+ assign repcnt_hi_watermarks_fips_repcnt_hi_watermark_re = addr_hit[15] && reg_re;
+
+ assign repcnt_hi_watermarks_bypass_repcnt_hi_watermark_re = addr_hit[15] && reg_re;
+
+ assign adaptp_hi_watermarks_fips_adaptp_hi_watermark_re = addr_hit[16] && reg_re;
+
+ assign adaptp_hi_watermarks_bypass_adaptp_hi_watermark_re = addr_hit[16] && reg_re;
+
+ assign adaptp_lo_watermarks_fips_adaptp_lo_watermark_re = addr_hit[17] && reg_re;
+
+ assign adaptp_lo_watermarks_bypass_adaptp_lo_watermark_re = addr_hit[17] && reg_re;
+
+ assign bucket_hi_watermarks_fips_bucket_hi_watermark_re = addr_hit[18] && reg_re;
+
+ assign bucket_hi_watermarks_bypass_bucket_hi_watermark_re = addr_hit[18] && reg_re;
+
+ assign markov_hi_watermarks_fips_markov_hi_watermark_re = addr_hit[19] && reg_re;
+
+ assign markov_hi_watermarks_bypass_markov_hi_watermark_re = addr_hit[19] && reg_re;
+
+ assign repcnt_total_fails_re = addr_hit[20] && reg_re;
+
+ assign adaptp_hi_total_fails_re = addr_hit[21] && reg_re;
+
+ assign adaptp_lo_total_fails_re = addr_hit[22] && reg_re;
+
+ assign bucket_total_fails_re = addr_hit[23] && reg_re;
+
+ assign markov_total_fails_re = addr_hit[24] && reg_re;
+
+ assign alert_threshold_we = addr_hit[25] & reg_we & ~wr_err;
+ assign alert_threshold_wd = reg_wdata[3:0];
+
+ assign alert_fail_counts_any_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_repcnt_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_adaptp_hi_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_adaptp_lo_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_bucket_fail_count_re = addr_hit[26] && reg_re;
+
+ assign alert_fail_counts_markov_fail_count_re = addr_hit[26] && reg_re;
+
+ assign debug_status_entropy_fifo_depth_re = addr_hit[27] && reg_re;
+
+ assign debug_status_diag_re = addr_hit[27] && reg_re;
+
+ assign seed_we = addr_hit[28] & reg_we & ~wr_err;
+ assign seed_wd = reg_wdata[3:0];
// Read data return
always_comb begin
@@ -1029,78 +1792,152 @@
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = intr_state_es_entropy_valid_qs;
- reg_rdata_next[1] = intr_state_es_rct_failed_qs;
- reg_rdata_next[2] = intr_state_es_apt_failed_qs;
- reg_rdata_next[3] = intr_state_es_fifo_err_qs;
+ reg_rdata_next[1] = intr_state_es_health_test_failed_qs;
+ reg_rdata_next[2] = intr_state_es_fifo_err_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = intr_enable_es_entropy_valid_qs;
- reg_rdata_next[1] = intr_enable_es_rct_failed_qs;
- reg_rdata_next[2] = intr_enable_es_apt_failed_qs;
- reg_rdata_next[3] = intr_enable_es_fifo_err_qs;
+ reg_rdata_next[1] = intr_enable_es_health_test_failed_qs;
+ reg_rdata_next[2] = intr_enable_es_fifo_err_qs;
end
addr_hit[2]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
reg_rdata_next[2] = '0;
- reg_rdata_next[3] = '0;
end
addr_hit[3]: begin
- reg_rdata_next[0] = es_regen_qs;
+ reg_rdata_next[0] = regen_qs;
end
addr_hit[4]: begin
- reg_rdata_next[7:0] = es_rev_abi_revision_qs;
- reg_rdata_next[15:8] = es_rev_hw_revision_qs;
- reg_rdata_next[23:16] = es_rev_chip_type_qs;
+ reg_rdata_next[7:0] = rev_abi_revision_qs;
+ reg_rdata_next[15:8] = rev_hw_revision_qs;
+ reg_rdata_next[23:16] = rev_chip_type_qs;
end
addr_hit[5]: begin
- reg_rdata_next[1:0] = es_conf_enable_qs;
- reg_rdata_next[4] = es_conf_rng_src_en_qs;
- reg_rdata_next[5] = es_conf_rct_en_qs;
- reg_rdata_next[6] = es_conf_apt_en_qs;
- reg_rdata_next[8] = es_conf_rng_bit_en_qs;
- reg_rdata_next[10:9] = es_conf_rng_bit_sel_qs;
+ reg_rdata_next[1:0] = conf_enable_qs;
+ reg_rdata_next[3] = conf_boot_bypass_disable_qs;
+ reg_rdata_next[4] = conf_repcnt_disable_qs;
+ reg_rdata_next[5] = conf_adaptp_disable_qs;
+ reg_rdata_next[6] = conf_bucket_disable_qs;
+ reg_rdata_next[7] = conf_markov_disable_qs;
+ reg_rdata_next[8] = conf_health_test_clr_qs;
+ reg_rdata_next[9] = conf_rng_bit_en_qs;
+ reg_rdata_next[11:10] = conf_rng_bit_sel_qs;
end
addr_hit[6]: begin
- reg_rdata_next[15:0] = es_rct_health_qs;
+ reg_rdata_next[15:0] = rate_qs;
end
addr_hit[7]: begin
- reg_rdata_next[15:0] = es_apt_health_apt_max_qs;
- reg_rdata_next[31:16] = es_apt_health_apt_win_qs;
+ reg_rdata_next[0] = entropy_control_es_route_qs;
+ reg_rdata_next[1] = entropy_control_es_type_qs;
end
addr_hit[8]: begin
- reg_rdata_next[31:0] = es_entropy_qs;
+ reg_rdata_next[31:0] = entropy_data_qs;
end
addr_hit[9]: begin
- reg_rdata_next[2:0] = es_fifo_status_dig_src_depth_qs;
- reg_rdata_next[6:4] = es_fifo_status_hwif_depth_qs;
- reg_rdata_next[16:12] = es_fifo_status_es_depth_qs;
- reg_rdata_next[31] = es_fifo_status_diag_qs;
+ reg_rdata_next[15:0] = health_test_windows_fips_window_qs;
+ reg_rdata_next[31:16] = health_test_windows_bypass_window_qs;
end
addr_hit[10]: begin
- reg_rdata_next[2:0] = es_fdepthst_qs;
+ reg_rdata_next[15:0] = repcnt_thresholds_fips_repcnt_thresh_qs;
+ reg_rdata_next[31:16] = repcnt_thresholds_bypass_repcnt_thresh_qs;
end
addr_hit[11]: begin
- reg_rdata_next[2:0] = es_thresh_qs;
+ reg_rdata_next[15:0] = adaptp_hi_thresholds_fips_adaptp_hi_thresh_qs;
+ reg_rdata_next[31:16] = adaptp_hi_thresholds_bypass_adaptp_hi_thresh_qs;
end
addr_hit[12]: begin
- reg_rdata_next[15:0] = es_rate_qs;
+ reg_rdata_next[15:0] = adaptp_lo_thresholds_fips_adaptp_lo_thresh_qs;
+ reg_rdata_next[31:16] = adaptp_lo_thresholds_bypass_adaptp_lo_thresh_qs;
end
addr_hit[13]: begin
- reg_rdata_next[3:0] = es_seed_qs;
+ reg_rdata_next[15:0] = bucket_thresholds_fips_bucket_thresh_qs;
+ reg_rdata_next[31:16] = bucket_thresholds_bypass_bucket_thresh_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[15:0] = markov_thresholds_fips_markov_thresh_qs;
+ reg_rdata_next[31:16] = markov_thresholds_bypass_markov_thresh_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[15:0] = repcnt_hi_watermarks_fips_repcnt_hi_watermark_qs;
+ reg_rdata_next[31:16] = repcnt_hi_watermarks_bypass_repcnt_hi_watermark_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[15:0] = adaptp_hi_watermarks_fips_adaptp_hi_watermark_qs;
+ reg_rdata_next[31:16] = adaptp_hi_watermarks_bypass_adaptp_hi_watermark_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[15:0] = adaptp_lo_watermarks_fips_adaptp_lo_watermark_qs;
+ reg_rdata_next[31:16] = adaptp_lo_watermarks_bypass_adaptp_lo_watermark_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[15:0] = bucket_hi_watermarks_fips_bucket_hi_watermark_qs;
+ reg_rdata_next[31:16] = bucket_hi_watermarks_bypass_bucket_hi_watermark_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[15:0] = markov_hi_watermarks_fips_markov_hi_watermark_qs;
+ reg_rdata_next[31:16] = markov_hi_watermarks_bypass_markov_hi_watermark_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[31:0] = repcnt_total_fails_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[31:0] = adaptp_hi_total_fails_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[31:0] = adaptp_lo_total_fails_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[31:0] = bucket_total_fails_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[31:0] = markov_total_fails_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[3:0] = alert_threshold_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[3:0] = alert_fail_counts_any_fail_count_qs;
+ reg_rdata_next[7:4] = alert_fail_counts_repcnt_fail_count_qs;
+ reg_rdata_next[11:8] = alert_fail_counts_adaptp_hi_fail_count_qs;
+ reg_rdata_next[15:12] = alert_fail_counts_adaptp_lo_fail_count_qs;
+ reg_rdata_next[19:16] = alert_fail_counts_bucket_fail_count_qs;
+ reg_rdata_next[23:20] = alert_fail_counts_markov_fail_count_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[1:0] = debug_status_entropy_fifo_depth_qs;
+ reg_rdata_next[31] = debug_status_diag_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[3:0] = seed_qs;
end
default: begin
diff --git a/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv
new file mode 100755
index 0000000..7ace6b7
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv
@@ -0,0 +1,114 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src repetitive count health test module
+//
+
+module entropy_src_repcnt_ht #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned RngBusWidth = 4
+) (
+ input clk_i,
+ input rst_ni,
+
+ // ins req interface
+ input logic [RngBusWidth-1:0] entropy_bit_i,
+ input logic entropy_bit_vld_i,
+ input logic clear_i,
+ input logic active_i,
+ input logic [RegWidth-1:0] thresh_i,
+ input logic [RegWidth-1:0] window_i,
+ output logic [RegWidth-1:0] test_cnt_o,
+ output logic test_done_pulse_o,
+ output logic test_fail_pulse_o
+);
+
+ // signals
+ logic window_cntr_wrap;
+ logic [RngBusWidth-1:0] samples_match_pulse;
+ logic [RngBusWidth-1:0] samples_no_match_pulse;
+ logic [RngBusWidth-1:0] rep_cnt_fail;
+
+ // flops
+ logic [RngBusWidth-1:0] prev_sample_q, prev_sample_d;
+ logic [RegWidth-1:0] rep_cntr_q[RngBusWidth], rep_cntr_d[RngBusWidth];
+ logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
+ logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ prev_sample_q <= '0;
+ rep_cntr_q <= {{RegWidth{1'b0}},{RegWidth{1'b0}},
+ {RegWidth{1'b0}},{RegWidth{1'b0}}};
+ window_cntr_q <= '0;
+ test_cnt_q <= '0;
+ end else begin
+ prev_sample_q <= prev_sample_d;
+ rep_cntr_q <= rep_cntr_d;
+ window_cntr_q <= window_cntr_d;
+ test_cnt_q <= test_cnt_d;
+ end
+
+
+ // Repetitive Count Test
+ //
+ // Test operation
+ // This test will look for catastrophic stuck bit failures. The rep_cntr
+ // uses zero as the starting value, differing from the NIST value of one.
+
+
+ genvar sh;
+ generate
+ for (sh = 0; sh < RngBusWidth; sh = sh+1) begin : gen_cntrs
+
+ // NIST A sample
+ assign prev_sample_d[sh] =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? entropy_bit_i[sh] :
+ prev_sample_q[sh];
+
+ assign samples_match_pulse[sh] = entropy_bit_vld_i &&
+ (prev_sample_q[sh] == entropy_bit_i[sh]);
+ assign samples_no_match_pulse[sh] = entropy_bit_vld_i &&
+ (prev_sample_q[sh] != entropy_bit_i[sh]);
+
+ // NIST B counter
+ assign rep_cntr_d[sh] =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ samples_match_pulse[sh] ? (rep_cntr_q[sh]+1) :
+ samples_no_match_pulse[sh] ? '0 :
+ rep_cntr_q[sh];
+
+ assign rep_cnt_fail[sh] = (rep_cntr_q[sh] >= thresh_i);
+
+ end
+ endgenerate
+
+
+ // Window wrap condition
+ assign window_cntr_wrap = (window_cntr_q == window_i);
+
+ // Window counter
+ assign window_cntr_d =
+ clear_i ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i ? (window_cntr_q+1) :
+ window_cntr_q;
+
+ // Test event counter
+ assign test_cnt_d =
+ (!active_i || clear_i) ? '0 :
+ window_cntr_wrap ? '0 :
+ entropy_bit_vld_i && (|rep_cnt_fail) ? (test_cnt_q+1) :
+ test_cnt_q;
+
+ // the pulses will be only one clock in length
+ assign test_fail_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > '0);
+ assign test_done_pulse_o = window_cntr_wrap;
+ assign test_cnt_o = test_cnt_q;
+
+
+endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_shtests.sv b/hw/ip/entropy_src/rtl/entropy_src_shtests.sv
deleted file mode 100755
index 7c3cd0e..0000000
--- a/hw/ip/entropy_src/rtl/entropy_src_shtests.sv
+++ /dev/null
@@ -1,138 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: entropy_src health tests module
-//
-
-module entropy_src_shtests (
- input clk_i,
- input rst_ni,
-
- // ins req interface
- input logic entropy_bit_i,
- input logic entropy_bit_vld_i,
- input logic rct_active_i,
- input logic [15:0] rct_max_cnt_i,
- input logic apt_active_i,
- input logic [15:0] apt_max_cnt_i,
- input logic [15:0] apt_window_i,
- output logic rct_fail_pls_o,
- output logic apt_fail_pls_o,
- output logic shtests_passing_o
-);
-
- // signals
- logic rct_samples_match;
- logic rct_fail;
- logic rct_pass;
- logic apt_reset_test;
- logic apt_samples_match;
- logic apt_fail;
- logic apt_pass;
-
-
- // flops
- logic rct_prev_sample_q, rct_prev_sample_d;
- logic [15:0] rct_rep_cntr_q, rct_rep_cntr_d;
- logic apt_initial_sample_q, apt_initial_sample_d;
- logic [15:0] apt_sample_cntr_q, apt_sample_cntr_d;
- logic [15:0] apt_match_cntr_q, apt_match_cntr_d;
- logic rct_passing_q, rct_passing_d;
- logic apt_passing_q, apt_passing_d;
-
- always_ff @(posedge clk_i or negedge rst_ni)
- if (!rst_ni) begin
- rct_prev_sample_q <= '0;
- rct_rep_cntr_q <= '0;
- apt_initial_sample_q <= '0;
- apt_sample_cntr_q <= '0;
- apt_match_cntr_q <= '0;
- rct_passing_q <= '0;
- apt_passing_q <= '0;
- end else begin
- rct_prev_sample_q <= rct_prev_sample_d;
- rct_rep_cntr_q <= rct_rep_cntr_d;
- apt_initial_sample_q <= apt_initial_sample_d;
- apt_sample_cntr_q <= apt_sample_cntr_d;
- apt_match_cntr_q <= apt_match_cntr_d;
- rct_passing_q <= rct_passing_d;
- apt_passing_q <= apt_passing_d;
- end
-
-
-
- // Repetition Count Test (RCT)
- //
- // Point of test
- // check for back to back patterns up to a
- // limit, fail if it does
-
-
- // NIST A sample
- assign rct_prev_sample_d = ~rct_active_i ? 1'b0 :
- (entropy_bit_vld_i & (rct_rep_cntr_q == 16'h0001)) ? entropy_bit_i :
- rct_prev_sample_q;
-
- assign rct_samples_match = (rct_prev_sample_q == (entropy_bit_vld_i & entropy_bit_i));
-
- // NIST B counter
- assign rct_rep_cntr_d =
- ~rct_active_i ? 16'h0001 :
- rct_fail ? 16'h0001 :
- (entropy_bit_vld_i & rct_samples_match) ? (rct_rep_cntr_q+1) :
- rct_pass ? 16'h0001 :
- rct_rep_cntr_q;
-
- assign rct_pass = rct_active_i & (entropy_bit_vld_i & ~rct_samples_match);
- assign rct_fail = rct_active_i & (rct_rep_cntr_q >= rct_max_cnt_i);
- assign rct_fail_pls_o = rct_fail;
-
- assign rct_passing_d =
- ~rct_active_i ? 1'b1 :
- rct_fail ? 1'b0 :
- rct_pass ? 1'b1 :
- rct_passing_q;
-
-
- // Adaptive Proportion Test (APT)
- //
- // Point of test
- // sample once, then check for period of time if
- // that pattern appears again, fail if it does
-
-
- // NIST N value
- assign apt_reset_test = ~apt_active_i | apt_fail | (apt_sample_cntr_q >= apt_window_i);
-
- // NIST A counter
- assign apt_initial_sample_d =
- ((apt_sample_cntr_q == 16'h0000) & entropy_bit_vld_i) ? entropy_bit_i :
- apt_initial_sample_q;
-
- // NIST S counter
- assign apt_sample_cntr_d = apt_reset_test ? 16'b0 :
- entropy_bit_vld_i ? (apt_sample_cntr_q+1) :
- apt_sample_cntr_q;
-
- assign apt_samples_match = entropy_bit_vld_i & (apt_initial_sample_q == entropy_bit_i);
-
- // NIST B counter
- assign apt_match_cntr_d = apt_reset_test ? 16'b0 :
- (entropy_bit_vld_i & apt_samples_match) ? (apt_match_cntr_q+1) :
- apt_match_cntr_q;
-
- assign apt_pass = (apt_sample_cntr_q >= apt_window_i);
- assign apt_fail = apt_active_i & (apt_match_cntr_q >= apt_max_cnt_i);
- assign apt_fail_pls_o = apt_fail;
-
- assign apt_passing_d =
- ~apt_active_i ? 1'b1 :
- apt_fail ? 1'b0 :
- apt_pass ? 1'b1 :
- apt_passing_q;
-
- // tests summary
- assign shtests_passing_o = rct_passing_q && apt_passing_q;
-
-endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv b/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv
new file mode 100755
index 0000000..577e5d7
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv
@@ -0,0 +1,55 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src high or how watermark register module
+//
+
+module entropy_src_watermark_reg #(
+ parameter int unsigned RegWidth = 16,
+ parameter int unsigned HighWatermark = 1
+) (
+ input logic clk_i,
+ input logic rst_ni,
+
+ // functional interface
+ input logic clear_i,
+ input logic active_i,
+ input logic event_i,
+ input logic [RegWidth-1:0] value_i,
+ output logic [RegWidth-1:0] value_o
+);
+
+ // signals
+ logic [RegWidth-1:0] event_cntr_change;
+
+ // flops
+ logic [RegWidth-1:0] event_cntr_q, event_cntr_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ event_cntr_q <= '0;
+ end else begin
+ event_cntr_q <= event_cntr_d;
+ end
+
+ assign event_cntr_d = (!active_i || clear_i) ? '0 :
+ event_i ? event_cntr_change :
+ event_cntr_q;
+
+ generate
+ if (HighWatermark) begin : gen_hi_wm
+
+ assign event_cntr_change = (value_i > event_cntr_q) ? (value_i) : event_cntr_q;
+
+ end else begin : gen_lo_wm
+
+ assign event_cntr_change = (value_i < event_cntr_q) ? (value_i) : event_cntr_q;
+
+ end
+ endgenerate
+
+ // drive output
+ assign value_o = event_cntr_q;
+
+endmodule
diff --git a/hw/ip/prim/doc/prim_packer_fifo.md b/hw/ip/prim/doc/prim_packer_fifo.md
new file mode 100644
index 0000000..95e5eaa
--- /dev/null
+++ b/hw/ip/prim/doc/prim_packer_fifo.md
@@ -0,0 +1,67 @@
+---
+title: "Primitive Component: Packer FIFO"
+---
+
+# Overview
+
+`prim_packer_fifo` is a module that supports three modes of operation: packing,
+unpacking, and single depth FIFO modes. Packing mode is where the input
+data width is less than the output data width. Unpacking mode is where the input
+data width is greater than the output data width. Single depth FIFO is where
+the input and output data widths are the same. Because masking options are not
+supported, the larger data size must be an even multiple of the smaller size.
+The controls for this module are modeled after the `prim_fifo_sync` module,
+both in name and functional behavior.
+It is one of a set of shared primitive modules
+available for use within OpenTitan as referred to in the Comportability
+Specification section on shared primitives.
+
+## Parameters
+
+Name | type | Description
+-----|------|-------------
+InW | int | Input data width
+OutW | int | Output data width
+
+## Signal Interfaces
+
+Name | In/Out | Description
+-------------|--------|-------------
+clk_i | input | Input clock
+rst_ni | input | Input reset, negative active
+clr_i | input | Input clear, clears all internal flops.
+wvalid_i | input | Writes data into the first available position.
+wdata_i[InW] | input | Input data.
+wready_o | output | Indicates if prim_packer_fifo is able to accept data.
+rvalid_o | output | Indicates if output data is valid.
+rdata_o[OutW]| output | Output data.
+rready_i | input | Output data is popped from the FIFO.
+depth_o | output | Indicates the fullness of the FIFO.
+
+# Theory of Opeations
+
+```code
+ /----------\
+wvalid_i | | rvalid_o
+---------->| |--------------->
+wdata_i | Flop | rdata_o
+=====/====>| FIFO |=======/=======>
+ [InW] | | [OutW]
+ | | depth_o
+ | |--------------->
+wready_o | | rready_i
+<----------| |<---------------
+ | |
+ \----------/
+```
+
+In pack mode, `prim_packer_fifo` accepts `InW` bits of data. On a `wvalid_i`/
+`wready_o` handshake, `wdata_i` is stored to internal registers and accumulated
+until `OutW` data has been gathered. Once the FIFO is full, a single pop (when
+rvalid_o and rready_i are coincident), will clear the data and depth values on
+the next clock cycle. The complimentary flow occurs when the`prim_packer_fifo`
+module is in unpack mode.
+
+The internal register size is the greate of `InW` and `OutW` bits.
+Timing diagrams are shown in the header of the `prim_packer_fifo` module.
+
diff --git a/hw/ip/prim/prim.core b/hw/ip/prim/prim.core
index e81142f..e802a83 100644
--- a/hw/ip/prim/prim.core
+++ b/hw/ip/prim/prim.core
@@ -36,6 +36,7 @@
- rtl/prim_sync_reqack.sv
- rtl/prim_keccak.sv
- rtl/prim_packer.sv
+ - rtl/prim_packer_fifo.sv
- rtl/prim_cipher_pkg.sv
- rtl/prim_present.sv
- rtl/prim_prince.sv
diff --git a/hw/ip/prim/rtl/prim_packer.sv b/hw/ip/prim/rtl/prim_packer.sv
index 12520e5..ceb7bbc 100644
--- a/hw/ip/prim/rtl/prim_packer.sv
+++ b/hw/ip/prim/rtl/prim_packer.sv
@@ -87,7 +87,7 @@
lod_idx = 0;
for (int i = InW-1; i >= 0 ; i--) begin
if (mask_i[i] == 1'b1) begin
- lod_idx = i;
+ lod_idx = $unsigned(i);
end
end
end
diff --git a/hw/ip/prim/rtl/prim_packer_fifo.sv b/hw/ip/prim/rtl/prim_packer_fifo.sv
new file mode 100755
index 0000000..6ffc1a8
--- /dev/null
+++ b/hw/ip/prim/rtl/prim_packer_fifo.sv
@@ -0,0 +1,164 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Supports packed and unpacked modes
+// Uses FIFO timing on the control signals
+// No masking or flush functions supported
+
+// Timings - case where InW < OutW
+// clk_i __|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__
+// wvalid_i _____|~~~~|_____|~~~~|_____|~~~~|_____|~~~~|___________________
+// wdata_i Val N |Val N+1 |Val N+2 |Val N+3 |-------------------
+// wready_o ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|__________|~~~~~~~~
+// rvalid_o ___________________________________________|~~~~~~~~~~|________
+// rdata_o -------------------------------------------|Val |--------
+// rready_i _________________________________________________|~~~~|________
+// depth_o 0000000000|1111111111|2222222222|3333333333|4444444444|00000000
+
+
+// Timings - case where InW > OutW
+// clk_i __|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__
+// wvalid_i _____|~~~~|____________________________________________________
+// wdata_i -----|Val |----------------------------------------------------
+// wready_o ~~~~~~~~~~|___________________________________________|~~~~~~~~
+// rvalid_o __________|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|________
+// rdata_o ----------|Val N |Val N+1 |Val N+2 |Val N+3 |--------
+// rready_i ________________|~~~~|_____|~~~~|_____|~~~~|_____|~~~~|________
+// depth_o 0000000000|4444444444|3333333333|2222222222|1111111111|00000000
+
+
+// Timings - case where InW = OutW
+// clk_i __|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__
+// wvalid_i _____|~~~~|____________________________________________________
+// wdata_i -----|Val |----------------------------------------------------
+// wready_o ~~~~~~~~~~|__________|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+// rvalid_o __________|~~~~~~~~~~|_________________________________________
+// rdata_o ----------|Val |-----------------------------------------
+// rready_i ________________|~~~~|_________________________________________
+// depth_o 0000000000|1111111111|00000000000000000000000000000000000000000
+
+
+`include "prim_assert.sv"
+
+module prim_packer_fifo #(
+ parameter int InW = 32,
+ parameter int OutW = 8,
+ // derived parameters
+ localparam int MaxW = (InW > OutW) ? InW : OutW,
+ localparam int MinW = (InW < OutW) ? InW : OutW,
+// localparam int DepthW = $clog2(MaxW/MinW) + ~|$clog2(MaxW/MinW)
+ localparam int DepthW = $clog2(MaxW/MinW)
+) (
+ input logic clk_i ,
+ input logic rst_ni,
+
+ input logic clr_i,
+ input logic wvalid_i,
+ input logic [InW-1:0] wdata_i,
+ output logic wready_o,
+
+ output logic rvalid_o,
+ output logic [OutW-1:0] rdata_o,
+ input logic rready_i,
+ output logic [DepthW:0] depth_o
+);
+
+
+ // signals
+ logic load_data;
+ logic clear_data;
+
+ // flops
+ logic [DepthW:0] depth_q, depth_d;
+ logic [MaxW-1:0] data_q, data_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ depth_q <= '0;
+ data_q <= '0;
+ end else begin
+ depth_q <= depth_d;
+ data_q <= data_d;
+ end
+ end
+
+ assign depth_o = depth_q;
+
+ generate
+ if (InW < OutW) begin : g_pack_mode
+ logic [MaxW-1:0] wdata_shifted;
+
+ assign wdata_shifted = wdata_i << (depth_q*InW);
+ assign clear_data = (rready_i && rvalid_o) || clr_i;
+ assign load_data = wvalid_i && wready_o;
+
+ assign depth_d = clear_data ? '0 :
+ load_data ? depth_q+1 :
+ depth_q;
+
+ assign data_d = clear_data ? '0 :
+ load_data ? (data_q | wdata_shifted) :
+ data_q;
+
+ // set outputs
+ assign wready_o = !(depth_q == (MaxW/MinW));
+ assign rdata_o = data_q;
+ assign rvalid_o = (depth_q == (MaxW/MinW));
+
+ end else begin : g_unpack_mode
+ logic [MaxW-1:0] rdata_shifted; // ri lint_check_waive NOT_READ
+ logic pull_data;
+ logic [DepthW-1:0] ptr_q, ptr_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ ptr_q <= '0;
+ end else begin
+ ptr_q <= ptr_d;
+ end
+ end
+
+ assign rdata_shifted = data_q >> ptr_q*OutW;
+ assign clear_data = (rready_i && (depth_q == {{DepthW{1'b0}},1'b1})) || clr_i;
+ assign load_data = wvalid_i && wready_o;
+ assign pull_data = rvalid_o && rready_i;
+
+ assign depth_d = clear_data ? '0 :
+ load_data ? {1'b1,{DepthW{1'b0}}} :
+ pull_data ? depth_q-1 :
+ depth_q;
+
+ assign ptr_d = clear_data ? '0 :
+ pull_data ? ptr_q+1 :
+ ptr_q;
+
+ assign data_d = clear_data ? '0 :
+ load_data ? wdata_i :
+ data_q;
+
+ // set outputs
+ assign wready_o = (depth_q == '0);
+ assign rdata_o = rdata_shifted[OutW-1:0];
+ assign rvalid_o = !(depth_q == '0);
+
+ end
+ endgenerate
+
+
+
+ //////////////////////////////////////////////
+ // Assertions, Assumptions, and Coverpoints //
+ //////////////////////////////////////////////
+
+ // If not acked, valid_o should keep asserting
+ `ASSERT(ValidOPairedWidthReadyI_A,
+ rvalid_o && !rready_i |=> rvalid_o)
+
+ // If output port doesn't accept the data, the data should be stable
+ `ASSERT(DataOStableWhenPending_A,
+ ##1 rvalid_o && $past(rvalid_o)
+ && !$past(rready_i) |-> $stable(rdata_o))
+
+
+endmodule
diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
index aac538b..c5bf2fc 100644
--- a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
+++ b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
@@ -11,7 +11,7 @@
"{proj_root}/hw/data/common_project_cfg.hjson"]
use_cfgs: ["{proj_root}/hw/ip/aes/dv/aes_sim_cfg.hjson",
- "{proj_root}/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson",
+// "{proj_root}/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson",
"{proj_root}/hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson",
"{proj_root}/hw/ip/gpio/dv/gpio_sim_cfg.hjson",
"{proj_root}/hw/ip/hmac/dv/hmac_sim_cfg.hjson",
