[csrng/rtl] bug fix for cmds with additional data
Changing the main csrng state machine to treat all app interface commands as if they provided additional data.
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/csrng/rtl/csrng_core.sv b/hw/ip/csrng/rtl/csrng_core.sv
index 0dac1dd..af006d7 100644
--- a/hw/ip/csrng/rtl/csrng_core.sv
+++ b/hw/ip/csrng/rtl/csrng_core.sv
@@ -62,6 +62,9 @@
localparam int BlkEncArbWidth = KeyLen+BlkLen+StateId+Cmd;
localparam int NUpdateArbReqs = 2;
localparam int UpdateArbWidth = KeyLen+BlkLen+SeedLen+StateId+Cmd;
+ localparam int MaxClen = 12;
+ localparam int ADataDepthWidth = SeedLen/AppCmdWidth;
+ localparam unsigned ADataDepthClog = $clog2(ADataDepthWidth)+1;
// signals
// interrupt signals
@@ -91,6 +94,9 @@
logic [AppCmdWidth-1:0] acmd_bus;
logic [SeedLen-1:0] packer_adata;
+ logic [ADataDepthClog-1:0] packer_adata_depth;
+ logic packer_adata_pop;
+ logic packer_adata_clr;
logic [SeedLen-1:0] seed_diversification;
logic cmd_entropy_req;
@@ -133,6 +139,7 @@
logic generate_req;
logic update_req;
logic uninstant_req;
+ logic clr_adata_packer;
logic [Cmd-1:0] ctr_drbg_cmd_ccmd;
logic ctr_drbg_cmd_req;
logic ctr_drbg_gen_req;
@@ -330,7 +337,6 @@
logic cmd_req_dly_q, cmd_req_dly_d;
logic [Cmd-1:0] cmd_req_ccmd_dly_q, cmd_req_ccmd_dly_d;
logic cs_aes_halt_q, cs_aes_halt_d;
- logic packer_adata_pop_q, packer_adata_pop_d;
logic [SeedLen-1:0] entropy_src_seed_q, entropy_src_seed_d;
logic entropy_src_fips_q, entropy_src_fips_d;
@@ -346,7 +352,6 @@
cmd_req_dly_q <= '0;
cmd_req_ccmd_dly_q <= '0;
cs_aes_halt_q <= '0;
- packer_adata_pop_q <= '0;
entropy_src_seed_q <= '0;
entropy_src_fips_q <= '0;
end else begin
@@ -360,7 +365,6 @@
cmd_req_dly_q <= cmd_req_dly_d;
cmd_req_ccmd_dly_q <= cmd_req_ccmd_dly_d;
cs_aes_halt_q <= cs_aes_halt_d;
- packer_adata_pop_q <= packer_adata_pop_d;
entropy_src_seed_q <= entropy_src_seed_d;
entropy_src_fips_q <= entropy_src_fips_d;
end
@@ -860,6 +864,7 @@
.generate_req_o(generate_req),
.update_req_o(update_req),
.uninstant_req_o(uninstant_req),
+ .clr_adata_packer_o(clr_adata_packer),
.cmd_complete_i(state_db_wr_req),
.main_sm_err_o(main_sm_err)
);
@@ -891,22 +896,21 @@
) u_prim_packer_fifo_adata (
.clk_i (clk_i),
.rst_ni (rst_ni),
- .clr_i (!cs_enable || packer_adata_pop_q),
+ .clr_i (!cs_enable || packer_adata_clr),
.wvalid_i (acmd_mop),
.wdata_i (acmd_bus),
.wready_o (),
.rvalid_o (),
.rdata_o (packer_adata),
- .rready_i (packer_adata_pop_q),
- .depth_o ()
+ .rready_i (packer_adata_pop),
+ .depth_o (packer_adata_depth)
);
- assign packer_adata_pop_d = cs_enable &&
- ((instant_req && flag0_q) ||
- reseed_req ||
- update_req ||
- uninstant_req ||
- (generate_req && flag0_q));
+ assign packer_adata_pop = cs_enable &&
+ clr_adata_packer && (packer_adata_depth == ADataDepthClog'(MaxClen));
+
+ assign packer_adata_clr = cs_enable &&
+ clr_adata_packer && (packer_adata_depth < ADataDepthClog'(MaxClen));
//-------------------------------------
// csrng_state_db nstantiation
diff --git a/hw/ip/csrng/rtl/csrng_main_sm.sv b/hw/ip/csrng/rtl/csrng_main_sm.sv
index 86aec08..f70ed09 100644
--- a/hw/ip/csrng/rtl/csrng_main_sm.sv
+++ b/hw/ip/csrng/rtl/csrng_main_sm.sv
@@ -25,45 +25,49 @@
output logic generate_req_o,
output logic update_req_o,
output logic uninstant_req_o,
+ output logic clr_adata_packer_o,
input logic cmd_complete_i,
output logic main_sm_err_o
);
// Encoding generated with:
-// $ ./util/design/sparse-fsm-encode.py -d 3 -m 12 -n 8 \
-// -s 2565810189 --language=sv
+// $ ./util/design/sparse-fsm-encode.py -d 3 -m 15 -n 8 \
+// -s 1300573258 --language=sv
//
// Hamming distance histogram:
//
// 0: --
// 1: --
// 2: --
-// 3: |||||||||||||||| (30.30%)
-// 4: |||||||||||||||||||| (37.88%)
-// 5: ||||||||| (18.18%)
-// 6: |||| (9.09%)
-// 7: || (4.55%)
+// 3: |||||||||||||||||| (32.38%)
+// 4: |||||||||||||||||||| (35.24%)
+// 5: |||||||| (15.24%)
+// 6: |||||| (11.43%)
+// 7: ||| (5.71%)
// 8: --
//
// Minimum Hamming distance: 3
// Maximum Hamming distance: 7
-// Minimum Hamming weight: 2
-// Maximum Hamming weight: 6
+// Minimum Hamming weight: 1
+// Maximum Hamming weight: 7
//
localparam int StateWidth = 8;
typedef enum logic [StateWidth-1:0] {
- Idle = 8'b01010011, // idle
- ParseCmd = 8'b01001100, // parse the cmd
- InstantPrep = 8'b00101010, // instantiate prep
- InstantReq = 8'b11011101, // instantiate request (takes adata or entropy)
- ReseedPrep = 8'b10110111, // reseed prep
- ReseedReq = 8'b11001011, // reseed request (takes adata and entropy and Key,V,RC)
- GenerateReq = 8'b10011110, // generate request (takes adata? and Key,V,RC)
- UpdatePrep = 8'b10101001, // update prep
- UpdateReq = 8'b00011001, // update request (takes adata and Key,V,RC)
- UninstantReq = 8'b00000111, // uninstantiate request (no input)
- CmdCompWait = 8'b00010100, // wait for command to complete
- Error = 8'b11110001 // error state, results in fatal alert
+ Idle = 8'b01001110, // idle
+ ParseCmd = 8'b10111011, // parse the cmd
+ InstantPrep = 8'b11000001, // instantiate prep
+ InstantReq = 8'b01010100, // instantiate request (takes adata or entropy)
+ ReseedPrep = 8'b11011101, // reseed prep
+ ReseedReq = 8'b01011011, // reseed request (takes adata and entropy and Key,V,RC)
+ GeneratePrep = 8'b11101111, // generate request (takes adata? and Key,V,RC)
+ GenerateReq = 8'b00100100, // generate request (takes adata? and Key,V,RC)
+ UpdatePrep = 8'b00110001, // update prep
+ UpdateReq = 8'b10010000, // update request (takes adata and Key,V,RC)
+ UninstantPrep = 8'b11110110, // uninstantiate prep
+ UninstantReq = 8'b01100011, // uninstantiate request
+ ClrAData = 8'b00000010, // clear out the additional data packer fifo
+ CmdCompWait = 8'b10111100, // wait for command to complete
+ Error = 8'b01111000 // error state, results in fatal alert
} state_e;
state_e state_d, state_q;
@@ -94,6 +98,7 @@
generate_req_o = 1'b0;
update_req_o = 1'b0;
uninstant_req_o = 1'b0;
+ clr_adata_packer_o = 1'b0;
main_sm_err_o = 1'b0;
unique case (state_q)
Idle: begin
@@ -121,16 +126,20 @@
state_d = ReseedPrep;
end
end else if (acmd_i == GEN) begin
- acmd_hdr_capt_o = 1'b1;
- state_d = GenerateReq;
+ if (acmd_eop_i) begin
+ acmd_hdr_capt_o = 1'b1;
+ state_d = GeneratePrep;
+ end
end else if (acmd_i == UPD) begin
if (acmd_eop_i) begin
acmd_hdr_capt_o = 1'b1;
state_d = UpdatePrep;
end
end else if (acmd_i == UNI) begin
- acmd_hdr_capt_o = 1'b1;
- state_d = UninstantReq;
+ if (acmd_eop_i) begin
+ acmd_hdr_capt_o = 1'b1;
+ state_d = UninstantPrep;
+ end
end
end
end
@@ -156,7 +165,7 @@
state_d = Idle;
end else begin
instant_req_o = 1'b1;
- state_d = CmdCompWait;
+ state_d = ClrAData;
end
end
ReseedPrep: begin
@@ -175,7 +184,15 @@
state_d = Idle;
end else begin
reseed_req_o = 1'b1;
- state_d = CmdCompWait;
+ state_d = ClrAData;
+ end
+ end
+ GeneratePrep: begin
+ if (!enable_i) begin
+ state_d = Idle;
+ end else begin
+ // assumes all adata is present now
+ state_d = GenerateReq;
end
end
GenerateReq: begin
@@ -183,7 +200,7 @@
state_d = Idle;
end else begin
generate_req_o = 1'b1;
- state_d = CmdCompWait;
+ state_d = ClrAData;
end
end
UpdatePrep: begin
@@ -199,7 +216,15 @@
state_d = Idle;
end else begin
update_req_o = 1'b1;
- state_d = CmdCompWait;
+ state_d = ClrAData;
+ end
+ end
+ UninstantPrep: begin
+ if (!enable_i) begin
+ state_d = Idle;
+ end else begin
+ // assumes all adata is present now
+ state_d = UninstantReq;
end
end
UninstantReq: begin
@@ -207,6 +232,14 @@
state_d = Idle;
end else begin
uninstant_req_o = 1'b1;
+ state_d = ClrAData;
+ end
+ end
+ ClrAData: begin
+ if (!enable_i) begin
+ state_d = Idle;
+ end else begin
+ clr_adata_packer_o = 1'b1;
state_d = CmdCompWait;
end
end
