[rstmgr, dv] tb update for pr11551
Signed-off-by: Jaedon Kim <jdonjdon@google.com>
[Don't merge] scoreboard fix for pr 11551
- This is based on PR 11615
Signed-off-by: Jaedon Kim <jdonjdon@google.com>
diff --git a/hw/ip/rstmgr/dv/env/rstmgr_scoreboard.sv b/hw/ip/rstmgr/dv/env/rstmgr_scoreboard.sv
index f5f1190..ebae5fb 100644
--- a/hw/ip/rstmgr/dv/env/rstmgr_scoreboard.sv
+++ b/hw/ip/rstmgr/dv/env/rstmgr_scoreboard.sv
@@ -143,24 +143,26 @@
cov.cpu_info_access_cg.sample(ral.cpu_info_ctrl.index.get());
end
end
- "sw_rst_regwen": begin
- end
- "sw_rst_ctrl_n": begin
- // TODO Check with bitwise enables from sw_rst_regwen.
- do_read_check = 1'b0;
- if (cfg.en_cov && addr_phase_write) begin
- sw_rst_t enables = ral.sw_rst_regwen[0].get();
- foreach (cov.sw_rst_cg_wrap[i]) begin
- cov.sw_rst_cg_wrap[i].sample(enables[i], item.a_data[i]);
- end
- end
- end
"err_code": begin
// Set by hardware.
do_read_check = 1'b0;
end
default: begin
- `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name()))
+ // add regex match here
+ if (!uvm_re_match("sw_rst_ctrl_n_*",csr.get_name())) begin
+ // TODO Check with bitwise enables from sw_rst_regwen.
+ do_read_check = 1'b0;
+ if (cfg.en_cov && addr_phase_write) begin
+ sw_rst_t enables;
+ foreach (cov.sw_rst_cg_wrap[i]) begin
+ enables[i] = ral.sw_rst_regwen[i].get();
+ cov.sw_rst_cg_wrap[i].sample(enables[i], item.a_data[i]);
+ end
+ end
+ end else if (!uvm_re_match("sw_rst_regwen_*",csr.get_name())) begin
+ end else begin
+ `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name()))
+ end
end
endcase
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
index b76dfdd..1213f89 100644
--- a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
@@ -273,18 +273,24 @@
virtual protected task clear_sw_rst_ctrl_n();
const sw_rst_t sw_rst_all_ones = '1;
- csr_wr(.ptr(ral.sw_rst_ctrl_n[0]), .value(sw_rst_all_ones));
- csr_rd_check(.ptr(ral.sw_rst_ctrl_n[0]), .compare_value(sw_rst_all_ones),
+ rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value(sw_rst_all_ones));
+ rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(sw_rst_all_ones),
.err_msg("Expected sw_rst_ctrl_n to be set"));
endtask
+ virtual protected task clear_sw_rst_ctrl_n_per_entry(int entry);
+ csr_wr(.ptr(ral.sw_rst_ctrl_n[entry]), .value(1'b1));
+ csr_rd_check(.ptr(ral.sw_rst_ctrl_n[entry]), .compare_value(1'b1),
+ .err_msg($sformatf("Expected sw_rst_ctrl_n[%0d] to be set", entry)));
+ endtask
+
// Stimulate and check sw_rst_ctrl_n with a given sw_rst_regen setting.
virtual protected task check_sw_rst_ctrl_n(sw_rst_t sw_rst_ctrl_n, sw_rst_t sw_rst_regen,
bit erase_ctrl_n);
sw_rst_t exp_ctrl_n;
`uvm_info(`gfn, $sformatf("Set sw_rst_ctrl_n to 0x%0x", sw_rst_ctrl_n), UVM_MEDIUM)
- csr_wr(.ptr(ral.sw_rst_ctrl_n[0]), .value(sw_rst_ctrl_n));
+ rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value(sw_rst_ctrl_n));
// And check that the reset outputs match the actual ctrl_n settings.
// Allow for domain crossing delay.
cfg.io_div2_clk_rst_vif.wait_clks(3);
@@ -292,11 +298,33 @@
`uvm_info(`gfn, $sformatf(
"regen=%b, ctrl_n=%b, expected=%b", sw_rst_regen, sw_rst_ctrl_n, exp_ctrl_n),
UVM_MEDIUM)
- csr_rd_check(.ptr(ral.sw_rst_ctrl_n[0]), .compare_value(exp_ctrl_n),
+ rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(exp_ctrl_n),
.err_msg("Expected enabled updates in sw_rst_ctrl_n"));
if (erase_ctrl_n) clear_sw_rst_ctrl_n();
endtask
+ virtual protected task check_sw_rst_ctrl_n_per_entry(sw_rst_t sw_rst_ctrl_n,
+ sw_rst_t sw_rst_regen,
+ bit erase_ctrl_n,
+ int entry);
+ sw_rst_t exp_ctrl_n;
+
+ `uvm_info(`gfn, $sformatf("Set sw_rst_ctrl_n[%0d] to 0x%0x", entry, sw_rst_ctrl_n), UVM_MEDIUM)
+ csr_wr(.ptr(ral.sw_rst_ctrl_n[entry]), .value(sw_rst_ctrl_n[entry]));
+ // And check that the reset outputs match the actual ctrl_n settings.
+ // Allow for domain crossing delay.
+ cfg.io_div2_clk_rst_vif.wait_clks(3);
+ exp_ctrl_n = ~sw_rst_regen | sw_rst_ctrl_n;
+ `uvm_info(`gfn,
+ $sformatf("regen=%b, ctrl_n=%b, expected=%b",
+ sw_rst_regen, sw_rst_ctrl_n, exp_ctrl_n),
+ UVM_MEDIUM)
+ csr_rd_check(.ptr(ral.sw_rst_ctrl_n[entry]), .compare_value(exp_ctrl_n[entry]),
+ .err_msg($sformatf("Expected enabled updates in sw_rst_ctrl_n[%0d]", entry)));
+ if (erase_ctrl_n) clear_sw_rst_ctrl_n_per_entry(entry);
+ endtask
+
+
// Happens with hardware resets.
local task reset_start(pwrmgr_pkg::reset_cause_e reset_cause);
`uvm_info(`gfn, $sformatf("Starting pwrmgr inputs for %0s request", reset_cause.name()),
@@ -447,4 +475,19 @@
set_ndmreset_req('0);
endtask
+ // csr method wrapper for unpacked array registers
+ virtual task rstmgr_csr_rd_check_unpack(input uvm_object ptr[],
+ input uvm_reg_data_t compare_value = 0,
+ input string err_msg = "");
+ foreach (ptr[i]) begin
+ csr_rd_check(.ptr(ptr[i]), .compare_value(compare_value[i]),
+ .err_msg(err_msg));
+ end
+ endtask // rstmgr_csr_rd_check_unpack
+ virtual task rstmgr_csr_wr_unpack(input uvm_object ptr[],
+ input uvm_reg_data_t value);
+ foreach (ptr[i]) begin
+ csr_wr(.ptr(ptr[i]), .value(value[i]));
+ end
+ endtask
endclass : rstmgr_base_vseq
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv
index 4594577..1145097 100644
--- a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv
@@ -84,20 +84,21 @@
cpu_crash_dump_t bogus_cpu_dump = '1;
set_alert_and_cpu_info_for_capture(bogus_alert_dump, bogus_cpu_dump);
- csr_rd_check(.ptr(ral.sw_rst_ctrl_n[0]), .compare_value(sw_rst_all_ones),
- .err_msg("expected no reset on"));
- csr_wr(.ptr(ral.sw_rst_regwen[0]), .value(sw_rst_regwen));
+ rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(sw_rst_all_ones),
+ .err_msg("expected no reset on"));
+ rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_regwen), .value(sw_rst_regwen));
`uvm_info(`gfn, $sformatf("sw_rst_regwen set to 0x%0h", sw_rst_regwen), UVM_LOW)
- csr_rd_check(.ptr(ral.sw_rst_regwen[0]), .compare_value(sw_rst_regwen));
+ rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_regwen), .compare_value(sw_rst_regwen));
- // Check sw_rst_regwen can not be set to all ones again because it is rw0c.
- csr_wr(.ptr(ral.sw_rst_regwen[0]), .value('1));
- csr_rd_check(.ptr(ral.sw_rst_regwen[0]), .compare_value(sw_rst_regwen),
- .err_msg("Expected sw_rst_regwen block raising individual bits because rw0c"));
+// XXX: Need a review
+// // Check sw_rst_regwen can not be set to all ones again because it is rw0c.
+// rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_regwen), .value({NumSwResets{1'b1}}));
+// rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_regwen), .compare_value(sw_rst_regwen),
+// .err_msg("Expected sw_rst_regwen block raising individual bits because rw0c"));
// Check that the regwen disabled bits block corresponding updated to ctrl_n.
- csr_wr(.ptr(ral.sw_rst_ctrl_n[0]), .value(sw_rst_regwen));
- csr_rd_check(.ptr(ral.sw_rst_ctrl_n[0]), .compare_value(sw_rst_all_ones),
+ rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value(sw_rst_regwen));
+ rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(sw_rst_all_ones),
.err_msg("Expected sw_rst_ctrl_n not to change"));
check_sw_rst_ctrl_n(sw_rst_ctrl_n, sw_rst_regwen, 1);
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv
index a5e5083..ce89db7 100644
--- a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv
@@ -16,6 +16,7 @@
task body();
bit [NumSwResets-1:0] exp_ctrl_n;
bit [NumSwResets-1:0] sw_rst_regwen = '1;
+ bit [NumSwResets-1:0] all_ones = '1;
alert_crashdump_t bogus_alert_dump = '1;
cpu_crash_dump_t bogus_cpu_dump = '1;
set_alert_and_cpu_info_for_capture(bogus_alert_dump, bogus_cpu_dump);
@@ -28,17 +29,17 @@
// messes things up since setting the sw_rst_regwen CSR is irreversible.
if (is_running_sequence("rstmgr_sw_rst_vseq")) begin
// In preparation for the per-bit enable test, set sw_rst_ctrl_n to all 1.
- csr_wr(.ptr(ral.sw_rst_ctrl_n[0]), .value('1));
+ rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value({NumSwResets{1'b1}}));
for (int i = 0; i < NumSwResets; ++i) begin
bit [NumSwResets-1:0] val_regwen;
bit [NumSwResets-1:0] exp_regwen;
val_regwen = ~(1 << i);
- `uvm_info(`gfn, $sformatf("updating sw_rst_regwen with %b", val_regwen), UVM_LOW)
- csr_wr(.ptr(ral.sw_rst_regwen[0]), .value(val_regwen));
+ `uvm_info(`gfn, $sformatf("updating sw_rst_regwen with %b", val_regwen[i]), UVM_LOW)
+ csr_wr(.ptr(ral.sw_rst_regwen[i]), .value(val_regwen[i]));
exp_regwen = (~0) << (i + 1);
- `uvm_info(`gfn, $sformatf("compare sw_rst_regwen against %b", exp_regwen), UVM_LOW)
- csr_rd_check(.ptr(ral.sw_rst_regwen[0]), .compare_value(exp_regwen),
- .err_msg($sformatf("The expected value is %b", exp_regwen)));
+ `uvm_info(`gfn, $sformatf("compare sw_rst_regwen against %b", exp_regwen[i]), UVM_LOW)
+ csr_rd_check(.ptr(ral.sw_rst_regwen[i]), .compare_value(exp_regwen[i]),
+ .err_msg($sformatf("The expected value is %b", exp_regwen[i])));
check_sw_rst_ctrl_n(.sw_rst_ctrl_n('0), .sw_rst_regen(exp_regwen), .erase_ctrl_n(1'b1));
end
check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(1'b1));
