| commit | 50a83bedd4d6e3af8ef3c3696cf12fdbce53aaad | [log] [tgz] |
|---|---|---|
| author | Mark Branstad <mark.branstad@wdc.com> | Mon Feb 22 10:44:19 2021 -0800 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Sun Feb 28 20:12:26 2021 +0100 |
| tree | 003b0fd5541d47bab291ae1032c129ae5ab017d8 | |
| parent | 64b6d9b7c0143aeeccabb53cf3a3e173962215f4 [diff] |
[csrng/rtl] internal state read timing improvements Re-structed the read flow for the internal state array. Added parameter to prim_fifo_sync to remove output mux. Added simple flops to break up configuration paths. Added fifo output mux back for genbits to prevent assertion. Cleaned up format for hjson file. Updated internal state rtl based on feedback. Fixed hjson register wording. Added comment for FIFO parameter use. Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).