| commit | debce956cd730f4799778457719060402fc90f10 | [log] [tgz] |
|---|---|---|
| author | Philipp Wagner <phw@lowrisc.org> | Mon May 25 16:41:19 2020 +0100 |
| committer | Philipp Wagner <mail@philipp-wagner.com> | Mon May 25 17:15:51 2020 +0100 |
| tree | fcaf657fbbd1c7b904bb5a9dd307daf49082a562 | |
| parent | 5b098350c1099526eb7a3b2056432f306af76de1 [diff] |
[prim_ram_2p] Enable memory loading through Verilator In #2311 we enabled memory loading for memories with sizes != 32 bit. This enables us to remove the previous workaround and enable memory loading also for 2p memories, which are used in OpenTitan with "odd" Width parameters (due to ECC/parity). Signed-off-by: Philipp Wagner <phw@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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