[prim] Restore ability to select default implementation
When we introduced the primitives library, we also had the possibility
to choose a per-design default implementation for primitives. To set a
default implementation, the synthesis script would set the
PRIM_DEFAULT_IMPL define to values like "xilinx" or "generic", which was
then used as default value for the Impl parameter, which is present in
all primitives modules:
```verilog
parameter Impl = `"`PRIM_DEFAULT_IMPL`"
```
Unfortunately, this syntax to "cast" a define to a string isn't
supported in Cadence LEC. As a stop-gap, we removed the functionality
altogether. This resulted in always using the "generic" implementation
for all targets, which produces suboptimal results e.g. on Xilinx FPGAs.
With this commit, the original functionality is restored in a
LEC-compatible way. Instead of using strings for PRIM_DEFAULT_IMPL, we
now use integers. The allowed values are listed in the
prim_pkg::impl_e enum.
Implementation notes on types:
* PRIM_DEFAULT_IMPL is a define passed through to tools as command line
options. Most/all tools only support "primitive" types in this way,
not enums; hence PRIM_DEFAULT_IMPL is an integer, and all assignments
to it must be integer as well. This includes the default assignment:
`ifndef PRIM_DEFAULT_IMPL
`define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
`endif
* Since we assign the PRIM_DEFAULT_IMPL define to the Impl parameter,
this parameter needs to be either an integer, or cast the RHS to an
enum.
* In this implementation we stayed with an integer type for the Impl to
avoid potential problems with tools don't supporting enums as
parameter type. (We don't know of any tool yet that doesn't support
it, but it seems sufficiently exotic to run into problems down the
road.)
Thanks to Tim for an initial version of this code.
Fixes #40
diff --git a/hw/ip/padctrl/fpv/padctrl_fpv.core b/hw/ip/padctrl/fpv/padctrl_fpv.core
index 6726f78..e43445e 100644
--- a/hw/ip/padctrl/fpv/padctrl_fpv.core
+++ b/hw/ip/padctrl/fpv/padctrl_fpv.core
@@ -8,6 +8,7 @@
files_fpv:
depend:
- lowrisc:ip:padctrl
+ - lowrisc:prim:prim_pkg
files:
- tb/padctrl_tb.sv
- tb/padctrl_bind.sv
diff --git a/hw/ip/padctrl/fpv/tb/padctrl_tb.sv b/hw/ip/padctrl/fpv/tb/padctrl_tb.sv
index e4fc0e5..91939b0 100644
--- a/hw/ip/padctrl/fpv/tb/padctrl_tb.sv
+++ b/hw/ip/padctrl/fpv/tb/padctrl_tb.sv
@@ -4,8 +4,12 @@
//
// Testbench module for padctrl. Intended to use with a formal tool.
+`ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
+`endif
+
module padctrl_tb #(
- parameter Impl = "generic"
+ parameter integer Impl = `PRIM_DEFAULT_IMPL
) (
input wire clk_i,
input wire rst_ni,
diff --git a/hw/ip/padctrl/fpv/vip/padctrl_assert.sv b/hw/ip/padctrl/fpv/vip/padctrl_assert.sv
index cadba49..150de48 100644
--- a/hw/ip/padctrl/fpv/vip/padctrl_assert.sv
+++ b/hw/ip/padctrl/fpv/vip/padctrl_assert.sv
@@ -5,8 +5,13 @@
// Assertions for padring. Intended to use with a formal tool.
// Note that only the mandatory pad attributes are tested here.
+
+`ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
+`endif
+
module padctrl_assert #(
- parameter Impl = "generic"
+ parameter integer Impl = `PRIM_DEFAULT_IMPL
) (
input clk_i,
input rst_ni,
@@ -20,6 +25,8 @@
[padctrl_reg_pkg::AttrDw-1:0] dio_attr_o
);
+ import prim_pkg::*;
+
// symbolic vars for FPV
int unsigned mio_sel;
int unsigned dio_sel;
@@ -31,14 +38,14 @@
`ASSUME(NMioRange_M, mio_sel < padctrl_reg_pkg::NMioPads, clk_i, !rst_ni)
`ASSUME(NMioStable_M, ##1 $stable(mio_sel), clk_i, !rst_ni)
- if (Impl == "generic") begin : gen_mio_generic
+ if (impl_e'(Impl) == ImplGeneric) begin : gen_mio_generic
`ASSERT(MioWarl_A, padctrl.reg2hw.mio_pads[mio_sel].qe |=>
!(|padctrl.mio_attr_q[mio_sel][padctrl_reg_pkg::AttrDw-1:6]),
clk_i, !rst_ni)
`ASSERT(MioAttr_A, padctrl.reg2hw.mio_pads[mio_sel].qe |=>
mio_attr_o[mio_sel][5:0] == $past(padctrl.reg2hw.mio_pads[mio_sel].q[5:0]),
clk_i, !rst_ni)
- end else if (Impl == "xilinx") begin : gen_mio_xilinx
+ end else if (impl_e'(Impl) == ImplXilinx) begin : gen_mio_xilinx
`ASSERT(MioWarl_A, padctrl.reg2hw.mio_pads[mio_sel].qe |=>
!(|padctrl.mio_attr_q[mio_sel][padctrl_reg_pkg::AttrDw-1:2]),
clk_i, !rst_ni)
@@ -56,15 +63,14 @@
`ASSUME(NDioRange_M, dio_sel < padctrl_reg_pkg::NDioPads, clk_i, !rst_ni)
`ASSUME(NDioStable_M, ##1 $stable(dio_sel), clk_i, !rst_ni)
-
- if (Impl == "generic") begin : gen_dio_generic
+ if (impl_e'(Impl) == ImplGeneric) begin : gen_dio_generic
`ASSERT(DioWarl_A, padctrl.reg2hw.dio_pads[dio_sel].qe |=>
!(|padctrl.dio_attr_q[dio_sel][padctrl_reg_pkg::AttrDw-1:6]),
clk_i, !rst_ni)
`ASSERT(DioAttr_A, padctrl.reg2hw.dio_pads[dio_sel].qe |=>
dio_attr_o[dio_sel][5:0] == $past(padctrl.reg2hw.dio_pads[dio_sel].q[5:0]),
clk_i, !rst_ni)
- end else if (Impl == "xilinx") begin : gen_dio_xilinx
+ end else if (impl_e'(Impl) == ImplXilinx) begin : gen_dio_xilinx
`ASSERT(DioWarl_A, padctrl.reg2hw.dio_pads[dio_sel].qe |=>
!(|padctrl.dio_attr_q[dio_sel][5:2]),
clk_i, !rst_ni)
diff --git a/hw/ip/padctrl/padctrl.core b/hw/ip/padctrl/padctrl.core
index ef7f112..5b07257 100644
--- a/hw/ip/padctrl/padctrl.core
+++ b/hw/ip/padctrl/padctrl.core
@@ -10,6 +10,7 @@
depend:
- lowrisc:ip:tlul
- lowrisc:prim:all
+ - lowrisc:prim:prim_pkg
files:
- rtl/padctrl_reg_pkg.sv
- rtl/padctrl_reg_top.sv
diff --git a/hw/ip/padctrl/rtl/padctrl.sv b/hw/ip/padctrl/rtl/padctrl.sv
index f4c368f..c6e84ee 100644
--- a/hw/ip/padctrl/rtl/padctrl.sv
+++ b/hw/ip/padctrl/rtl/padctrl.sv
@@ -7,9 +7,13 @@
// to be consumed on the chiplevel.
//
+`ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
+`endif
+
module padctrl #(
- parameter Impl = "generic" // "generic", "xilinx"...
- ) (
+ parameter integer Impl = `PRIM_DEFAULT_IMPL
+) (
input clk_i,
input rst_ni,
// Bus Interface (device)
@@ -22,6 +26,8 @@
[padctrl_reg_pkg::AttrDw-1:0] dio_attr_o
);
+ import prim_pkg::*;
+
//////////////////////////////////////////////////////
// This controls the WARL'ness of the CSRs
// needs to be in line with the corresponding
@@ -29,10 +35,10 @@
//////////////////////////////////////////////////////
logic [padctrl_reg_pkg::AttrDw-1:0] warl_mask;
- if (Impl == "generic") begin : gen_generic
+ if (impl_e'(Impl) == ImplGeneric) begin : gen_generic
// all attributes supported
assign warl_mask = padctrl_reg_pkg::AttrDw'(6'h3F);
- end else if (Impl == "xilinx") begin : gen_xilinx
+ end else if (impl_e'(Impl) == ImplXilinx) begin : gen_xilinx
// only OD and INV supported
assign warl_mask = padctrl_reg_pkg::AttrDw'(2'h3);
end else begin : gen_failure
diff --git a/hw/ip/padctrl/rtl/padring.sv b/hw/ip/padctrl/rtl/padring.sv
index f932229..5e0a96a 100644
--- a/hw/ip/padctrl/rtl/padring.sv
+++ b/hw/ip/padctrl/rtl/padring.sv
@@ -6,8 +6,13 @@
// The module instantiates the technology dependent pads, and connects them
// to the MIOs/DIOs and pad attributes coming from the padctrl block.
//
+
+`ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
+`endif
+
module padring #(
- parameter Impl = "generic" // this determines the pad implementation
+ parameter integer Impl = `PRIM_DEFAULT_IMPL // this determines the pad implementation
) (
// pad input
input wire clk_pad_i,
diff --git a/hw/ip/prim/abstract/prim_clock_gating.sv b/hw/ip/prim/abstract/prim_clock_gating.sv
index 9424d9a..07cf223 100644
--- a/hw/ip/prim/abstract/prim_clock_gating.sv
+++ b/hw/ip/prim/abstract/prim_clock_gating.sv
@@ -6,11 +6,11 @@
// "abstract module". This module is to be replaced by generated code.
`ifndef PRIM_DEFAULT_IMPL
- `define PRIM_DEFAULT_IMPL generic
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
`endif
module prim_clock_gating #(
- parameter Impl = "generic"
+ parameter integer Impl = `PRIM_DEFAULT_IMPL
) (
input clk_i,
input en_i,
@@ -18,14 +18,16 @@
output logic clk_o
);
- if (Impl == "generic") begin : gen_generic
+ import prim_pkg::*;
+
+ if (impl_e'(Impl) == ImplGeneric) begin : gen_generic
prim_generic_clock_gating u_impl_generic (
.clk_i,
.en_i,
.test_en_i,
.clk_o
);
- end else if (Impl == "xilinx") begin : gen_xilinx
+ end else if (impl_e'(Impl) == ImplXilinx) begin : gen_xilinx
prim_xilinx_clock_gating u_impl_xilinx (
.clk_i,
.en_i,
diff --git a/hw/ip/prim/abstract/prim_flash.sv b/hw/ip/prim/abstract/prim_flash.sv
index 6ecd88e..f09fdef 100644
--- a/hw/ip/prim/abstract/prim_flash.sv
+++ b/hw/ip/prim/abstract/prim_flash.sv
@@ -6,14 +6,15 @@
// "abstract module". This module is to be replaced by generated code.
`ifndef PRIM_DEFAULT_IMPL
- `define PRIM_DEFAULT_IMPL generic
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
`endif
module prim_flash #(
+ parameter integer Impl = `PRIM_DEFAULT_IMPL,
+
parameter int PagesPerBank = 256, // pages per bank
parameter int WordsPerPage = 256, // words per page
parameter int DataWidth = 32, // bits per word
- parameter Impl = "generic",
//Do not touch - Derived parameters
parameter int PageW = $clog2(PagesPerBank),
@@ -40,7 +41,9 @@
output logic init_busy_o
);
- if (Impl == "generic" || Impl == "xilinx") begin : gen_flash
+ import prim_pkg::*;
+
+ if (impl_e'(Impl) == ImplGeneric || impl_e'(Impl) == ImplXilinx) begin : gen_flash
prim_generic_flash #(
.PagesPerBank(PagesPerBank),
.WordsPerPage(WordsPerPage),
diff --git a/hw/ip/prim/abstract/prim_pad_wrapper.sv b/hw/ip/prim/abstract/prim_pad_wrapper.sv
index e18b7e3..2584cdb 100644
--- a/hw/ip/prim/abstract/prim_pad_wrapper.sv
+++ b/hw/ip/prim/abstract/prim_pad_wrapper.sv
@@ -5,8 +5,13 @@
// TODO: This module is a hard-coded stopgap to select an implementation of an
// "abstract module". This module is to be replaced by generated code.
+
+`ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
+`endif
+
module prim_pad_wrapper #(
- parameter Impl = "generic",
+ parameter int Impl = `PRIM_DEFAULT_IMPL,
parameter int unsigned AttrDw = 6
) (
inout wire inout_io, // bidirectional pad
@@ -17,8 +22,10 @@
input [AttrDw-1:0] attr_i
);
+ import prim_pkg::*;
+
// The generic implementation is NOT synthesizable
- if (Impl == "generic") begin : gen_pad_generic
+ if (impl_e'(Impl) == ImplGeneric) begin : gen_pad_generic
prim_generic_pad_wrapper #(
.AttrDw(AttrDw)
) i_pad_wrapper (
@@ -28,7 +35,7 @@
.oe_i,
.attr_i
);
- end else if (Impl == "xilinx") begin : gen_pad_xilinx
+ end else if (impl_e'(Impl) == ImplXilinx) begin : gen_pad_xilinx
prim_xilinx_pad_wrapper #(
.AttrDw(AttrDw)
) i_pad_wrapper (
diff --git a/hw/ip/prim/abstract/prim_ram_1p.sv b/hw/ip/prim/abstract/prim_ram_1p.sv
index 1d9dce6..9da25f0 100644
--- a/hw/ip/prim/abstract/prim_ram_1p.sv
+++ b/hw/ip/prim/abstract/prim_ram_1p.sv
@@ -5,11 +5,16 @@
// TODO: This module is a hard-coded stopgap to select an implementation of an
// "abstract module". This module is to be replaced by generated code.
+`ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
+`endif
+
module prim_ram_1p #(
+ parameter integer Impl = `PRIM_DEFAULT_IMPL,
+
parameter int Width = 32, // bit
parameter int Depth = 128,
parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask
- parameter Impl = "generic",
localparam int Aw = $clog2(Depth) // derived parameter
) (
input clk_i,
@@ -24,9 +29,11 @@
output logic [Width-1:0] rdata_o
);
+ import prim_pkg::*;
+
`ASSERT_INIT(paramCheckAw, Aw == $clog2(Depth))
- if (Impl == "generic" || Impl == "xilinx") begin : gen_mem_generic
+ if (impl_e'(Impl) == ImplGeneric || impl_e'(Impl) == ImplXilinx) begin : gen_mem_generic
prim_generic_ram_1p #(
.Width(Width),
.Depth(Depth),
diff --git a/hw/ip/prim/abstract/prim_ram_2p.sv b/hw/ip/prim/abstract/prim_ram_2p.sv
index 65d17d3..3f25fe7 100644
--- a/hw/ip/prim/abstract/prim_ram_2p.sv
+++ b/hw/ip/prim/abstract/prim_ram_2p.sv
@@ -5,14 +5,19 @@
// TODO: This module is a hard-coded stopgap to select an implementation of an
// "abstract module". This module is to be replaced by generated code.
+
+`ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
+`endif
+
module prim_ram_2p #(
- parameter int Width = 32, // bit
- parameter int Depth = 128,
+ parameter integer Impl = `PRIM_DEFAULT_IMPL,
+
+ parameter int Width = 32, // bit
+ parameter int Depth = 128,
// Do not touch
- parameter int Aw = $clog2(Depth), // derived parameter
-
- parameter Impl = "generic"
+ parameter int Aw = $clog2(Depth) // derived parameter
) (
input clk_a_i,
input clk_b_i,
@@ -30,9 +35,11 @@
output logic [Width-1:0] b_rdata_o
);
+ import prim_pkg::*;
+
`ASSERT_INIT(paramCheckAw, Aw == $clog2(Depth))
- if (Impl == "generic") begin : gen_mem_generic
+ if (impl_e'(Impl) == ImplGeneric) begin : gen_mem_generic
prim_generic_ram_2p #(
.Width(Width),
.Depth(Depth)
@@ -50,7 +57,7 @@
.b_wdata_i,
.b_rdata_o
);
- end else if (Impl == "xilinx") begin : gen_xilinx
+ end else if (impl_e'(Impl) == ImplXilinx) begin : gen_mem_xilinx
prim_xilinx_ram_2p #(
.Width(Width),
.Depth(Depth)
diff --git a/hw/ip/prim/abstract/prim_rom.sv b/hw/ip/prim/abstract/prim_rom.sv
index 8f73e19..51600b7 100644
--- a/hw/ip/prim/abstract/prim_rom.sv
+++ b/hw/ip/prim/abstract/prim_rom.sv
@@ -5,11 +5,14 @@
// TODO: This module is a hard-coded stopgap to select an implementation of an
// "abstract module". This module is to be replaced by generated code.
+`ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL integer'(prim_pkg::ImplGeneric)
+`endif
module prim_rom #(
- parameter int Width = 32,
- parameter int Depth = 2048, // 8kB default
- parameter Impl = "generic",
- parameter int Aw = $clog2(Depth)
+ parameter integer Impl = `PRIM_DEFAULT_IMPL,
+ parameter int Width = 32,
+ parameter int Depth = 2048, // 8kB default
+ parameter int Aw = $clog2(Depth)
) (
input clk_i,
input rst_ni,
@@ -19,7 +22,9 @@
output logic dvalid_o
);
- if (Impl == "generic") begin: gen_mem_generic
+ import prim_pkg::*;
+
+ if (impl_e'(Impl) == ImplGeneric) begin: gen_mem_generic
prim_generic_rom #(
.Width(Width),
.Depth(Depth)
@@ -31,7 +36,7 @@
.dout_o,
.dvalid_o
);
- end else if (Impl == "xilinx") begin: gen_rom_xilinx
+ end else if (impl_e'(Impl) == ImplXilinx) begin: gen_rom_xilinx
prim_xilinx_rom #(
.Width(Width),
.Depth(Depth)
diff --git a/hw/ip/prim/prim.core b/hw/ip/prim/prim.core
index 87620a3..47831bc 100644
--- a/hw/ip/prim/prim.core
+++ b/hw/ip/prim/prim.core
@@ -13,6 +13,7 @@
- lowrisc:prim:assert
- lowrisc:prim:diff_decode # for prim_alert_sender/receiver
- lowrisc:prim:pad_wrapper
+ - lowrisc:prim:prim_pkg
files:
- rtl/prim_clock_inverter.sv
- rtl/prim_alert_receiver.sv
diff --git a/hw/ip/prim/prim_clock_gating.core b/hw/ip/prim/prim_clock_gating.core
index 201e5bb..4b6d46c 100644
--- a/hw/ip/prim/prim_clock_gating.core
+++ b/hw/ip/prim/prim_clock_gating.core
@@ -10,6 +10,7 @@
depend:
- lowrisc:prim_generic:clock_gating
- lowrisc:prim_xilinx:clock_gating
+ - lowrisc:prim:prim_pkg
files:
- abstract/prim_clock_gating.sv
file_type: systemVerilogSource
diff --git a/hw/ip/prim/prim_flash.core b/hw/ip/prim/prim_flash.core
index 132ff25..aaf62c8 100644
--- a/hw/ip/prim/prim_flash.core
+++ b/hw/ip/prim/prim_flash.core
@@ -11,6 +11,7 @@
- lowrisc:prim_generic:flash
- lowrisc:prim:assert
- lowrisc:ip:flash_ctrl_pkg
+ - lowrisc:prim:prim_pkg
files:
- abstract/prim_flash.sv
file_type: systemVerilogSource
diff --git a/hw/ip/prim/prim_pad_wrapper.core b/hw/ip/prim/prim_pad_wrapper.core
index 32953dc..55017a1 100644
--- a/hw/ip/prim/prim_pad_wrapper.core
+++ b/hw/ip/prim/prim_pad_wrapper.core
@@ -11,6 +11,7 @@
- lowrisc:prim_generic:pad_wrapper
- lowrisc:prim_xilinx:pad_wrapper
- lowrisc:prim:assert
+ - lowrisc:prim:prim_pkg
files:
- abstract/prim_pad_wrapper.sv
file_type: systemVerilogSource
diff --git a/hw/ip/prim/prim_pkg.core b/hw/ip/prim/prim_pkg.core
new file mode 100644
index 0000000..e09d0fe
--- /dev/null
+++ b/hw/ip/prim/prim_pkg.core
@@ -0,0 +1,17 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:prim:prim_pkg:0.1"
+description: "Constants used by the primitives"
+
+filesets:
+ files_rtl:
+ files:
+ - rtl/prim_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/ip/prim/prim_ram_1p.core b/hw/ip/prim/prim_ram_1p.core
index 2789af8..0e873a5 100644
--- a/hw/ip/prim/prim_ram_1p.core
+++ b/hw/ip/prim/prim_ram_1p.core
@@ -10,6 +10,7 @@
depend:
- lowrisc:prim_generic:ram_1p
- lowrisc:prim:assert
+ - lowrisc:prim:prim_pkg
files:
- abstract/prim_ram_1p.sv
file_type: systemVerilogSource
diff --git a/hw/ip/prim/prim_ram_2p.core b/hw/ip/prim/prim_ram_2p.core
index dfb663a..e02ad97 100644
--- a/hw/ip/prim/prim_ram_2p.core
+++ b/hw/ip/prim/prim_ram_2p.core
@@ -11,6 +11,7 @@
- lowrisc:prim_generic:ram_2p
- lowrisc:prim_xilinx:ram_2p
- lowrisc:prim:assert
+ - lowrisc:prim:prim_pkg
files:
- abstract/prim_ram_2p.sv
file_type: systemVerilogSource
diff --git a/hw/ip/prim/prim_rom.core b/hw/ip/prim/prim_rom.core
index 31cdcb1..e8b15e0 100644
--- a/hw/ip/prim/prim_rom.core
+++ b/hw/ip/prim/prim_rom.core
@@ -10,6 +10,7 @@
depend:
- lowrisc:prim_generic:rom
- lowrisc:prim_xilinx:rom
+ - lowrisc:prim:prim_pkg
files:
- abstract/prim_rom.sv
file_type: systemVerilogSource
diff --git a/hw/ip/prim/rtl/prim_pkg.sv b/hw/ip/prim/rtl/prim_pkg.sv
new file mode 100644
index 0000000..e060144
--- /dev/null
+++ b/hw/ip/prim/rtl/prim_pkg.sv
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Constants for use in primitives
+
+package prim_pkg;
+
+ // Implementation target specialization
+ typedef enum integer {
+ ImplGeneric = 0,
+ ImplXilinx = 1
+ } impl_e;
+
+endpackage : prim_pkg
diff --git a/hw/ip/prim/rtl/prim_ram_2p_adv.sv b/hw/ip/prim/rtl/prim_ram_2p_adv.sv
index 7582051..196bd9c 100644
--- a/hw/ip/prim/rtl/prim_ram_2p_adv.sv
+++ b/hw/ip/prim/rtl/prim_ram_2p_adv.sv
@@ -85,7 +85,7 @@
prim_ram_2p #(
.Width (TotalWidth),
.Depth (Depth),
- .Impl ("generic")
+ .Impl (prim_pkg::ImplGeneric)
) u_mem (
.clk_a_i (clk_i),
.clk_b_i (clk_i),
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core
index 51ceb99..15128fd 100644
--- a/hw/top_earlgrey/top_earlgrey.core
+++ b/hw/top_earlgrey/top_earlgrey.core
@@ -38,14 +38,24 @@
ASIC_SYNTHESIS:
datatype: bool
paramtype: vlogdefine
+ # For value definition, please see ip/prim/rtl/prim_pkg.sv
+ PRIM_DEFAULT_IMPL:
+ datatype: int
+ paramtype: vlogdefine
+ description: Primitives implementation to use. 0=Generic, 1=Xilinx
+ default: 0 # generic
targets:
default: &default_target
filesets:
- files_rtl_generic
+ parameters:
+ - PRIM_DEFAULT_IMPL=0 # generic
toplevel: top_earlgrey
sim:
default_tool: icarus
filesets:
- files_rtl_generic
+ parameters:
+ - PRIM_DEFAULT_IMPL=0 # generic
toplevel: top_earlgrey
diff --git a/hw/top_earlgrey/top_earlgrey_artys7-50.core b/hw/top_earlgrey/top_earlgrey_artys7-50.core
index 852b565..ca784f8 100644
--- a/hw/top_earlgrey/top_earlgrey_artys7-50.core
+++ b/hw/top_earlgrey/top_earlgrey_artys7-50.core
@@ -30,10 +30,11 @@
description: SRAM initialization file in vmem hex format
default: "../../../../../sw/examples/hello_world/hello_world.vmem"
paramtype: vlogdefine
+ # For value definition, please see ip/prim/rtl/prim_pkg.sv
PRIM_DEFAULT_IMPL:
- datatype: str
+ datatype: int
paramtype: vlogdefine
- description: Primitives implementation to use
+ description: Primitives implementation to use. 0=Generic, 1=Xilinx
targets:
synth:
@@ -44,7 +45,7 @@
toplevel: top_earlgrey_artys7
parameters:
- SRAM_INIT_FILE
- - PRIM_DEFAULT_IMPL=xilinx
+ - PRIM_DEFAULT_IMPL=1 # xilinx
tools:
vivado:
part: "xc7s50csga324-1" # Arty S7-50
diff --git a/hw/top_earlgrey/top_earlgrey_nexysvideo.core b/hw/top_earlgrey/top_earlgrey_nexysvideo.core
index 1eaf472..d163e4a 100644
--- a/hw/top_earlgrey/top_earlgrey_nexysvideo.core
+++ b/hw/top_earlgrey/top_earlgrey_nexysvideo.core
@@ -31,10 +31,11 @@
description: SRAM initialization file in vmem hex format
default: "../../../../../sw/boot_rom/rom.vmem"
paramtype: vlogdefine
+ # For value definition, please see ip/prim/rtl/prim_pkg.sv
PRIM_DEFAULT_IMPL:
- datatype: str
+ datatype: int
paramtype: vlogdefine
- description: Primitives implementation to use
+ description: Primitives implementation to use. 0=Generic, 1=Xilinx
targets:
synth:
@@ -45,7 +46,7 @@
toplevel: top_earlgrey_nexysvideo
parameters:
- ROM_INIT_FILE
- - PRIM_DEFAULT_IMPL=xilinx
+ - PRIM_DEFAULT_IMPL=1 # xilinx
tools:
vivado:
part: "xc7a200tsbg484-1" # Nexys Video
diff --git a/hw/top_earlgrey/top_earlgrey_usb_nexysvideo.core b/hw/top_earlgrey/top_earlgrey_usb_nexysvideo.core
index 798108f..79a6f2e 100644
--- a/hw/top_earlgrey/top_earlgrey_usb_nexysvideo.core
+++ b/hw/top_earlgrey/top_earlgrey_usb_nexysvideo.core
@@ -31,9 +31,9 @@
default: "../../../../../sw/examples/hello_usbdev/hello_usbdev.vmem"
paramtype: vlogdefine
PRIM_DEFAULT_IMPL:
- datatype: str
+ datatype: int
paramtype: vlogdefine
- description: Primitives implementation to use
+ description: Primitives implementation to use. 0=Generic, 1=Xilinx
targets:
synth:
@@ -44,7 +44,7 @@
toplevel: top_earlgrey_usb_nexysvideo
parameters:
- SRAM_INIT_FILE
- - PRIM_DEFAULT_IMPL=xilinx
+ - PRIM_DEFAULT_IMPL=1 # xilinx
tools:
vivado:
part: "xc7a200tsbg484-1" # Nexys Video
diff --git a/hw/top_earlgrey/top_earlgrey_usb_verilator.core b/hw/top_earlgrey/top_earlgrey_usb_verilator.core
index a01c7bd..b2aa8c4 100644
--- a/hw/top_earlgrey/top_earlgrey_usb_verilator.core
+++ b/hw/top_earlgrey/top_earlgrey_usb_verilator.core
@@ -19,15 +19,16 @@
- rtl/top_earlgrey_usb_verilator.sv: { file_type: systemVerilogSource }
- top_earlgrey_usb_verilator.cc: { file_type: cppSource }
parameters:
+ # For value definition, please see ip/prim/rtl/prim_pkg.sv
PRIM_DEFAULT_IMPL:
- datatype: str
+ datatype: int
paramtype: vlogdefine
- description: Primitives implementation to use
+ description: Primitives implementation to use. 0=Generic, 1=Xilinx
targets:
sim:
parameters:
- - PRIM_DEFAULT_IMPL=generic
+ - PRIM_DEFAULT_IMPL=0 # generic
default_tool: verilator
filesets:
- files_sim_verilator
diff --git a/hw/top_earlgrey/top_earlgrey_verilator.core b/hw/top_earlgrey/top_earlgrey_verilator.core
index dfebbbc..d1cd469 100644
--- a/hw/top_earlgrey/top_earlgrey_verilator.core
+++ b/hw/top_earlgrey/top_earlgrey_verilator.core
@@ -20,10 +20,11 @@
- top_earlgrey_verilator.cc: { file_type: cppSource }
parameters:
+ # For value definition, please see ip/prim/rtl/prim_pkg.sv
PRIM_DEFAULT_IMPL:
- datatype: str
+ datatype: int
paramtype: vlogdefine
- description: Primitives implementation to use
+ description: Primitives implementation to use. 0=Generic, 1=Xilinx
RVFI:
datatype: bool
paramtype: vlogdefine
@@ -32,7 +33,7 @@
targets:
sim:
parameters:
- - PRIM_DEFAULT_IMPL=generic
+ - PRIM_DEFAULT_IMPL=0 # generic
- RVFI=true
default_tool: verilator
filesets:
