| commit | 0526196043521f6610e36d9d0e98c1326230639a | [log] [tgz] |
|---|---|---|
| author | Abdullah Varici <abdullah.varici@lowrisc.org> | Wed Oct 26 20:06:53 2022 +0100 |
| committer | Drew Macrae <drewmacrae@gmail.com> | Wed Nov 02 13:34:59 2022 -0400 |
| tree | c6076c31fcbd76adb434354ca610fe7a65b8cd00 | |
| parent | 3a7c11f8b3fbabd45ce31e9fd4ed1a2fb0b6eb86 [diff] |
[top-level/pwrmgr] Extend chip_sw_pwrmgr_main_power_glitch_reset Add three groups of assertions to check that: - the clock valids are deasserted if a power glitch is detected. - clocks are stopped if their valid is deasserted. - clocks are running if their valid is asserted. Enable pwrmgr_ast_sva_if.sv assertions in _vseq file. Add main_, io_, usb_ clock inputs to pwrmgr_ast_sva_if and create a binding in tb.sv for that. Signed-off-by: Abdullah Varici <abdullah.varici@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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