commit c909eb30d2be0479d5b013352eab832b46fb41a2
author Eunchan Kim <eunchan@google.com> Wed Oct 30 19:45:22 2019 -0700
committer Eunchan Kim <eunchan@google.com> Thu Oct 31 14:10:14 2019 -0700
tree fa54962bd0b2e3cee35e7c6ecf05bfcbbc5b6458
parent e86f54f596f93f0a279471e5d172e77e538b9daf

[prim/packer] Revert the design prior to #634

Problem:

    `prim_packer` sent out partial data (mask_o != '1) in some case
    without `flush_i`.

While testing the `hmac_back_pressure`, the test failed at the assertion
below in `sha2_pad.sv`.

```systemverilog
  // When fifo_partial, fifo shouldn't be empty and hash_process was set
  `ASSERT(ValidPartialConditionAssert,
          fifo_partial && fifo_rvalid |-> hash_process_flag,
          clk_i, !rst_ni)
```

It complains when it receives not full word data from MSG_FIFO wihout
`hash_process` indication from the software. It means, something wrong
happens along the data path from TL-UL interface to sha2_pad logic.

The mask (which creates `fifo_partial`) is generated in `prim_packer`.
While reviewing the logic again, I found that the PR #634 I assumed
`prim_packer` has 64 bit internal registers (InW := 32 and OutW := 32).

But, when I designed it, I made it to have `max(InW, OutW)`, so if the
stored data + incoming data size exceeds `MaxW`, the logic should lower
`ready_o`. It worked well before changing the design.

While adding FPV assertions internally, I've assumed it wrong and
changed the design to store the incoming data if current stored data
size is less than or equal to `OutW`.

Resolution:

    Rolled-back the `prim_packer` to original and increased `pos_next`
    size to accomodate `InW + OutW` value, which is `Width + 1`.

This is related to #19

[prim/packer] Add more assertions for solid FPV