[tlgen] Add crossbar assertions bind module
- Added bind and removed dv from the tlgen (incl. topgen) as dv template
isn't used anymore
diff --git a/hw/ip/tlul/xbar_dv.core b/hw/ip/tlul/xbar_dv.core
index e0b9ba2..4b6d3c0 100644
--- a/hw/ip/tlul/xbar_dv.core
+++ b/hw/ip/tlul/xbar_dv.core
@@ -5,15 +5,9 @@
name: "lowrisc:ip:xbar_dv:0.1"
description: "xbar_dv"
filesets:
- files_rtl:
- depend:
- - lowrisc:ip:tlul:0.1
- files:
- - dv/tb/xbar_main_bind.sv
- file_type: systemVerilogSource
-
files_dv:
depend:
+ - lowrisc:ip:tlul:0.1
- lowrisc:dv:dv_utils
- lowrisc:dv:tl_agent
- lowrisc:dv:scoreboard
@@ -28,12 +22,8 @@
file_type: systemVerilogSource
targets:
- default:
- filesets:
- - files_rtl
sim:
toplevel: xbar_tb_top
filesets:
- - files_rtl
- files_dv
default_tool: vcs
diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core
index 658fee9..70c6e59 100644
--- a/hw/top_earlgrey/dv/chip_sim.core
+++ b/hw/top_earlgrey/dv/chip_sim.core
@@ -11,7 +11,7 @@
- lowrisc:ibex:ibex_tracer:0.1
files:
- ../rtl/top_earlgrey_asic.sv
- - ../../ip/tlul/dv/tb/xbar_main_bind.sv
+ - xbar_main_bind.sv
file_type: systemVerilogSource
files_dv:
diff --git a/hw/ip/tlul/dv/tb/xbar_main_bind.sv b/hw/top_earlgrey/dv/xbar_main_bind.sv
similarity index 84%
rename from hw/ip/tlul/dv/tb/xbar_main_bind.sv
rename to hw/top_earlgrey/dv/xbar_main_bind.sv
index 538b9fc..e3dc26b 100644
--- a/hw/ip/tlul/dv/tb/xbar_main_bind.sv
+++ b/hw/top_earlgrey/dv/xbar_main_bind.sv
@@ -1,12 +1,11 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-
+//
+// xbar_main_bind module generated by `tlgen.py` tool for assertions
module xbar_main_bind;
- // TODO: this file should be generated like xbar_main
-
- // host interfaces
+ // Host interfaces
bind xbar_main tlul_assert tlul_assert_host_corei (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -19,27 +18,27 @@
.h2d (tl_cored_i),
.d2h (tl_cored_o)
);
- bind xbar_main tlul_assert tlul_assert_host_sba (
+ bind xbar_main tlul_assert tlul_assert_host_dm_sba (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
.h2d (tl_dm_sba_i),
.d2h (tl_dm_sba_o)
);
- // device interfaces
+ // Device interfaces
bind xbar_main tlul_assert tlul_assert_device_rom (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
.h2d (tl_rom_o),
.d2h (tl_rom_i)
);
- bind xbar_main tlul_assert tlul_assert_device_debug (
+ bind xbar_main tlul_assert tlul_assert_device_debug_mem (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
.h2d (tl_debug_mem_o),
.d2h (tl_debug_mem_i)
);
- bind xbar_main tlul_assert tlul_assert_device_ram (
+ bind xbar_main tlul_assert tlul_assert_device_ram_main (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
.h2d (tl_ram_main_o),
@@ -69,7 +68,7 @@
.h2d (tl_spi_device_o),
.d2h (tl_spi_device_i)
);
- bind xbar_main tlul_assert tlul_assert_device_flash (
+ bind xbar_main tlul_assert tlul_assert_device_flash_ctrl (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
.h2d (tl_flash_ctrl_o),
@@ -87,7 +86,7 @@
.h2d (tl_hmac_o),
.d2h (tl_hmac_i)
);
- bind xbar_main tlul_assert tlul_assert_device_plic (
+ bind xbar_main tlul_assert tlul_assert_device_rv_plic (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
.h2d (tl_rv_plic_o),
@@ -95,3 +94,5 @@
);
endmodule
+
+
diff --git a/util/tlgen/generate.py b/util/tlgen/generate.py
index 80f7e91..7a9ba25 100644
--- a/util/tlgen/generate.py
+++ b/util/tlgen/generate.py
@@ -18,10 +18,12 @@
filename=resource_filename('tlgen', 'xbar.rtl.tpl.sv'))
xbar_pkg_tpl = Template(
filename=resource_filename('tlgen', 'xbar.pkg.tpl.sv'))
- xbar_dv_tpl = Template(
- filename=resource_filename('tlgen', 'xbar.dv.tpl.sv'))
+ #xbar_dv_tpl = Template(
+ # filename=resource_filename('tlgen', 'xbar.dv.tpl.sv'))
+ xbar_bind_tpl = Template(
+ filename=resource_filename('tlgen', 'xbar.bind.tpl.sv'))
out_rtl = xbar_rtl_tpl.render(xbar=xbar, ntype=NodeType)
out_pkg = xbar_pkg_tpl.render(xbar=xbar)
- out_dv = xbar_dv_tpl.render(xbar=xbar, ntype=NodeType)
- return (out_rtl, out_pkg, out_dv)
+ out_bind = xbar_bind_tpl.render(xbar=xbar, ntype=NodeType)
+ return (out_rtl, out_pkg, out_bind)
diff --git a/util/tlgen/xbar.bind.tpl.sv b/util/tlgen/xbar.bind.tpl.sv
new file mode 100644
index 0000000..dab0b79
--- /dev/null
+++ b/util/tlgen/xbar.bind.tpl.sv
@@ -0,0 +1,30 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_${xbar.name}_bind module generated by `tlgen.py` tool for assertions
+module xbar_${xbar.name}_bind;
+
+ // Host interfaces
+% for node in xbar.hosts:
+ bind xbar_${xbar.name} tlul_assert tlul_assert_host_${node.name} (
+ .clk_i (clk_${node.clocks[0]}_i),
+ .rst_ni (rst_${node.clocks[0]}_ni),
+ .h2d (tl_${node.name}_i),
+ .d2h (tl_${node.name}_o)
+ );
+% endfor
+
+ // Device interfaces
+% for node in xbar.devices:
+ bind xbar_${xbar.name} tlul_assert tlul_assert_device_${node.name} (
+ .clk_i (clk_${node.clocks[0]}_i),
+ .rst_ni (rst_${node.clocks[0]}_ni),
+ .h2d (tl_${node.name}_o),
+ .d2h (tl_${node.name}_i)
+ );
+% endfor
+
+endmodule
+
+
diff --git a/util/topgen.py b/util/topgen.py
index 434fc0c..c421e3c 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -29,6 +29,7 @@
// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
'''
+
def generate_rtl(top, tpl_filename):
top_rtl_tpl = Template(filename=tpl_filename)
@@ -45,7 +46,7 @@
# Add clocks to the top configuration
obj["clocks"] = xbar.clocks
- out_rtl, out_pkg, out_dv = tlgen.generate(xbar)
+ out_rtl, out_pkg, out_bind = tlgen.generate(xbar)
rtl_path = out_path / 'rtl'
rtl_path.mkdir(parents=True, exist_ok=True)
@@ -62,10 +63,10 @@
with pkg_filepath.open(mode='w', encoding='UTF-8') as fout:
fout.write(out_pkg)
- dv_filename = "xbar_%s_tb.sv" % (xbar.name)
- dv_filepath = dv_path / dv_filename
- with dv_filepath.open(mode='w', encoding='UTF-8') as fout:
- fout.write(out_dv)
+ bind_filename = "xbar_%s_bind.sv" % (xbar.name)
+ bind_filepath = dv_path / bind_filename
+ with bind_filepath.open(mode='w', encoding='UTF-8') as fout:
+ fout.write(out_bind)
def generate_plic(top, out_path):
@@ -103,8 +104,9 @@
return
hjson_gen_path = doc_path / "rv_plic.hjson"
- gencmd = ("// util/topgen.py -t hw/top_earlgrey/doc/top_earlgrey.hjson --plic-only "
- "-o hw/top_earlgrey/\n\n")
+ gencmd = (
+ "// util/topgen.py -t hw/top_earlgrey/doc/top_earlgrey.hjson --plic-only "
+ "-o hw/top_earlgrey/\n\n")
with hjson_gen_path.open(mode='w', encoding='UTF-8') as fout:
fout.write(genhdr + gencmd + out)
@@ -166,11 +168,10 @@
def main():
parser = argparse.ArgumentParser(prog="topgen")
- parser.add_argument(
- '--topcfg',
- '-t',
- required=True,
- help="`top_{name}.hjson` file.")
+ parser.add_argument('--topcfg',
+ '-t',
+ required=True,
+ help="`top_{name}.hjson` file.")
parser.add_argument('--tpl', '-c', help="`top_{name}.tpl.sv` file.")
parser.add_argument(
'--outdir',
@@ -298,10 +299,9 @@
x.stem)
continue
- obj = hjson.load(
- x.open('r'),
- use_decimal=True,
- object_pairs_hook=validate.checking_dict)
+ obj = hjson.load(x.open('r'),
+ use_decimal=True,
+ object_pairs_hook=validate.checking_dict)
if validate.validate(obj) != 0:
log.info("Parsing IP %s configuration failed. Skip" % x)
continue
@@ -323,8 +323,9 @@
completecfg = merge_top(topcfg, ip_objs, xbar_objs)
genhjson_path = hjson_dir / ("top_%s.gen.hjson" % completecfg["name"])
- gencmd = ("// util/topgen.py -t hw/top_earlgrey/doc/top_earlgrey.hjson --hjson-only "
- "-o hw/top_earlgrey/\n")
+ gencmd = (
+ "// util/topgen.py -t hw/top_earlgrey/doc/top_earlgrey.hjson --hjson-only "
+ "-o hw/top_earlgrey/\n")
if args.top_ral:
generate_top_ral(completecfg, ip_objs, out_path)
