commit c66d8c9b7aced9c489551054cd7ff153990564cc
author Rupert Swarbrick <rswarbrick@lowrisc.org> Thu Mar 18 09:14:58 2021 +0000
committer Rupert Swarbrick <rswarbrick@gmail.com> Thu Mar 18 16:31:33 2021 +0000
tree 3cf440a2b7f3305a9e0f0bf8d052a8afab0eec2b
parent d0ca7e97ffd988d9d9ec27a73d876ff009b29b79

[keymgr] Fix AlertAsyncOn parameter

This needs a bit per alert, but the existing code just had a single
bit, causing a Verilator lint warning when wiring up the top-level.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

hw/ip/keymgr/rtl/keymgr.sv

diff --git a/hw/ip/keymgr/rtl/keymgr.sv b/hw/ip/keymgr/rtl/keymgr.sv
index d795006..47fde28 100644
--- a/hw/ip/keymgr/rtl/keymgr.sv
+++ b/hw/ip/keymgr/rtl/keymgr.sv
@@ -7,8 +7,11 @@
 
 `include "prim_assert.sv"
 
-module keymgr import keymgr_pkg::*; #(
-  parameter logic AlertAsyncOn                 = 1'b1,
+module keymgr
+  import keymgr_pkg::*;
+  import keymgr_reg_pkg::*;
+#(
+  parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
   parameter lfsr_seed_t RndCnstLfsrSeed        = RndCnstLfsrSeedDefault,
   parameter lfsr_perm_t RndCnstLfsrPerm        = RndCnstLfsrPermDefault,
   parameter rand_perm_t RndCnstRandPerm        = RndCnstRandPermDefault,
@@ -509,7 +512,7 @@
   assign fault_alert_test = reg2hw.alert_test.fatal_fault_err.q &
                             reg2hw.alert_test.fatal_fault_err.qe;
   prim_alert_sender #(
-    .AsyncOn(AlertAsyncOn),
+    .AsyncOn(AlertAsyncOn[0]),
     .IsFatal(1)
   ) u_fault_alert (
     .clk_i,
@@ -526,8 +529,8 @@
   assign op_err_alert_test = reg2hw.alert_test.recov_operation_err.q &
                              reg2hw.alert_test.recov_operation_err.qe;
   prim_alert_sender #(
-    .AsyncOn(AlertAsyncOn),
-      .IsFatal(0)
+    .AsyncOn(AlertAsyncOn[1]),
+    .IsFatal(0)
   ) u_op_err_alert (
     .clk_i,
     .rst_ni,