[dv/pwrmgr] Declare V1
Add stress as a testpoint for V3.
Signed-off-by: Guillermo Maturana <maturana@google.com>
diff --git a/hw/ip/pwrmgr/data/pwrmgr.prj.hjson b/hw/ip/pwrmgr/data/pwrmgr.prj.hjson
index 31bd4f4..2794767 100644
--- a/hw/ip/pwrmgr/data/pwrmgr.prj.hjson
+++ b/hw/ip/pwrmgr/data/pwrmgr.prj.hjson
@@ -21,7 +21,7 @@
version: "0.5",
life_stage: "L1",
design_stage: "D2",
- verification_stage: "V0", // this module is not verified at the block level
+ verification_stage: "V1",
dif_stage: "S0",
}
]
diff --git a/hw/ip/pwrmgr/data/pwrmgr_testplan.hjson b/hw/ip/pwrmgr/data/pwrmgr_testplan.hjson
index b80af9f..871369b 100644
--- a/hw/ip/pwrmgr/data/pwrmgr_testplan.hjson
+++ b/hw/ip/pwrmgr/data/pwrmgr_testplan.hjson
@@ -5,8 +5,9 @@
name: "pwrmgr"
// TODO: remove the common testplans if not applicable
import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
- // "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
- "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"]
+ "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson"]
testpoints: [
{
name: smoke
@@ -216,7 +217,14 @@
milestone: V2
tests: []
}
+ {
+ name: stress
+ desc: '''The standard stress test.'''
+ milestone: V3
+ tests: []
+ }
]
+
covergroups: [
{
name: wakeup_cg
diff --git a/hw/ip/pwrmgr/doc/checklist.md b/hw/ip/pwrmgr/doc/checklist.md
index 2136293..2619a45 100644
--- a/hw/ip/pwrmgr/doc/checklist.md
+++ b/hw/ip/pwrmgr/doc/checklist.md
@@ -110,28 +110,28 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [PWRMGR DV document]({{<relref "hw/top_earlgrey/doc/dv/index.md" >}})
-Documentation | [TESTPLAN_COMPLETED][] | Not Started | [PWRMGR testplan]()
-Testbench | [TB_TOP_CREATED][] | Not Started |
-Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
-Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
-Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started |
-Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started |
-Testbench | [TB_GEN_AUTOMATED][] | Not Started |
-Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started |
-Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started |
-Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started |
-Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started |
-Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started |
-Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started |
-Regression | [FPV_REGRESSION_SETUP][] | Not Started |
-Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started |
-Code Quality | [TB_LINT_SETUP][] | Not Started |
-Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started |
-Review | [DESIGN_SPEC_REVIEWED][] | Not Started |
-Review | [TESTPLAN_REVIEWED][] | Not Started |
-Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?)
-Review | [V2_CHECKLIST_SCOPED][] | Not Started |
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [PWRMGR DV document]({{<relref "dv/index.md" >}})
+Documentation | [TESTPLAN_COMPLETED][] | Done | [PWRMGR testplan]({{< relref "dv/index.md#testplan" >}})
+Testbench | [TB_TOP_CREATED][] | Done |
+Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
+Testbench | [SIM_TB_ENV_CREATED][] | Done |
+Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done |
+Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done |
+Testbench | [TB_GEN_AUTOMATED][] | Done |
+Tests | [SIM_SMOKE_TEST_PASSING][] | Done |
+Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | Block has no mem
+Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A |
+Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium
+Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done |
+Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done |
+Regression | [FPV_REGRESSION_SETUP][] | N/A |
+Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done |
+Code Quality | [TB_LINT_SETUP][] | Done |
+Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done |
+Review | [DESIGN_SPEC_REVIEWED][] | Done |
+Review | [TESTPLAN_REVIEWED][] | Done |
+Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exceptions: debug, power, performance
+Review | [V2_CHECKLIST_SCOPED][] | Done |
[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
[TESTPLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#testplan_completed" >}}
