commit c62e71d1cb8b09d9fe96f54ecea38dc08bfc70a9
author Timothy Chen <timothytim@google.com> Thu Apr 14 14:35:33 2022 -0700
committer tjaychen <timothytim@google.com> Fri Apr 15 09:11:05 2022 -0700
tree 7cae12c21b4feb30f832a3956185167e299fdfed
parent 74b0740cec8836b11b71d9ce97bb244f77c75bb1

[clkmgr] Connect prim count failure to right alert

- fixes #11448

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/ip/clkmgr/data/clkmgr.sv.tpl

diff --git a/hw/ip/clkmgr/data/clkmgr.sv.tpl b/hw/ip/clkmgr/data/clkmgr.sv.tpl
index 38df40e..f19e4db 100644
--- a/hw/ip/clkmgr/data/clkmgr.sv.tpl
+++ b/hw/ip/clkmgr/data/clkmgr.sv.tpl
@@ -484,7 +484,7 @@
   `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
     ${assert_name.as_camel_case()}CountCheck_A,
     u_${clk}_trans.u_idle_cnt,
-    alert_tx_o[0])
+    alert_tx_o[1])
 % endfor
   assign hw2reg.fatal_err_code.idle_cnt.d = 1'b1;
   assign hw2reg.fatal_err_code.idle_cnt.de = |idle_cnt_err;

hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv

diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index c9a0e9e..716a9a0 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -1049,7 +1049,7 @@
   `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
     ClkMainAesCountCheck_A,
     u_clk_main_aes_trans.u_idle_cnt,
-    alert_tx_o[0])
+    alert_tx_o[1])
 
   clkmgr_trans #(
     .FpgaBufGlobal(1'b0) // This clock is used primarily locally.
@@ -1069,7 +1069,7 @@
   `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
     ClkMainHmacCountCheck_A,
     u_clk_main_hmac_trans.u_idle_cnt,
-    alert_tx_o[0])
+    alert_tx_o[1])
 
   clkmgr_trans #(
     .FpgaBufGlobal(1'b1) // KMAC is getting too big for a single clock region.
@@ -1089,7 +1089,7 @@
   `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
     ClkMainKmacCountCheck_A,
     u_clk_main_kmac_trans.u_idle_cnt,
-    alert_tx_o[0])
+    alert_tx_o[1])
 
   clkmgr_trans #(
     .FpgaBufGlobal(1'b0) // This clock is used primarily locally.
@@ -1109,7 +1109,7 @@
   `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
     ClkMainOtbnCountCheck_A,
     u_clk_main_otbn_trans.u_idle_cnt,
-    alert_tx_o[0])
+    alert_tx_o[1])
   assign hw2reg.fatal_err_code.idle_cnt.d = 1'b1;
   assign hw2reg.fatal_err_code.idle_cnt.de = |idle_cnt_err;