[dvsim] Support for running pre-built SW tests
This PR adds support for running pre-built SW tests, with a few
optimizations:
- Removed `sw_dir` var from hjson - paths to SW tests relative to
`REPO_TOP` are to be indicated now with `sw_test` instead
- Renamed `sw_name` with `sw_test` instead
- Added `sw_test_is_prebuilt` flag to indicate that it is prebuilt
- Supporting updates in `sim.mk` to decide what to do based on the
above flag
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/dv/data/sim.mk b/hw/dv/data/sim.mk
index f212362..0d69912 100644
--- a/hw/dv/data/sim.mk
+++ b/hw/dv/data/sim.mk
@@ -41,37 +41,48 @@
pre_run:
@echo "[make]: pre_run"
mkdir -p ${run_dir}
-ifneq (${sw_name},)
+ifneq (${sw_test},)
mkdir -p ${sw_build_dir}
endif
sw_build: pre_run
@echo "[make]: sw_build"
-ifneq (${sw_name},)
+ifneq (${sw_test},)
# Initialize meson build system.
${LOCK_SW_BUILD} "cd ${proj_root} && \
BUILD_ROOT=${sw_build_dir} ${proj_root}/meson_init.sh"
# Compile boot rom code and generate the image.
${LOCK_SW_BUILD} "ninja -C ${sw_build_dir}/build-out \
sw/device/boot_rom/boot_rom_export_${sw_build_device}"
- # Extract the rom logs.
+ # Extract the boot rom logs.
${proj_root}/util/device_sw_utils/extract_sw_logs.py \
-e "${sw_build_dir}/build-out/sw/device/boot_rom/boot_rom_${sw_build_device}.elf" \
-f .logs.fields -r .rodata .chip_info \
-n "rom" -o "${run_dir}"
- # Compile the test sw code and generate the image.
- ${LOCK_SW_BUILD} "ninja -C ${sw_build_dir}/build-out \
- sw/device/${sw_dir}/${sw_name}_export_${sw_build_device}"
- # Extract the sw logs.
- ${proj_root}/util/device_sw_utils/extract_sw_logs.py \
- -e "${sw_build_dir}/build-out/sw/device/${sw_dir}/${sw_name}_${sw_build_device}.elf" \
- -f .logs.fields -r .rodata \
- -n "sw" -o "${run_dir}"
- # Copy over the images to the run_dir.
+ # Copy over the boot rom image to the run_dir.
cp ${sw_build_dir}/build-out/sw/device/boot_rom/boot_rom_${sw_build_device}.32.vmem \
${run_dir}/rom.32.vmem
- cp ${sw_build_dir}/build-out/sw/device/${sw_dir}/${sw_name}_${sw_build_device}.32.vmem \
+
+ifeq (${sw_test_is_prebuilt},)
+ # Compile the sw test code and generate the image.
+ ${LOCK_SW_BUILD} "ninja -C ${sw_build_dir}/build-out \
+ ${sw_test}_export_${sw_build_device}"
+ # Extract the sw test logs.
+ ${proj_root}/util/device_sw_utils/extract_sw_logs.py \
+ -e "${sw_build_dir}/build-out/${sw_test}_${sw_build_device}.elf" \
+ -f .logs.fields -r .rodata \
+ -n "sw" -o "${run_dir}"
+ # Copy over the sw test image to the run_dir.
+ cp ${sw_build_dir}/build-out/${sw_test}_${sw_build_device}.32.vmem \
${run_dir}/sw.32.vmem
+else
+ # Copy over the sw test image and related sources to the run_dir.
+ cp ${proj_root}/${sw_test}.32.vmem ${run_dir}/sw.32.vmem
+ # Optionally, copy ${sw_test}_logs.txt over to the run_dir if it exists.
+ -cp ${proj_root}/${sw_test}_logs.txt ${run_dir}/sw_logs.txt
+ -cp ${proj_root}/${sw_test}_rodata.txt ${run_dir}/sw_rodata.txt
+endif
+
endif
simulate: sw_build
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 47b564e..a6b6797 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -95,44 +95,37 @@
{
name: chip_sanity
uvm_test_seq: chip_sw_test_base_vseq
- sw_name: hello_world
- sw_dir: examples/hello_world
+ sw_test: sw/device/examples/hello_world/hello_world
}
{
name: chip_aes_test
uvm_test_seq: chip_sw_test_base_vseq
- sw_name: aes_test
- sw_dir: tests
+ sw_test: sw/device/tests/aes_test
}
{
name: chip_consecutive_irqs_test
uvm_test_seq: chip_sw_test_base_vseq
- sw_name: consecutive_irqs_test
- sw_dir: tests
+ sw_test: sw/device/tests/consecutive_irqs_test
}
{
name: chip_flash_ctrl_test
uvm_test_seq: chip_sw_test_base_vseq
- sw_name: flash_ctrl_test
- sw_dir: tests
+ sw_test: sw/device/tests/flash_ctrl_test
}
{
name: chip_sha256_test
uvm_test_seq: chip_sw_test_base_vseq
- sw_name: sha256_test
- sw_dir: tests
+ sw_test: sw/device/tests/sha256_test
}
{
name: chip_rv_timer_test
uvm_test_seq: chip_sw_test_base_vseq
- sw_name: rv_timer_test
- sw_dir: tests
+ sw_test: sw/device/tests/rv_timer_test
}
{
name: chip_coremark
uvm_test_seq: chip_sw_test_base_vseq
- sw_name: coremark_top_earlgrey
- sw_dir: benchmarks/coremark
+ sw_test: sw/device/benchmarks/coremark/coremark_top_earlgrey
run_opts: ["+en_uart_logger=1",
"+sw_test_timeout_ns=20000000"]
}
diff --git a/util/dvsim/Deploy.py b/util/dvsim/Deploy.py
index 0b1b2d6..0a53397 100644
--- a/util/dvsim/Deploy.py
+++ b/util/dvsim/Deploy.py
@@ -659,8 +659,8 @@
"uvm_test": False,
"uvm_test_seq": False,
"run_opts": False,
- "sw_dir": False,
- "sw_name": False,
+ "sw_test": False,
+ "sw_test_is_prebuilt": False,
"sw_build_device": False,
"sw_build_dir": False,
"run_dir": False,
diff --git a/util/dvsim/Modes.py b/util/dvsim/Modes.py
index 0432702..2d3a60e 100644
--- a/util/dvsim/Modes.py
+++ b/util/dvsim/Modes.py
@@ -271,8 +271,8 @@
self.uvm_test_seq = ""
self.build_mode = ""
self.en_run_modes = []
- self.sw_dir = ""
- self.sw_name = ""
+ self.sw_test = ""
+ self.sw_test_is_prebuilt = ""
self.sw_build_device = ""
super().__init__(rdict)
@@ -298,8 +298,8 @@
"uvm_test": "",
"uvm_test_seq": "",
"build_mode": "",
- "sw_dir": "",
- "sw_name": "",
+ "sw_test": "",
+ "sw_test_is_prebuilt": "",
"sw_build_device": "",
}
diff --git a/util/dvsim/SimCfg.py b/util/dvsim/SimCfg.py
index 1afa573..fe94210 100644
--- a/util/dvsim/SimCfg.py
+++ b/util/dvsim/SimCfg.py
@@ -124,7 +124,7 @@
# TODO: Find a way to set these in sim cfg instead
ignored_wildcards = [
"build_mode", "index", "test", "seed", "uvm_test", "uvm_test_seq",
- "cov_db_dirs", "sw_dir", "sw_name", "sw_build_device"
+ "cov_db_dirs", "sw_test", "sw_test_is_prebuilt", "sw_build_device"
]
self.__dict__ = find_and_substitute_wildcards(self.__dict__,
self.__dict__,
