[top_earlgrey] - Top level changes to integrate rstmgr / pwrmgr

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 9ec7cef..5a794d2 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -125,11 +125,6 @@
   % endfor
 % endfor
 
-  //reset wires declaration
-% for reset in top['resets']:
-  logic ${reset['name']}_rst_n;
-% endfor
-
   //clock wires declaration
 % for clock_group in clks_attr['groups']:
   % for k in clock_group['clocks']:
@@ -222,30 +217,9 @@
   % endfor
 % endfor
 
-
   // Non-debug module reset == reset for everything except for the debug module
   logic ndmreset_req;
 
-  // root resets
-  // TODO: lc_rst_n is not the true root reset.  It will be differentiated once the
-  //       the reset controller logic is present
-  assign lc_rst_n = rst_ni;
-  assign sys_rst_n = (scanmode_i) ? lc_rst_n : ~ndmreset_req & lc_rst_n;
-
-  // Non-root reset assignments
-% for reset in top['resets']:
-  % if reset['type'] in ['gen'] and reset['name'] != "usb" :
-  assign ${reset['name']}_rst_n = ${reset['root']}_rst_n;
-  % endif
-% endfor
-
-  // Reset synchronizer for USB
-  logic [1:0] usb_rst_q;
-  always_ff @(posedge clk_usb_48mhz_peri) begin
-    usb_rst_q <= {usb_rst_q[0], sys_rst_n};
-  end
-  assign usb_rst_n = sys_rst_n & usb_rst_q[1];
-
   // debug request from rv_dm to core
   logic debug_req;
 
@@ -288,7 +262,7 @@
     .debug_req_i          (debug_req),
     // CPU control signals
     .fetch_enable_i       (1'b1),
-    .core_sleep_o         ()
+    .core_sleep_o         (pwrmgr_pwr_cpu.core_sleeping)
   );
 
   // Debug Module (RISC-V Debug Spec 0.13)
@@ -323,6 +297,9 @@
     .tdo_oe_o         (       )
   );
 
+  assign rstmgr_cpu.ndmreset_req = ndmreset_req;
+  assign rstmgr_cpu.rst_cpu_n = ${top["reset_paths"]["sys"]};
+
 ## Memory Instantiation
 % for m in top["memory"]:
 <%