[top] Move spi_host* in memory map
- Fixes #8748
- This reduces the amount of asynchronous latency when accessing
the spi_host modules.
- Note, ideally there should be another xbar that is "hi_speed" xbar,
but that is overkill for only 2 peripherals. Just tack it onto the
main xbar.
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 20c075f..7618c45 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -157,9 +157,9 @@
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
- clk_io_peri: io
clk_aon_peri: aon
clk_usb_peri: usb
+ clk_io_peri: io
}
}
{
@@ -825,122 +825,6 @@
}
}
{
- name: spi_host0
- type: spi_host
- clock_srcs:
- {
- clk_i: io
- }
- clock_group: peri
- reset_connections:
- {
- rst_ni:
- {
- name: spi_host0
- domain: "0"
- }
- }
- clock_connections:
- {
- clk_i: clkmgr_aon_clocks.clk_io_peri
- }
- domain:
- [
- "0"
- ]
- param_decl: {}
- param_list: []
- inter_signal_list:
- [
- {
- name: passthrough
- struct: passthrough
- package: spi_device_pkg
- type: req_rsp
- act: rsp
- width: 1
- inst_name: spi_host0
- default: ""
- top_signame: spi_device_passthrough
- index: -1
- }
- {
- name: tl
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- width: 1
- inst_name: spi_host0
- default: ""
- end_idx: -1
- top_signame: spi_host0_tl
- index: -1
- }
- ]
- base_addrs:
- {
- null: 0x40060000
- }
- }
- {
- name: spi_host1
- type: spi_host
- clock_srcs:
- {
- clk_i: io_div2
- }
- clock_group: peri
- reset_connections:
- {
- rst_ni:
- {
- name: spi_host1
- domain: "0"
- }
- }
- clock_connections:
- {
- clk_i: clkmgr_aon_clocks.clk_io_div2_peri
- }
- domain:
- [
- "0"
- ]
- param_decl: {}
- param_list: []
- inter_signal_list:
- [
- {
- name: passthrough
- struct: passthrough
- package: spi_device_pkg
- type: req_rsp
- act: rsp
- width: 1
- inst_name: spi_host1
- index: -1
- }
- {
- name: tl
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- width: 1
- inst_name: spi_host1
- default: ""
- end_idx: -1
- top_signame: spi_host1_tl
- index: -1
- }
- ]
- base_addrs:
- {
- null: 0x40070000
- }
- }
- {
name: i2c0
type: i2c
clock_srcs:
@@ -2292,6 +2176,122 @@
}
}
{
+ name: spi_host0
+ type: spi_host
+ clock_srcs:
+ {
+ clk_i: io
+ }
+ clock_group: peri
+ reset_connections:
+ {
+ rst_ni:
+ {
+ name: spi_host0
+ domain: "0"
+ }
+ }
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_peri
+ }
+ domain:
+ [
+ "0"
+ ]
+ param_decl: {}
+ param_list: []
+ inter_signal_list:
+ [
+ {
+ name: passthrough
+ struct: passthrough
+ package: spi_device_pkg
+ type: req_rsp
+ act: rsp
+ width: 1
+ inst_name: spi_host0
+ default: ""
+ top_signame: spi_device_passthrough
+ index: -1
+ }
+ {
+ name: tl
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ width: 1
+ inst_name: spi_host0
+ default: ""
+ end_idx: -1
+ top_signame: spi_host0_tl
+ index: -1
+ }
+ ]
+ base_addrs:
+ {
+ null: 0x40300000
+ }
+ }
+ {
+ name: spi_host1
+ type: spi_host
+ clock_srcs:
+ {
+ clk_i: io_div2
+ }
+ clock_group: peri
+ reset_connections:
+ {
+ rst_ni:
+ {
+ name: spi_host1
+ domain: "0"
+ }
+ }
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div2_peri
+ }
+ domain:
+ [
+ "0"
+ ]
+ param_decl: {}
+ param_list: []
+ inter_signal_list:
+ [
+ {
+ name: passthrough
+ struct: passthrough
+ package: spi_device_pkg
+ type: req_rsp
+ act: rsp
+ width: 1
+ inst_name: spi_host1
+ index: -1
+ }
+ {
+ name: tl
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ width: 1
+ inst_name: spi_host1
+ default: ""
+ end_idx: -1
+ top_signame: spi_host1_tl
+ index: -1
+ }
+ ]
+ base_addrs:
+ {
+ null: 0x40310000
+ }
+ }
+ {
name: pwrmgr_aon
type: pwrmgr
clock_group: powerup
@@ -7359,6 +7359,14 @@
[
peri.tl_main
]
+ spi_host0.tl:
+ [
+ main.tl_spi_host0
+ ]
+ spi_host1.tl:
+ [
+ main.tl_spi_host1
+ ]
flash_ctrl.core_tl:
[
main.tl_flash_ctrl__core
@@ -7467,14 +7475,6 @@
[
peri.tl_spi_device
]
- spi_host0.tl:
- [
- peri.tl_spi_host0
- ]
- spi_host1.tl:
- [
- peri.tl_spi_host1
- ]
rv_timer.tl:
[
peri.tl_rv_timer
@@ -7607,6 +7607,8 @@
{
clk_main_i: main
clk_fixed_i: io_div4
+ clk_spi_host0_i: io
+ clk_spi_host1_i: io_div2
}
clock_group: infra
reset: rst_main_ni
@@ -7622,11 +7624,23 @@
name: sys_io_div4
domain: "0"
}
+ rst_spi_host0_ni:
+ {
+ name: spi_host0
+ domain: "0"
+ }
+ rst_spi_host1_ni:
+ {
+ name: spi_host1
+ domain: "0"
+ }
}
clock_connections:
{
clk_main_i: clkmgr_aon_clocks.clk_main_infra
clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
+ clk_spi_host0_i: clkmgr_aon_clocks.clk_io_infra
+ clk_spi_host1_i: clkmgr_aon_clocks.clk_io_div2_infra
}
domain:
[
@@ -7649,6 +7663,8 @@
rv_dm.regs
sram_ctrl_main.ram
peri
+ spi_host0
+ spi_host1
flash_ctrl.core
flash_ctrl.prim
flash_ctrl.mem
@@ -7809,11 +7825,51 @@
[
{
base_addr: 0x40000000
- size_byte: 0x800000
+ size_byte: 0x200000
+ }
+ {
+ base_addr: 0x40400000
+ size_byte: 0x400000
}
]
}
{
+ name: spi_host0
+ type: device
+ clock: clk_spi_host0_i
+ reset: rst_spi_host0_ni
+ pipeline: "false"
+ inst_type: spi_host
+ addr_range:
+ [
+ {
+ base_addr: 0x40300000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: spi_host1
+ type: device
+ clock: clk_spi_host1_i
+ reset: rst_spi_host1_ni
+ pipeline: "false"
+ inst_type: spi_host
+ addr_range:
+ [
+ {
+ base_addr: 0x40310000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
name: flash_ctrl.core
type: device
clock: clk_main_i
@@ -8207,6 +8263,30 @@
index: -1
}
{
+ name: tl_spi_host0
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: req
+ width: 1
+ inst_name: main
+ default: ""
+ top_signame: spi_host0_tl
+ index: -1
+ }
+ {
+ name: tl_spi_host1
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: req
+ width: 1
+ inst_name: main
+ default: ""
+ top_signame: spi_host1_tl
+ index: -1
+ }
+ {
name: tl_flash_ctrl__core
struct: tl
package: tlul_pkg
@@ -8405,8 +8485,6 @@
clock_srcs:
{
clk_peri_i: io_div4
- clk_spi_host0_i: io
- clk_spi_host1_i: io_div2
}
clock_group: infra
reset: rst_peri_ni
@@ -8417,22 +8495,10 @@
name: sys_io_div4
domain: "0"
}
- rst_spi_host0_ni:
- {
- name: spi_host0
- domain: "0"
- }
- rst_spi_host1_ni:
- {
- name: spi_host1
- domain: "0"
- }
}
clock_connections:
{
clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
- clk_spi_host0_i: clkmgr_aon_clocks.clk_io_infra
- clk_spi_host1_i: clkmgr_aon_clocks.clk_io_div2_infra
}
domain:
[
@@ -8452,8 +8518,6 @@
pattgen
gpio
spi_device
- spi_host0
- spi_host1
rv_timer
usbdev
pwrmgr_aon
@@ -8686,42 +8750,6 @@
pipeline_byp: "true"
}
{
- name: spi_host0
- type: device
- clock: clk_spi_host0_i
- reset: rst_spi_host0_ni
- pipeline: "false"
- inst_type: spi_host
- addr_range:
- [
- {
- base_addr: 0x40060000
- size_byte: 0x1000
- }
- ]
- xbar: false
- stub: false
- pipeline_byp: "true"
- }
- {
- name: spi_host1
- type: device
- clock: clk_spi_host1_i
- reset: rst_spi_host1_ni
- pipeline: "false"
- inst_type: spi_host
- addr_range:
- [
- {
- base_addr: 0x40070000
- size_byte: 0x1000
- }
- ]
- xbar: false
- stub: false
- pipeline_byp: "true"
- }
- {
name: rv_timer
type: device
clock: clk_peri_i
@@ -9177,30 +9205,6 @@
index: -1
}
{
- name: tl_spi_host0
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: req
- width: 1
- inst_name: peri
- default: ""
- top_signame: spi_host0_tl
- index: -1
- }
- {
- name: tl_spi_host1
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: req
- width: 1
- inst_name: peri
- default: ""
- top_signame: spi_host1_tl
- index: -1
- }
- {
name: tl_rv_timer
struct: tl
package: tlul_pkg
@@ -12218,8 +12222,6 @@
uart3
gpio
spi_device
- spi_host0
- spi_host1
i2c0
i2c1
i2c2
@@ -12228,6 +12230,8 @@
usbdev
otp_ctrl
alert_handler
+ spi_host0
+ spi_host1
pwrmgr_aon
sysrst_ctrl_aon
adc_ctrl_aon
@@ -12485,30 +12489,6 @@
module_name: spi_device
}
{
- name: spi_host0_error
- width: 1
- type: interrupt
- module_name: spi_host0
- }
- {
- name: spi_host0_spi_event
- width: 1
- type: interrupt
- module_name: spi_host0
- }
- {
- name: spi_host1_error
- width: 1
- type: interrupt
- module_name: spi_host1
- }
- {
- name: spi_host1_spi_event
- width: 1
- type: interrupt
- module_name: spi_host1
- }
- {
name: i2c0_fmt_watermark
width: 1
type: interrupt
@@ -12953,6 +12933,30 @@
module_name: alert_handler
}
{
+ name: spi_host0_error
+ width: 1
+ type: interrupt
+ module_name: spi_host0
+ }
+ {
+ name: spi_host0_spi_event
+ width: 1
+ type: interrupt
+ module_name: spi_host0
+ }
+ {
+ name: spi_host1_error
+ width: 1
+ type: interrupt
+ module_name: spi_host1
+ }
+ {
+ name: spi_host1_spi_event
+ width: 1
+ type: interrupt
+ module_name: spi_host1
+ }
+ {
name: pwrmgr_aon_wakeup
width: 1
type: interrupt
@@ -13147,8 +13151,6 @@
uart3
gpio
spi_device
- spi_host0
- spi_host1
i2c0
i2c1
i2c2
@@ -13157,6 +13159,8 @@
usbdev
otp_ctrl
lc_ctrl
+ spi_host0
+ spi_host1
pwrmgr_aon
rstmgr_aon
clkmgr_aon
@@ -13240,31 +13244,13 @@
lpg_idx: 1
}
{
- name: spi_host0_fatal_fault
- width: 1
- type: alert
- async: "1"
- module_name: spi_host0
- lpg_name: peri_spi_host0_0
- lpg_idx: 2
- }
- {
- name: spi_host1_fatal_fault
- width: 1
- type: alert
- async: "1"
- module_name: spi_host1
- lpg_name: peri_spi_host1_0
- lpg_idx: 3
- }
- {
name: i2c0_fatal_fault
width: 1
type: alert
async: "1"
module_name: i2c0
lpg_name: peri_i2c0_0
- lpg_idx: 4
+ lpg_idx: 2
}
{
name: i2c1_fatal_fault
@@ -13273,7 +13259,7 @@
async: "1"
module_name: i2c1
lpg_name: peri_i2c1_0
- lpg_idx: 5
+ lpg_idx: 3
}
{
name: i2c2_fatal_fault
@@ -13282,7 +13268,7 @@
async: "1"
module_name: i2c2
lpg_name: peri_i2c2_0
- lpg_idx: 6
+ lpg_idx: 4
}
{
name: pattgen_fatal_fault
@@ -13300,7 +13286,7 @@
async: "1"
module_name: rv_timer
lpg_name: timers_sys_io_div4_0
- lpg_idx: 7
+ lpg_idx: 5
}
{
name: usbdev_fatal_fault
@@ -13309,7 +13295,7 @@
async: "1"
module_name: usbdev
lpg_name: peri_usb_0
- lpg_idx: 8
+ lpg_idx: 6
}
{
name: otp_ctrl_fatal_macro_error
@@ -13318,7 +13304,7 @@
async: "1"
module_name: otp_ctrl
lpg_name: secure_lc_io_div4_0
- lpg_idx: 9
+ lpg_idx: 7
}
{
name: otp_ctrl_fatal_check_error
@@ -13327,7 +13313,7 @@
async: "1"
module_name: otp_ctrl
lpg_name: secure_lc_io_div4_0
- lpg_idx: 9
+ lpg_idx: 7
}
{
name: otp_ctrl_fatal_bus_integ_error
@@ -13336,7 +13322,7 @@
async: "1"
module_name: otp_ctrl
lpg_name: secure_lc_io_div4_0
- lpg_idx: 9
+ lpg_idx: 7
}
{
name: lc_ctrl_fatal_prog_error
@@ -13345,7 +13331,7 @@
async: "1"
module_name: lc_ctrl
lpg_name: secure_lc_io_div4_0
- lpg_idx: 9
+ lpg_idx: 7
}
{
name: lc_ctrl_fatal_state_error
@@ -13354,7 +13340,7 @@
async: "1"
module_name: lc_ctrl
lpg_name: secure_lc_io_div4_0
- lpg_idx: 9
+ lpg_idx: 7
}
{
name: lc_ctrl_fatal_bus_integ_error
@@ -13363,6 +13349,24 @@
async: "1"
module_name: lc_ctrl
lpg_name: secure_lc_io_div4_0
+ lpg_idx: 7
+ }
+ {
+ name: spi_host0_fatal_fault
+ width: 1
+ type: alert
+ async: "1"
+ module_name: spi_host0
+ lpg_name: peri_spi_host0_0
+ lpg_idx: 8
+ }
+ {
+ name: spi_host1_fatal_fault
+ width: 1
+ type: alert
+ async: "1"
+ module_name: spi_host1
+ lpg_name: peri_spi_host1_0
lpg_idx: 9
}
{
@@ -13732,26 +13736,6 @@
}
}
{
- name: peri_spi_host0_0
- clock_group: peri
- clock_connection: clkmgr_aon_clocks.clk_io_peri
- reset_connection:
- {
- name: spi_host0
- domain: "0"
- }
- }
- {
- name: peri_spi_host1_0
- clock_group: peri
- clock_connection: clkmgr_aon_clocks.clk_io_div2_peri
- reset_connection:
- {
- name: spi_host1
- domain: "0"
- }
- }
- {
name: peri_i2c0_0
clock_group: peri
clock_connection: clkmgr_aon_clocks.clk_io_div4_peri
@@ -13812,6 +13796,26 @@
}
}
{
+ name: peri_spi_host0_0
+ clock_group: peri
+ clock_connection: clkmgr_aon_clocks.clk_io_peri
+ reset_connection:
+ {
+ name: spi_host0
+ domain: "0"
+ }
+ }
+ {
+ name: peri_spi_host1_0
+ clock_group: peri
+ clock_connection: clkmgr_aon_clocks.clk_io_div2_peri
+ reset_connection:
+ {
+ name: spi_host1
+ domain: "0"
+ }
+ }
+ {
name: powerup_por_io_div4_Aon
clock_group: powerup
clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup
@@ -14042,54 +14046,6 @@
index: -1
}
{
- name: passthrough
- struct: passthrough
- package: spi_device_pkg
- type: req_rsp
- act: rsp
- width: 1
- inst_name: spi_host0
- default: ""
- top_signame: spi_device_passthrough
- index: -1
- }
- {
- name: tl
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- width: 1
- inst_name: spi_host0
- default: ""
- end_idx: -1
- top_signame: spi_host0_tl
- index: -1
- }
- {
- name: passthrough
- struct: passthrough
- package: spi_device_pkg
- type: req_rsp
- act: rsp
- width: 1
- inst_name: spi_host1
- index: -1
- }
- {
- name: tl
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- width: 1
- inst_name: spi_host1
- default: ""
- end_idx: -1
- top_signame: spi_host1_tl
- index: -1
- }
- {
name: tl
struct: tl
package: tlul_pkg
@@ -15011,6 +14967,54 @@
index: -1
}
{
+ name: passthrough
+ struct: passthrough
+ package: spi_device_pkg
+ type: req_rsp
+ act: rsp
+ width: 1
+ inst_name: spi_host0
+ default: ""
+ top_signame: spi_device_passthrough
+ index: -1
+ }
+ {
+ name: tl
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ width: 1
+ inst_name: spi_host0
+ default: ""
+ end_idx: -1
+ top_signame: spi_host0_tl
+ index: -1
+ }
+ {
+ name: passthrough
+ struct: passthrough
+ package: spi_device_pkg
+ type: req_rsp
+ act: rsp
+ width: 1
+ inst_name: spi_host1
+ index: -1
+ }
+ {
+ name: tl
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ width: 1
+ inst_name: spi_host1
+ default: ""
+ end_idx: -1
+ top_signame: spi_host1_tl
+ index: -1
+ }
+ {
name: pwr_ast
struct: pwr_ast
package: pwrmgr_pkg
@@ -17697,6 +17701,30 @@
index: -1
}
{
+ name: tl_spi_host0
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: req
+ width: 1
+ inst_name: main
+ default: ""
+ top_signame: spi_host0_tl
+ index: -1
+ }
+ {
+ name: tl_spi_host1
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: req
+ width: 1
+ inst_name: main
+ default: ""
+ top_signame: spi_host1_tl
+ index: -1
+ }
+ {
name: tl_flash_ctrl__core
struct: tl
package: tlul_pkg
@@ -18033,30 +18061,6 @@
index: -1
}
{
- name: tl_spi_host0
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: req
- width: 1
- inst_name: peri
- default: ""
- top_signame: spi_host0_tl
- index: -1
- }
- {
- name: tl_spi_host1
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: req
- width: 1
- inst_name: peri
- default: ""
- top_signame: spi_host1_tl
- index: -1
- }
- {
name: tl_rv_timer
struct: tl
package: tlul_pkg
@@ -20000,6 +20004,50 @@
{
package: tlul_pkg
struct: tl_h2d
+ signame: spi_host0_tl_req
+ width: 1
+ type: req_rsp
+ end_idx: -1
+ act: rsp
+ suffix: req
+ default: tlul_pkg::TL_H2D_DEFAULT
+ }
+ {
+ package: tlul_pkg
+ struct: tl_d2h
+ signame: spi_host0_tl_rsp
+ width: 1
+ type: req_rsp
+ end_idx: -1
+ act: rsp
+ suffix: rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_h2d
+ signame: spi_host1_tl_req
+ width: 1
+ type: req_rsp
+ end_idx: -1
+ act: rsp
+ suffix: req
+ default: tlul_pkg::TL_H2D_DEFAULT
+ }
+ {
+ package: tlul_pkg
+ struct: tl_d2h
+ signame: spi_host1_tl_rsp
+ width: 1
+ type: req_rsp
+ end_idx: -1
+ act: rsp
+ suffix: rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_h2d
signame: flash_ctrl_core_tl_req
width: 1
type: req_rsp
@@ -20594,50 +20642,6 @@
{
package: tlul_pkg
struct: tl_h2d
- signame: spi_host0_tl_req
- width: 1
- type: req_rsp
- end_idx: -1
- act: rsp
- suffix: req
- default: tlul_pkg::TL_H2D_DEFAULT
- }
- {
- package: tlul_pkg
- struct: tl_d2h
- signame: spi_host0_tl_rsp
- width: 1
- type: req_rsp
- end_idx: -1
- act: rsp
- suffix: rsp
- default: ""
- }
- {
- package: tlul_pkg
- struct: tl_h2d
- signame: spi_host1_tl_req
- width: 1
- type: req_rsp
- end_idx: -1
- act: rsp
- suffix: req
- default: tlul_pkg::TL_H2D_DEFAULT
- }
- {
- package: tlul_pkg
- struct: tl_d2h
- signame: spi_host1_tl_rsp
- width: 1
- type: req_rsp
- end_idx: -1
- act: rsp
- suffix: rsp
- default: ""
- }
- {
- package: tlul_pkg
- struct: tl_h2d
signame: rv_timer_tl_req
width: 1
type: req_rsp
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index b903b45..b10e836 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -249,20 +249,6 @@
reset_connections: {rst_ni: "spi_device"},
base_addr: "0x40050000",
},
- { name: "spi_host0",
- type: "spi_host",
- clock_srcs: {clk_i: "io"},
- clock_group: "peri",
- reset_connections: {rst_ni: "spi_host0"},
- base_addr: "0x40060000",
- },
- { name: "spi_host1",
- type: "spi_host",
- clock_srcs: {clk_i: "io_div2"},
- clock_group: "peri",
- reset_connections: {rst_ni: "spi_host1"},
- base_addr: "0x40070000",
- },
{ name: "i2c0",
type: "i2c",
clock_srcs: {clk_i: "io_div4"},
@@ -327,6 +313,20 @@
base_addr: "0x40150000",
attr: "templated",
},
+ { name: "spi_host0",
+ type: "spi_host",
+ clock_srcs: {clk_i: "io"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "spi_host0"},
+ base_addr: "0x40300000",
+ },
+ { name: "spi_host1",
+ type: "spi_host",
+ clock_srcs: {clk_i: "io_div2"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "spi_host1"},
+ base_addr: "0x40310000",
+ },
{ name: "pwrmgr_aon",
type: "pwrmgr",
clock_group: "powerup",
@@ -999,18 +999,22 @@
// Assume xbar.hjson is located in the same directory of top.hjson
xbar: [
{ name: "main",
- clock_srcs: {clk_main_i: "main", clk_fixed_i: "io_div4"},
+ clock_srcs: {clk_main_i: "main",
+ clk_fixed_i: "io_div4",
+ clk_spi_host0_i: "io",
+ clk_spi_host1_i: "io_div2"},
clock_group: "infra",
reset: "sys",
- reset_connections: {rst_main_ni: "sys", rst_fixed_ni: "sys_io_div4"}
+ reset_connections: {rst_main_ni: "sys",
+ rst_fixed_ni: "sys_io_div4",
+ rst_spi_host0_ni: "spi_host0",
+ rst_spi_host1_ni: "spi_host1"}
},
{ name: "peri",
- clock_srcs: {clk_peri_i: "io_div4", clk_spi_host0_i: "io", clk_spi_host1_i: "io_div2"},
+ clock_srcs: {clk_peri_i: "io_div4", },
clock_group: "infra",
reset: "sys_io_div4",
- reset_connections: {rst_peri_ni: "sys_io_div4",
- rst_spi_host0_ni: "spi_host0",
- rst_spi_host1_ni: "spi_host1"},
+ reset_connections: {rst_peri_ni: "sys_io_div4"},
}
],
diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson
index 9822089..4dc6a21 100644
--- a/hw/top_earlgrey/data/xbar_main.hjson
+++ b/hw/top_earlgrey/data/xbar_main.hjson
@@ -4,9 +4,9 @@
{ name: "main",
type: "xbar",
clock_primary: "clk_main_i", // Main clock, used in sockets
- other_clock_list: [ "clk_fixed_i" ] // Secondary clocks used by specific nodes
+ other_clock_list: [ "clk_fixed_i", "clk_spi_host0_i", "clk_spi_host1_i" ] // Secondary clocks used by specific nodes
reset_primary: "rst_main_ni", // Main reset, used in sockets
- other_reset_list: [ "rst_fixed_ni" ] // Secondary clocks used by specific nodes
+ other_reset_list: [ "rst_fixed_ni", "rst_spi_host0_ni", "rst_spi_host1_ni"] // Secondary clocks used by specific nodes
nodes: [
{ name: "rv_core_ibex.corei",
@@ -58,6 +58,18 @@
reset: "rst_fixed_ni",
pipeline_byp: "false"
},
+ { name: "spi_host0",
+ type: "device",
+ clock: "clk_spi_host0_i",
+ reset: "rst_spi_host0_ni",
+ pipeline: "false"
+ },
+ { name: "spi_host1",
+ type: "device",
+ clock: "clk_spi_host1_i",
+ reset: "rst_spi_host1_ni",
+ pipeline: "false"
+ },
{ name: "flash_ctrl.core",
type: "device",
clock: "clk_main_i",
@@ -160,7 +172,8 @@
rv_core_ibex.corei: ["rom_ctrl.rom", "rv_dm.rom", "sram_ctrl_main.ram", "flash_ctrl.mem"],
rv_core_ibex.cored: [
"rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.rom", "rv_dm.regs",
- "sram_ctrl_main.ram", "peri", "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem",
+ "sram_ctrl_main.ram", "peri", "spi_host0", "spi_host1",
+ "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem",
"aes", "entropy_src", "csrng", "edn0", "edn1", "hmac",
"rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs",
"rv_core_ibex.cfg"
diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson
index a8e3d25..2f6b473 100644
--- a/hw/top_earlgrey/data/xbar_peri.hjson
+++ b/hw/top_earlgrey/data/xbar_peri.hjson
@@ -4,9 +4,9 @@
{ name: "peri",
type: "xbar",
clock_primary: "clk_peri_i", // Main clock, used in sockets
- other_clock_list: [ "clk_spi_host0_i", "clk_spi_host1_i" ] // Secondary clocks used by specific nodes
+ other_clock_list: [] // Secondary clocks used by specific nodes
reset_primary: "rst_peri_ni", // Main reset, used in sockets
- other_reset_list: [ "rst_spi_host0_ni", "rst_spi_host1_ni" ] // Secondary resets used by specific nodes
+ other_reset_list: [] // Secondary resets used by specific nodes
nodes: [
{ name: "main",
@@ -83,18 +83,6 @@
reset: "rst_peri_ni",
pipeline: "false"
},
- { name: "spi_host0",
- type: "device",
- clock: "clk_spi_host0_i",
- reset: "rst_spi_host0_ni",
- pipeline: "false"
- },
- { name: "spi_host1",
- type: "device",
- clock: "clk_spi_host1_i",
- reset: "rst_spi_host1_ni",
- pipeline: "false"
- },
{ name: "rv_timer",
type: "device",
clock: "clk_peri_i",
@@ -201,7 +189,7 @@
connections: {
main: [
"uart0", "uart1", "uart2", "uart3", "i2c0", "i2c1", "i2c2", "pattgen",
- "gpio", "spi_device", "spi_host0", "spi_host1", "rv_timer", "usbdev",
+ "gpio", "spi_device", "rv_timer", "usbdev",
"pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon",
"otp_ctrl.core", "otp_ctrl.prim", "lc_ctrl", "sensor_ctrl",
"alert_handler", "ast", "sram_ctrl_ret_aon.ram", "sram_ctrl_ret_aon.regs",
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index d3a4326..fe4f224 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -10,20 +10,20 @@
assign alert_if[3].alert_tx = `CHIP_HIER.u_uart3.alert_tx_o[0];
assign alert_if[4].alert_tx = `CHIP_HIER.u_gpio.alert_tx_o[0];
assign alert_if[5].alert_tx = `CHIP_HIER.u_spi_device.alert_tx_o[0];
-assign alert_if[6].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0];
-assign alert_if[7].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0];
-assign alert_if[8].alert_tx = `CHIP_HIER.u_i2c0.alert_tx_o[0];
-assign alert_if[9].alert_tx = `CHIP_HIER.u_i2c1.alert_tx_o[0];
-assign alert_if[10].alert_tx = `CHIP_HIER.u_i2c2.alert_tx_o[0];
-assign alert_if[11].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0];
-assign alert_if[12].alert_tx = `CHIP_HIER.u_rv_timer.alert_tx_o[0];
-assign alert_if[13].alert_tx = `CHIP_HIER.u_usbdev.alert_tx_o[0];
-assign alert_if[14].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
-assign alert_if[15].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
-assign alert_if[16].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[2];
-assign alert_if[17].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
-assign alert_if[18].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
+assign alert_if[6].alert_tx = `CHIP_HIER.u_i2c0.alert_tx_o[0];
+assign alert_if[7].alert_tx = `CHIP_HIER.u_i2c1.alert_tx_o[0];
+assign alert_if[8].alert_tx = `CHIP_HIER.u_i2c2.alert_tx_o[0];
+assign alert_if[9].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0];
+assign alert_if[10].alert_tx = `CHIP_HIER.u_rv_timer.alert_tx_o[0];
+assign alert_if[11].alert_tx = `CHIP_HIER.u_usbdev.alert_tx_o[0];
+assign alert_if[12].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
+assign alert_if[13].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
+assign alert_if[14].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[2];
+assign alert_if[15].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
+assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
+assign alert_if[17].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0];
assign alert_if[20].alert_tx = `CHIP_HIER.u_pwrmgr_aon.alert_tx_o[0];
assign alert_if[21].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[0];
assign alert_if[22].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[0];
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
index 4a6e834..84758a9 100644
--- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -41,6 +41,8 @@
tl_if rv_dm__rom_tl_if(clk_main, rst_n);
tl_if rom_ctrl__rom_tl_if(clk_main, rst_n);
tl_if rom_ctrl__regs_tl_if(clk_main, rst_n);
+tl_if spi_host0_tl_if(clk_io, rst_n);
+tl_if spi_host1_tl_if(clk_io_div2, rst_n);
tl_if flash_ctrl__core_tl_if(clk_main, rst_n);
tl_if flash_ctrl__prim_tl_if(clk_main, rst_n);
tl_if flash_ctrl__mem_tl_if(clk_main, rst_n);
@@ -68,8 +70,6 @@
tl_if pwm_aon_tl_if(clk_io_div4, rst_n);
tl_if gpio_tl_if(clk_io_div4, rst_n);
tl_if spi_device_tl_if(clk_io_div4, rst_n);
-tl_if spi_host0_tl_if(clk_io, rst_n);
-tl_if spi_host1_tl_if(clk_io_div2, rst_n);
tl_if rv_timer_tl_if(clk_io_div4, rst_n);
tl_if usbdev_tl_if(clk_io_div4, rst_n);
tl_if pwrmgr_aon_tl_if(clk_io_div4, rst_n);
@@ -109,16 +109,16 @@
// bypass clkmgr, force clocks directly
force tb.dut.top_earlgrey.u_xbar_main.clk_main_i = clk_main;
force tb.dut.top_earlgrey.u_xbar_main.clk_fixed_i = clk_io_div4;
+ force tb.dut.top_earlgrey.u_xbar_main.clk_spi_host0_i = clk_io;
+ force tb.dut.top_earlgrey.u_xbar_main.clk_spi_host1_i = clk_io_div2;
force tb.dut.top_earlgrey.u_xbar_peri.clk_peri_i = clk_io_div4;
- force tb.dut.top_earlgrey.u_xbar_peri.clk_spi_host0_i = clk_io;
- force tb.dut.top_earlgrey.u_xbar_peri.clk_spi_host1_i = clk_io_div2;
// bypass rstmgr, force resets directly
force tb.dut.top_earlgrey.u_xbar_main.rst_main_ni = rst_n;
force tb.dut.top_earlgrey.u_xbar_main.rst_fixed_ni = rst_n;
+ force tb.dut.top_earlgrey.u_xbar_main.rst_spi_host0_ni = rst_n;
+ force tb.dut.top_earlgrey.u_xbar_main.rst_spi_host1_ni = rst_n;
force tb.dut.top_earlgrey.u_xbar_peri.rst_peri_ni = rst_n;
- force tb.dut.top_earlgrey.u_xbar_peri.rst_spi_host0_ni = rst_n;
- force tb.dut.top_earlgrey.u_xbar_peri.rst_spi_host1_ni = rst_n;
`DRIVE_CHIP_TL_HOST_IF(rv_core_ibex__corei, rv_core_ibex, corei_tl_h)
`DRIVE_CHIP_TL_HOST_IF(rv_core_ibex__cored, rv_core_ibex, cored_tl_h)
@@ -127,6 +127,8 @@
`DRIVE_CHIP_TL_DEVICE_IF(rv_dm__rom, rv_dm, rom_tl_d)
`DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl__rom, rom_ctrl, rom_tl)
`DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl__regs, rom_ctrl, regs_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(spi_host0, spi_host0, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(spi_host1, spi_host1, tl)
`DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__core, flash_ctrl, core_tl)
`DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__prim, flash_ctrl, prim_tl)
`DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__mem, flash_ctrl, mem_tl)
@@ -154,8 +156,6 @@
`DRIVE_CHIP_TL_DEVICE_IF(pwm_aon, pwm_aon, tl)
`DRIVE_CHIP_TL_DEVICE_IF(gpio, gpio, tl)
`DRIVE_CHIP_TL_DEVICE_IF(spi_device, spi_device, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(spi_host0, spi_host0, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(spi_host1, spi_host1, tl)
`DRIVE_CHIP_TL_DEVICE_IF(rv_timer, rv_timer, tl)
`DRIVE_CHIP_TL_DEVICE_IF(usbdev, usbdev, tl)
`DRIVE_CHIP_TL_DEVICE_IF(pwrmgr_aon, pwrmgr_aon, tl)
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
index 0b6ee6c..dddc6c3 100644
--- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -19,6 +19,12 @@
'{"rom_ctrl__regs", '{
'{32'h411e0000, 32'h411e0fff}
}},
+ '{"spi_host0", '{
+ '{32'h40300000, 32'h40300fff}
+ }},
+ '{"spi_host1", '{
+ '{32'h40310000, 32'h40310fff}
+ }},
'{"flash_ctrl__core", '{
'{32'h41000000, 32'h41000fff}
}},
@@ -100,12 +106,6 @@
'{"spi_device", '{
'{32'h40050000, 32'h40051fff}
}},
- '{"spi_host0", '{
- '{32'h40060000, 32'h40060fff}
- }},
- '{"spi_host1", '{
- '{32'h40070000, 32'h40070fff}
- }},
'{"rv_timer", '{
'{32'h40100000, 32'h40100fff}
}},
@@ -182,8 +182,6 @@
"pattgen",
"gpio",
"spi_device",
- "spi_host0",
- "spi_host1",
"rv_timer",
"usbdev",
"pwrmgr_aon",
@@ -202,6 +200,8 @@
"adc_ctrl_aon",
"sysrst_ctrl_aon",
"pwm_aon",
+ "spi_host0",
+ "spi_host1",
"flash_ctrl__core",
"flash_ctrl__prim",
"flash_ctrl__mem",
@@ -233,8 +233,6 @@
"pattgen",
"gpio",
"spi_device",
- "spi_host0",
- "spi_host1",
"rv_timer",
"usbdev",
"pwrmgr_aon",
diff --git a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg
index 3b9a3c0..d1f8103 100644
--- a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg
+++ b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg
@@ -34,6 +34,13 @@
-node tb.dut*.u_rom_ctrl__regs *tl_i.a_address[23:21]
-node tb.dut*.u_rom_ctrl__regs *tl_i.a_address[29:25]
-node tb.dut*.u_rom_ctrl__regs *tl_i.a_address[31:31]
+-node tb.dut*.u_spi_host0 *tl_i.a_address[19:12]
+-node tb.dut*.u_spi_host0 *tl_i.a_address[29:22]
+-node tb.dut*.u_spi_host0 *tl_i.a_address[31:31]
+-node tb.dut*.u_spi_host1 *tl_i.a_address[15:12]
+-node tb.dut*.u_spi_host1 *tl_i.a_address[19:17]
+-node tb.dut*.u_spi_host1 *tl_i.a_address[29:22]
+-node tb.dut*.u_spi_host1 *tl_i.a_address[31:31]
-node tb.dut*.u_flash_ctrl__core *tl_i.a_address[23:12]
-node tb.dut*.u_flash_ctrl__core *tl_i.a_address[29:25]
-node tb.dut*.u_flash_ctrl__core *tl_i.a_address[31:31]
@@ -135,12 +142,6 @@
-node tb.dut*.u_spi_device *tl_i.a_address[17:17]
-node tb.dut*.u_spi_device *tl_i.a_address[29:19]
-node tb.dut*.u_spi_device *tl_i.a_address[31:31]
--node tb.dut*.u_spi_host0 *tl_i.a_address[16:12]
--node tb.dut*.u_spi_host0 *tl_i.a_address[29:19]
--node tb.dut*.u_spi_host0 *tl_i.a_address[31:31]
--node tb.dut*.u_spi_host1 *tl_i.a_address[15:12]
--node tb.dut*.u_spi_host1 *tl_i.a_address[29:19]
--node tb.dut*.u_spi_host1 *tl_i.a_address[31:31]
-node tb.dut*.u_rv_timer *tl_i.a_address[19:12]
-node tb.dut*.u_rv_timer *tl_i.a_address[29:21]
-node tb.dut*.u_rv_timer *tl_i.a_address[31:31]
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index e198abd..61e8034 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -11,8 +11,6 @@
"uart3_fatal_fault",
"gpio_fatal_fault",
"spi_device_fatal_fault",
- "spi_host0_fatal_fault",
- "spi_host1_fatal_fault",
"i2c0_fatal_fault",
"i2c1_fatal_fault",
"i2c2_fatal_fault",
@@ -25,6 +23,8 @@
"lc_ctrl_fatal_prog_error",
"lc_ctrl_fatal_state_error",
"lc_ctrl_fatal_bus_integ_error",
+ "spi_host0_fatal_fault",
+ "spi_host1_fatal_fault",
"pwrmgr_aon_fatal_fault",
"rstmgr_aon_fatal_fault",
"clkmgr_aon_recov_fault",
diff --git a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
index 1ec7278..32b29fa 100644
--- a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
+++ b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
@@ -258,15 +258,6 @@
}
{
bits: "2",
- name: "CLK_IO_PERI_EN",
- resval: 1,
- desc: '''
- 0 CLK_IO_PERI is disabled.
- 1 CLK_IO_PERI is enabled.
- '''
- }
- {
- bits: "3",
name: "CLK_USB_PERI_EN",
resval: 1,
desc: '''
@@ -274,6 +265,15 @@
1 CLK_USB_PERI is enabled.
'''
}
+ {
+ bits: "3",
+ name: "CLK_IO_PERI_EN",
+ resval: 1,
+ desc: '''
+ 0 CLK_IO_PERI is disabled.
+ 1 CLK_IO_PERI is enabled.
+ '''
+ }
]
// the CLK_ENABLE register cannot be written, otherwise there is the potential clocks could be
// disabled and the system will hang
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index 067aa27..ccf750f 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -824,8 +824,8 @@
logic clk_io_div4_peri_sw_en;
logic clk_io_div2_peri_sw_en;
- logic clk_io_peri_sw_en;
logic clk_usb_peri_sw_en;
+ logic clk_io_peri_sw_en;
prim_flop_2sync #(
.Width(1)
@@ -911,47 +911,6 @@
prim_flop_2sync #(
.Width(1)
- ) u_clk_io_peri_sw_en_sync (
- .clk_i(clk_io_i),
- .rst_ni(rst_io_ni),
- .d_i(reg2hw.clk_enables.clk_io_peri_en.q),
- .q_o(clk_io_peri_sw_en)
- );
-
- prim_mubi_pkg::mubi4_t clk_io_peri_scanmode;
- prim_mubi4_sync #(
- .NumCopies(1),
- .AsyncOn(0)
- ) u_clk_io_peri_scanmode_sync (
- .clk_i(1'b0), //unused
- .rst_ni(1'b1), //unused
- .mubi_i(scanmode_i),
- .mubi_o(clk_io_peri_scanmode)
- );
-
- logic clk_io_peri_combined_en;
- assign clk_io_peri_combined_en = clk_io_peri_sw_en & clk_io_en;
- prim_clock_gating #(
- .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
- ) u_clk_io_peri_cg (
- .clk_i(clk_io_root),
- .en_i(clk_io_peri_combined_en),
- .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_io_peri_scanmode)),
- .clk_o(clocks_o.clk_io_peri)
- );
-
- // clock gated indication for alert handler
- prim_mubi4_sender #(
- .ResetValue(MuBi4True)
- ) u_prim_mubi4_sender_clk_io_peri (
- .clk_i(clk_io_i),
- .rst_ni(rst_io_ni),
- .mubi_i(((clk_io_peri_combined_en) ? MuBi4False : MuBi4True)),
- .mubi_o(cg_en_o.io_peri)
- );
-
- prim_flop_2sync #(
- .Width(1)
) u_clk_usb_peri_sw_en_sync (
.clk_i(clk_usb_i),
.rst_ni(rst_usb_ni),
@@ -991,6 +950,47 @@
.mubi_o(cg_en_o.usb_peri)
);
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_clk_io_peri_sw_en_sync (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_io_ni),
+ .d_i(reg2hw.clk_enables.clk_io_peri_en.q),
+ .q_o(clk_io_peri_sw_en)
+ );
+
+ prim_mubi_pkg::mubi4_t clk_io_peri_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_clk_io_peri_scanmode_sync (
+ .clk_i(1'b0), //unused
+ .rst_ni(1'b1), //unused
+ .mubi_i(scanmode_i),
+ .mubi_o(clk_io_peri_scanmode)
+ );
+
+ logic clk_io_peri_combined_en;
+ assign clk_io_peri_combined_en = clk_io_peri_sw_en & clk_io_en;
+ prim_clock_gating #(
+ .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
+ ) u_clk_io_peri_cg (
+ .clk_i(clk_io_root),
+ .en_i(clk_io_peri_combined_en),
+ .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_io_peri_scanmode)),
+ .clk_o(clocks_o.clk_io_peri)
+ );
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_io_peri (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_io_ni),
+ .mubi_i(((clk_io_peri_combined_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.io_peri)
+ );
+
////////////////////////////////////////////////////
// Software hint group
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
index 08b8f39..6fe992f 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
@@ -47,8 +47,8 @@
logic clk_io_div4_timers;
logic clk_io_div4_peri;
logic clk_io_div2_peri;
- logic clk_io_peri;
logic clk_usb_peri;
+ logic clk_io_peri;
} clkmgr_out_t;
// clock gating indication for alert handler
@@ -78,8 +78,8 @@
prim_mubi_pkg::mubi4_t io_div4_timers;
prim_mubi_pkg::mubi4_t io_div4_peri;
prim_mubi_pkg::mubi4_t io_div2_peri;
- prim_mubi_pkg::mubi4_t io_peri;
prim_mubi_pkg::mubi4_t usb_peri;
+ prim_mubi_pkg::mubi4_t io_peri;
} clkmgr_cg_en_t;
parameter int NumOutputClk = 27;
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv
index 0ccf42e..328e60e 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv
@@ -52,10 +52,10 @@
} clk_io_div2_peri_en;
struct packed {
logic q;
- } clk_io_peri_en;
+ } clk_usb_peri_en;
struct packed {
logic q;
- } clk_usb_peri_en;
+ } clk_io_peri_en;
} clkmgr_reg2hw_clk_enables_reg_t;
typedef struct packed {
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
index 7a7a2b3..57cb224 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
@@ -197,10 +197,10 @@
logic clk_enables_clk_io_div4_peri_en_wd;
logic clk_enables_clk_io_div2_peri_en_qs;
logic clk_enables_clk_io_div2_peri_en_wd;
- logic clk_enables_clk_io_peri_en_qs;
- logic clk_enables_clk_io_peri_en_wd;
logic clk_enables_clk_usb_peri_en_qs;
logic clk_enables_clk_usb_peri_en_wd;
+ logic clk_enables_clk_io_peri_en_qs;
+ logic clk_enables_clk_io_peri_en_wd;
logic clk_hints_we;
logic clk_hints_clk_main_aes_hint_qs;
logic clk_hints_clk_main_aes_hint_wd;
@@ -646,32 +646,7 @@
.qs (clk_enables_clk_io_div2_peri_en_qs)
);
- // F[clk_io_peri_en]: 2:2
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h1)
- ) u_clk_enables_clk_io_peri_en (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (clk_enables_we),
- .wd (clk_enables_clk_io_peri_en_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.clk_enables.clk_io_peri_en.q),
-
- // to register interface (read)
- .qs (clk_enables_clk_io_peri_en_qs)
- );
-
- // F[clk_usb_peri_en]: 3:3
+ // F[clk_usb_peri_en]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
@@ -696,6 +671,31 @@
.qs (clk_enables_clk_usb_peri_en_qs)
);
+ // F[clk_io_peri_en]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_enables_clk_io_peri_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_enables_we),
+ .wd (clk_enables_clk_io_peri_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_enables.clk_io_peri_en.q),
+
+ // to register interface (read)
+ .qs (clk_enables_clk_io_peri_en_qs)
+ );
+
// R[clk_hints]: V(False)
// F[clk_main_aes_hint]: 0:0
@@ -1704,9 +1704,9 @@
assign clk_enables_clk_io_div2_peri_en_wd = reg_wdata[1];
- assign clk_enables_clk_io_peri_en_wd = reg_wdata[2];
+ assign clk_enables_clk_usb_peri_en_wd = reg_wdata[2];
- assign clk_enables_clk_usb_peri_en_wd = reg_wdata[3];
+ assign clk_enables_clk_io_peri_en_wd = reg_wdata[3];
assign clk_hints_we = addr_hit[5] & reg_we & !reg_error;
assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0];
@@ -1788,8 +1788,8 @@
addr_hit[4]: begin
reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs;
reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs;
- reg_rdata_next[2] = clk_enables_clk_io_peri_en_qs;
- reg_rdata_next[3] = clk_enables_clk_usb_peri_en_qs;
+ reg_rdata_next[2] = clk_enables_clk_usb_peri_en_qs;
+ reg_rdata_next[3] = clk_enables_clk_io_peri_en_qs;
end
addr_hit[5]: begin
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index 87dd48e..bac9093 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -12,6 +12,8 @@
{
clk_main_i: main
clk_fixed_i: io_div4
+ clk_spi_host0_i: io
+ clk_spi_host1_i: io_div2
}
clock_group: infra
reset: rst_main_ni
@@ -27,11 +29,23 @@
name: sys_io_div4
domain: "0"
}
+ rst_spi_host0_ni:
+ {
+ name: spi_host0
+ domain: "0"
+ }
+ rst_spi_host1_ni:
+ {
+ name: spi_host1
+ domain: "0"
+ }
}
clock_connections:
{
clk_main_i: clkmgr_aon_clocks.clk_main_infra
clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
+ clk_spi_host0_i: clkmgr_aon_clocks.clk_io_infra
+ clk_spi_host1_i: clkmgr_aon_clocks.clk_io_div2_infra
}
domain:
[
@@ -54,6 +68,8 @@
rv_dm.regs
sram_ctrl_main.ram
peri
+ spi_host0
+ spi_host1
flash_ctrl.core
flash_ctrl.prim
flash_ctrl.mem
@@ -214,11 +230,51 @@
[
{
base_addr: 0x40000000
- size_byte: 0x800000
+ size_byte: 0x200000
+ }
+ {
+ base_addr: 0x40400000
+ size_byte: 0x400000
}
]
}
{
+ name: spi_host0
+ type: device
+ clock: clk_spi_host0_i
+ reset: rst_spi_host0_ni
+ pipeline: "false"
+ inst_type: spi_host
+ addr_range:
+ [
+ {
+ base_addr: 0x40300000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: spi_host1
+ type: device
+ clock: clk_spi_host1_i
+ reset: rst_spi_host1_ni
+ pipeline: "false"
+ inst_type: spi_host
+ addr_range:
+ [
+ {
+ base_addr: 0x40310000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
name: flash_ctrl.core
type: device
clock: clk_main_i
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
index 29c7565..c89a951 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
@@ -63,6 +63,18 @@
}
{ struct: "tl"
type: "req_rsp"
+ name: "tl_spi_host0"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_spi_host1"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
name: "tl_flash_ctrl__core"
act: "req"
package: "tlul_pkg"
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
index 8d3c162..4db923a 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
@@ -8,13 +8,19 @@
`DRIVE_CLK(clk_main_i)
`DRIVE_CLK(clk_fixed_i)
+`DRIVE_CLK(clk_spi_host0_i)
+`DRIVE_CLK(clk_spi_host1_i)
initial force dut.clk_main_i = clk_main_i;
initial force dut.clk_fixed_i = clk_fixed_i;
+initial force dut.clk_spi_host0_i = clk_spi_host0_i;
+initial force dut.clk_spi_host1_i = clk_spi_host1_i;
// TODO, all resets tie together
initial force dut.rst_main_ni = rst_n;
initial force dut.rst_fixed_ni = rst_n;
+initial force dut.rst_spi_host0_ni = rst_n;
+initial force dut.rst_spi_host1_ni = rst_n;
// Host TileLink interface connections
`CONNECT_TL_HOST_IF(rv_core_ibex__corei, dut, clk_main_i, rst_n)
@@ -27,6 +33,8 @@
`CONNECT_TL_DEVICE_IF(rom_ctrl__rom, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(rom_ctrl__regs, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(peri, dut, clk_fixed_i, rst_n)
+`CONNECT_TL_DEVICE_IF(spi_host0, dut, clk_spi_host0_i, rst_n)
+`CONNECT_TL_DEVICE_IF(spi_host1, dut, clk_spi_host1_i, rst_n)
`CONNECT_TL_DEVICE_IF(flash_ctrl__core, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(flash_ctrl__prim, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(flash_ctrl__mem, dut, clk_main_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
index 7865fa3..2f68335 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
@@ -27,6 +27,13 @@
-node tb.dut tl_rom_ctrl__regs_o.a_address[31:31]
-node tb.dut tl_peri_o.a_address[29:23]
-node tb.dut tl_peri_o.a_address[31:31]
+-node tb.dut tl_spi_host0_o.a_address[19:12]
+-node tb.dut tl_spi_host0_o.a_address[29:22]
+-node tb.dut tl_spi_host0_o.a_address[31:31]
+-node tb.dut tl_spi_host1_o.a_address[15:12]
+-node tb.dut tl_spi_host1_o.a_address[19:17]
+-node tb.dut tl_spi_host1_o.a_address[29:22]
+-node tb.dut tl_spi_host1_o.a_address[31:31]
-node tb.dut tl_flash_ctrl__core_o.a_address[23:12]
-node tb.dut tl_flash_ctrl__core_o.a_address[29:25]
-node tb.dut tl_flash_ctrl__core_o.a_address[31:31]
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
index 91d8311..1fccc45 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -20,7 +20,14 @@
'{32'h411e0000, 32'h411e0fff}
}},
'{"peri", '{
- '{32'h40000000, 32'h407fffff}
+ '{32'h40000000, 32'h401fffff},
+ '{32'h40400000, 32'h407fffff}
+ }},
+ '{"spi_host0", '{
+ '{32'h40300000, 32'h40300fff}
+ }},
+ '{"spi_host1", '{
+ '{32'h40310000, 32'h40310fff}
}},
'{"flash_ctrl__core", '{
'{32'h41000000, 32'h41000fff}
@@ -86,6 +93,8 @@
"rv_dm__regs",
"sram_ctrl_main__ram",
"peri",
+ "spi_host0",
+ "spi_host1",
"flash_ctrl__core",
"flash_ctrl__prim",
"flash_ctrl__mem",
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
index d1d814e..fa5f6e8 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
@@ -56,6 +56,18 @@
.h2d (tl_peri_o),
.d2h (tl_peri_i)
);
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host0 (
+ .clk_i (clk_spi_host0_i),
+ .rst_ni (rst_spi_host0_ni),
+ .h2d (tl_spi_host0_o),
+ .d2h (tl_spi_host0_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host1 (
+ .clk_i (clk_spi_host1_i),
+ .rst_ni (rst_spi_host1_ni),
+ .h2d (tl_spi_host1_o),
+ .d2h (tl_spi_host1_i)
+ );
bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__core (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
index fd69797..396b902 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -10,9 +10,12 @@
localparam logic [31:0] ADDR_SPACE_RV_DM__ROM = 32'h 00010000;
localparam logic [31:0] ADDR_SPACE_ROM_CTRL__ROM = 32'h 00008000;
localparam logic [31:0] ADDR_SPACE_ROM_CTRL__REGS = 32'h 411e0000;
- localparam logic [0:0][31:0] ADDR_SPACE_PERI = {
+ localparam logic [1:0][31:0] ADDR_SPACE_PERI = {
+ 32'h 40400000,
32'h 40000000
};
+ localparam logic [31:0] ADDR_SPACE_SPI_HOST0 = 32'h 40300000;
+ localparam logic [31:0] ADDR_SPACE_SPI_HOST1 = 32'h 40310000;
localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__CORE = 32'h 41000000;
localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__PRIM = 32'h 41008000;
localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__MEM = 32'h 20000000;
@@ -34,9 +37,12 @@
localparam logic [31:0] ADDR_MASK_RV_DM__ROM = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_ROM_CTRL__ROM = 32'h 00007fff;
localparam logic [31:0] ADDR_MASK_ROM_CTRL__REGS = 32'h 00000fff;
- localparam logic [0:0][31:0] ADDR_MASK_PERI = {
- 32'h 007fffff
+ localparam logic [1:0][31:0] ADDR_MASK_PERI = {
+ 32'h 003fffff,
+ 32'h 001fffff
};
+ localparam logic [31:0] ADDR_MASK_SPI_HOST0 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_SPI_HOST1 = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_FLASH_CTRL__CORE = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_FLASH_CTRL__PRIM = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_FLASH_CTRL__MEM = 32'h 000fffff;
@@ -55,7 +61,7 @@
localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__RAM = 32'h 0001ffff;
localparam int N_HOST = 3;
- localparam int N_DEVICE = 21;
+ localparam int N_DEVICE = 23;
typedef enum int {
TlRvDmRegs = 0,
@@ -63,22 +69,24 @@
TlRomCtrlRom = 2,
TlRomCtrlRegs = 3,
TlPeri = 4,
- TlFlashCtrlCore = 5,
- TlFlashCtrlPrim = 6,
- TlFlashCtrlMem = 7,
- TlHmac = 8,
- TlKmac = 9,
- TlAes = 10,
- TlEntropySrc = 11,
- TlCsrng = 12,
- TlEdn0 = 13,
- TlEdn1 = 14,
- TlRvPlic = 15,
- TlOtbn = 16,
- TlKeymgr = 17,
- TlRvCoreIbexCfg = 18,
- TlSramCtrlMainRegs = 19,
- TlSramCtrlMainRam = 20
+ TlSpiHost0 = 5,
+ TlSpiHost1 = 6,
+ TlFlashCtrlCore = 7,
+ TlFlashCtrlPrim = 8,
+ TlFlashCtrlMem = 9,
+ TlHmac = 10,
+ TlKmac = 11,
+ TlAes = 12,
+ TlEntropySrc = 13,
+ TlCsrng = 14,
+ TlEdn0 = 15,
+ TlEdn1 = 16,
+ TlRvPlic = 17,
+ TlOtbn = 18,
+ TlKeymgr = 19,
+ TlRvCoreIbexCfg = 20,
+ TlSramCtrlMainRegs = 21,
+ TlSramCtrlMainRam = 22
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
index 52e37e4..98e590d 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -7,109 +7,117 @@
//
// Interconnect
// rv_core_ibex.corei
-// -> s1n_24
-// -> sm1_25
-// -> rom_ctrl.rom
-// -> sm1_26
-// -> rv_dm.rom
+// -> s1n_26
// -> sm1_27
-// -> sram_ctrl_main.ram
+// -> rom_ctrl.rom
// -> sm1_28
+// -> rv_dm.rom
+// -> sm1_29
+// -> sram_ctrl_main.ram
+// -> sm1_30
// -> flash_ctrl.mem
// rv_core_ibex.cored
-// -> s1n_29
-// -> sm1_25
-// -> rom_ctrl.rom
-// -> sm1_30
-// -> rom_ctrl.regs
-// -> sm1_26
-// -> rv_dm.rom
-// -> sm1_31
-// -> rv_dm.regs
+// -> s1n_31
// -> sm1_27
-// -> sram_ctrl_main.ram
-// -> sm1_33
-// -> asf_32
-// -> peri
-// -> sm1_34
-// -> flash_ctrl.core
-// -> sm1_35
-// -> flash_ctrl.prim
+// -> rom_ctrl.rom
+// -> sm1_32
+// -> rom_ctrl.regs
// -> sm1_28
-// -> flash_ctrl.mem
-// -> sm1_36
-// -> aes
-// -> sm1_37
-// -> entropy_src
+// -> rv_dm.rom
+// -> sm1_33
+// -> rv_dm.regs
+// -> sm1_29
+// -> sram_ctrl_main.ram
+// -> sm1_35
+// -> asf_34
+// -> peri
+// -> asf_36
+// -> spi_host0
+// -> asf_37
+// -> spi_host1
// -> sm1_38
-// -> csrng
+// -> flash_ctrl.core
// -> sm1_39
-// -> edn0
+// -> flash_ctrl.prim
+// -> sm1_30
+// -> flash_ctrl.mem
// -> sm1_40
-// -> edn1
+// -> aes
// -> sm1_41
-// -> hmac
+// -> entropy_src
// -> sm1_42
-// -> rv_plic
+// -> csrng
// -> sm1_43
-// -> otbn
+// -> edn0
// -> sm1_44
-// -> keymgr
+// -> edn1
// -> sm1_45
-// -> kmac
+// -> hmac
// -> sm1_46
-// -> sram_ctrl_main.regs
+// -> rv_plic
// -> sm1_47
+// -> otbn
+// -> sm1_48
+// -> keymgr
+// -> sm1_49
+// -> kmac
+// -> sm1_50
+// -> sram_ctrl_main.regs
+// -> sm1_51
// -> rv_core_ibex.cfg
// rv_dm.sba
-// -> s1n_48
-// -> sm1_25
-// -> rom_ctrl.rom
-// -> sm1_30
-// -> rom_ctrl.regs
-// -> sm1_31
-// -> rv_dm.regs
+// -> s1n_52
// -> sm1_27
-// -> sram_ctrl_main.ram
+// -> rom_ctrl.rom
+// -> sm1_32
+// -> rom_ctrl.regs
// -> sm1_33
-// -> asf_32
-// -> peri
-// -> sm1_34
-// -> flash_ctrl.core
+// -> rv_dm.regs
+// -> sm1_29
+// -> sram_ctrl_main.ram
// -> sm1_35
-// -> flash_ctrl.prim
-// -> sm1_28
-// -> flash_ctrl.mem
-// -> sm1_36
-// -> aes
-// -> sm1_37
-// -> entropy_src
+// -> asf_34
+// -> peri
// -> sm1_38
-// -> csrng
+// -> flash_ctrl.core
// -> sm1_39
-// -> edn0
+// -> flash_ctrl.prim
+// -> sm1_30
+// -> flash_ctrl.mem
// -> sm1_40
-// -> edn1
+// -> aes
// -> sm1_41
-// -> hmac
+// -> entropy_src
// -> sm1_42
-// -> rv_plic
+// -> csrng
// -> sm1_43
-// -> otbn
+// -> edn0
// -> sm1_44
-// -> keymgr
+// -> edn1
// -> sm1_45
-// -> kmac
+// -> hmac
// -> sm1_46
-// -> sram_ctrl_main.regs
+// -> rv_plic
// -> sm1_47
+// -> otbn
+// -> sm1_48
+// -> keymgr
+// -> sm1_49
+// -> kmac
+// -> sm1_50
+// -> sram_ctrl_main.regs
+// -> sm1_51
// -> rv_core_ibex.cfg
module xbar_main (
input clk_main_i,
input clk_fixed_i,
+ input clk_spi_host0_i,
+ input clk_spi_host1_i,
input rst_main_ni,
input rst_fixed_ni,
+ input rst_spi_host0_ni,
+ input rst_spi_host1_ni,
// Host interfaces
input tlul_pkg::tl_h2d_t tl_rv_core_ibex__corei_i,
@@ -130,6 +138,10 @@
input tlul_pkg::tl_d2h_t tl_rom_ctrl__regs_i,
output tlul_pkg::tl_h2d_t tl_peri_o,
input tlul_pkg::tl_d2h_t tl_peri_i,
+ output tlul_pkg::tl_h2d_t tl_spi_host0_o,
+ input tlul_pkg::tl_d2h_t tl_spi_host0_i,
+ output tlul_pkg::tl_h2d_t tl_spi_host1_o,
+ input tlul_pkg::tl_d2h_t tl_spi_host1_i,
output tlul_pkg::tl_h2d_t tl_flash_ctrl__core_o,
input tlul_pkg::tl_d2h_t tl_flash_ctrl__core_i,
output tlul_pkg::tl_h2d_t tl_flash_ctrl__prim_o,
@@ -174,29 +186,15 @@
logic unused_scanmode;
assign unused_scanmode = ^scanmode_i;
- tl_h2d_t tl_s1n_24_us_h2d ;
- tl_d2h_t tl_s1n_24_us_d2h ;
+ tl_h2d_t tl_s1n_26_us_h2d ;
+ tl_d2h_t tl_s1n_26_us_d2h ;
- tl_h2d_t tl_s1n_24_ds_h2d [4];
- tl_d2h_t tl_s1n_24_ds_d2h [4];
+ tl_h2d_t tl_s1n_26_ds_h2d [4];
+ tl_d2h_t tl_s1n_26_ds_d2h [4];
// Create steering signal
- logic [2:0] dev_sel_s1n_24;
-
-
- tl_h2d_t tl_sm1_25_us_h2d [3];
- tl_d2h_t tl_sm1_25_us_d2h [3];
-
- tl_h2d_t tl_sm1_25_ds_h2d ;
- tl_d2h_t tl_sm1_25_ds_d2h ;
-
-
- tl_h2d_t tl_sm1_26_us_h2d [2];
- tl_d2h_t tl_sm1_26_us_d2h [2];
-
- tl_h2d_t tl_sm1_26_ds_h2d ;
- tl_d2h_t tl_sm1_26_ds_d2h ;
+ logic [2:0] dev_sel_s1n_26;
tl_h2d_t tl_sm1_27_us_h2d [3];
@@ -206,40 +204,42 @@
tl_d2h_t tl_sm1_27_ds_d2h ;
- tl_h2d_t tl_sm1_28_us_h2d [3];
- tl_d2h_t tl_sm1_28_us_d2h [3];
+ tl_h2d_t tl_sm1_28_us_h2d [2];
+ tl_d2h_t tl_sm1_28_us_d2h [2];
tl_h2d_t tl_sm1_28_ds_h2d ;
tl_d2h_t tl_sm1_28_ds_d2h ;
- tl_h2d_t tl_s1n_29_us_h2d ;
- tl_d2h_t tl_s1n_29_us_d2h ;
+
+ tl_h2d_t tl_sm1_29_us_h2d [3];
+ tl_d2h_t tl_sm1_29_us_d2h [3];
+
+ tl_h2d_t tl_sm1_29_ds_h2d ;
+ tl_d2h_t tl_sm1_29_ds_d2h ;
- tl_h2d_t tl_s1n_29_ds_h2d [21];
- tl_d2h_t tl_s1n_29_ds_d2h [21];
-
- // Create steering signal
- logic [4:0] dev_sel_s1n_29;
-
-
- tl_h2d_t tl_sm1_30_us_h2d [2];
- tl_d2h_t tl_sm1_30_us_d2h [2];
+ tl_h2d_t tl_sm1_30_us_h2d [3];
+ tl_d2h_t tl_sm1_30_us_d2h [3];
tl_h2d_t tl_sm1_30_ds_h2d ;
tl_d2h_t tl_sm1_30_ds_d2h ;
+ tl_h2d_t tl_s1n_31_us_h2d ;
+ tl_d2h_t tl_s1n_31_us_d2h ;
- tl_h2d_t tl_sm1_31_us_h2d [2];
- tl_d2h_t tl_sm1_31_us_d2h [2];
- tl_h2d_t tl_sm1_31_ds_h2d ;
- tl_d2h_t tl_sm1_31_ds_d2h ;
+ tl_h2d_t tl_s1n_31_ds_h2d [23];
+ tl_d2h_t tl_s1n_31_ds_d2h [23];
- tl_h2d_t tl_asf_32_us_h2d ;
- tl_d2h_t tl_asf_32_us_d2h ;
- tl_h2d_t tl_asf_32_ds_h2d ;
- tl_d2h_t tl_asf_32_ds_d2h ;
+ // Create steering signal
+ logic [4:0] dev_sel_s1n_31;
+
+
+ tl_h2d_t tl_sm1_32_us_h2d [2];
+ tl_d2h_t tl_sm1_32_us_d2h [2];
+
+ tl_h2d_t tl_sm1_32_ds_h2d ;
+ tl_d2h_t tl_sm1_32_ds_d2h ;
tl_h2d_t tl_sm1_33_us_h2d [2];
@@ -248,12 +248,10 @@
tl_h2d_t tl_sm1_33_ds_h2d ;
tl_d2h_t tl_sm1_33_ds_d2h ;
-
- tl_h2d_t tl_sm1_34_us_h2d [2];
- tl_d2h_t tl_sm1_34_us_d2h [2];
-
- tl_h2d_t tl_sm1_34_ds_h2d ;
- tl_d2h_t tl_sm1_34_ds_d2h ;
+ tl_h2d_t tl_asf_34_us_h2d ;
+ tl_d2h_t tl_asf_34_us_d2h ;
+ tl_h2d_t tl_asf_34_ds_h2d ;
+ tl_d2h_t tl_asf_34_ds_d2h ;
tl_h2d_t tl_sm1_35_us_h2d [2];
@@ -262,19 +260,15 @@
tl_h2d_t tl_sm1_35_ds_h2d ;
tl_d2h_t tl_sm1_35_ds_d2h ;
+ tl_h2d_t tl_asf_36_us_h2d ;
+ tl_d2h_t tl_asf_36_us_d2h ;
+ tl_h2d_t tl_asf_36_ds_h2d ;
+ tl_d2h_t tl_asf_36_ds_d2h ;
- tl_h2d_t tl_sm1_36_us_h2d [2];
- tl_d2h_t tl_sm1_36_us_d2h [2];
-
- tl_h2d_t tl_sm1_36_ds_h2d ;
- tl_d2h_t tl_sm1_36_ds_d2h ;
-
-
- tl_h2d_t tl_sm1_37_us_h2d [2];
- tl_d2h_t tl_sm1_37_us_d2h [2];
-
- tl_h2d_t tl_sm1_37_ds_h2d ;
- tl_d2h_t tl_sm1_37_ds_d2h ;
+ tl_h2d_t tl_asf_37_us_h2d ;
+ tl_d2h_t tl_asf_37_us_d2h ;
+ tl_h2d_t tl_asf_37_ds_h2d ;
+ tl_d2h_t tl_asf_37_ds_d2h ;
tl_h2d_t tl_sm1_38_us_h2d [2];
@@ -346,420 +340,472 @@
tl_h2d_t tl_sm1_47_ds_h2d ;
tl_d2h_t tl_sm1_47_ds_d2h ;
- tl_h2d_t tl_s1n_48_us_h2d ;
- tl_d2h_t tl_s1n_48_us_d2h ;
+
+ tl_h2d_t tl_sm1_48_us_h2d [2];
+ tl_d2h_t tl_sm1_48_us_d2h [2];
+
+ tl_h2d_t tl_sm1_48_ds_h2d ;
+ tl_d2h_t tl_sm1_48_ds_d2h ;
- tl_h2d_t tl_s1n_48_ds_h2d [20];
- tl_d2h_t tl_s1n_48_ds_d2h [20];
+ tl_h2d_t tl_sm1_49_us_h2d [2];
+ tl_d2h_t tl_sm1_49_us_d2h [2];
+
+ tl_h2d_t tl_sm1_49_ds_h2d ;
+ tl_d2h_t tl_sm1_49_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_50_us_h2d [2];
+ tl_d2h_t tl_sm1_50_us_d2h [2];
+
+ tl_h2d_t tl_sm1_50_ds_h2d ;
+ tl_d2h_t tl_sm1_50_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_51_us_h2d [2];
+ tl_d2h_t tl_sm1_51_us_d2h [2];
+
+ tl_h2d_t tl_sm1_51_ds_h2d ;
+ tl_d2h_t tl_sm1_51_ds_d2h ;
+
+ tl_h2d_t tl_s1n_52_us_h2d ;
+ tl_d2h_t tl_s1n_52_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_52_ds_h2d [20];
+ tl_d2h_t tl_s1n_52_ds_d2h [20];
// Create steering signal
- logic [4:0] dev_sel_s1n_48;
+ logic [4:0] dev_sel_s1n_52;
- assign tl_sm1_25_us_h2d[0] = tl_s1n_24_ds_h2d[0];
- assign tl_s1n_24_ds_d2h[0] = tl_sm1_25_us_d2h[0];
+ assign tl_sm1_27_us_h2d[0] = tl_s1n_26_ds_h2d[0];
+ assign tl_s1n_26_ds_d2h[0] = tl_sm1_27_us_d2h[0];
- assign tl_sm1_26_us_h2d[0] = tl_s1n_24_ds_h2d[1];
- assign tl_s1n_24_ds_d2h[1] = tl_sm1_26_us_d2h[0];
+ assign tl_sm1_28_us_h2d[0] = tl_s1n_26_ds_h2d[1];
+ assign tl_s1n_26_ds_d2h[1] = tl_sm1_28_us_d2h[0];
- assign tl_sm1_27_us_h2d[0] = tl_s1n_24_ds_h2d[2];
- assign tl_s1n_24_ds_d2h[2] = tl_sm1_27_us_d2h[0];
+ assign tl_sm1_29_us_h2d[0] = tl_s1n_26_ds_h2d[2];
+ assign tl_s1n_26_ds_d2h[2] = tl_sm1_29_us_d2h[0];
- assign tl_sm1_28_us_h2d[0] = tl_s1n_24_ds_h2d[3];
- assign tl_s1n_24_ds_d2h[3] = tl_sm1_28_us_d2h[0];
+ assign tl_sm1_30_us_h2d[0] = tl_s1n_26_ds_h2d[3];
+ assign tl_s1n_26_ds_d2h[3] = tl_sm1_30_us_d2h[0];
- assign tl_sm1_25_us_h2d[1] = tl_s1n_29_ds_h2d[0];
- assign tl_s1n_29_ds_d2h[0] = tl_sm1_25_us_d2h[1];
+ assign tl_sm1_27_us_h2d[1] = tl_s1n_31_ds_h2d[0];
+ assign tl_s1n_31_ds_d2h[0] = tl_sm1_27_us_d2h[1];
- assign tl_sm1_30_us_h2d[0] = tl_s1n_29_ds_h2d[1];
- assign tl_s1n_29_ds_d2h[1] = tl_sm1_30_us_d2h[0];
+ assign tl_sm1_32_us_h2d[0] = tl_s1n_31_ds_h2d[1];
+ assign tl_s1n_31_ds_d2h[1] = tl_sm1_32_us_d2h[0];
- assign tl_sm1_26_us_h2d[1] = tl_s1n_29_ds_h2d[2];
- assign tl_s1n_29_ds_d2h[2] = tl_sm1_26_us_d2h[1];
+ assign tl_sm1_28_us_h2d[1] = tl_s1n_31_ds_h2d[2];
+ assign tl_s1n_31_ds_d2h[2] = tl_sm1_28_us_d2h[1];
- assign tl_sm1_31_us_h2d[0] = tl_s1n_29_ds_h2d[3];
- assign tl_s1n_29_ds_d2h[3] = tl_sm1_31_us_d2h[0];
+ assign tl_sm1_33_us_h2d[0] = tl_s1n_31_ds_h2d[3];
+ assign tl_s1n_31_ds_d2h[3] = tl_sm1_33_us_d2h[0];
- assign tl_sm1_27_us_h2d[1] = tl_s1n_29_ds_h2d[4];
- assign tl_s1n_29_ds_d2h[4] = tl_sm1_27_us_d2h[1];
+ assign tl_sm1_29_us_h2d[1] = tl_s1n_31_ds_h2d[4];
+ assign tl_s1n_31_ds_d2h[4] = tl_sm1_29_us_d2h[1];
- assign tl_sm1_33_us_h2d[0] = tl_s1n_29_ds_h2d[5];
- assign tl_s1n_29_ds_d2h[5] = tl_sm1_33_us_d2h[0];
+ assign tl_sm1_35_us_h2d[0] = tl_s1n_31_ds_h2d[5];
+ assign tl_s1n_31_ds_d2h[5] = tl_sm1_35_us_d2h[0];
- assign tl_sm1_34_us_h2d[0] = tl_s1n_29_ds_h2d[6];
- assign tl_s1n_29_ds_d2h[6] = tl_sm1_34_us_d2h[0];
+ assign tl_asf_36_us_h2d = tl_s1n_31_ds_h2d[6];
+ assign tl_s1n_31_ds_d2h[6] = tl_asf_36_us_d2h;
- assign tl_sm1_35_us_h2d[0] = tl_s1n_29_ds_h2d[7];
- assign tl_s1n_29_ds_d2h[7] = tl_sm1_35_us_d2h[0];
+ assign tl_asf_37_us_h2d = tl_s1n_31_ds_h2d[7];
+ assign tl_s1n_31_ds_d2h[7] = tl_asf_37_us_d2h;
- assign tl_sm1_28_us_h2d[1] = tl_s1n_29_ds_h2d[8];
- assign tl_s1n_29_ds_d2h[8] = tl_sm1_28_us_d2h[1];
+ assign tl_sm1_38_us_h2d[0] = tl_s1n_31_ds_h2d[8];
+ assign tl_s1n_31_ds_d2h[8] = tl_sm1_38_us_d2h[0];
- assign tl_sm1_36_us_h2d[0] = tl_s1n_29_ds_h2d[9];
- assign tl_s1n_29_ds_d2h[9] = tl_sm1_36_us_d2h[0];
+ assign tl_sm1_39_us_h2d[0] = tl_s1n_31_ds_h2d[9];
+ assign tl_s1n_31_ds_d2h[9] = tl_sm1_39_us_d2h[0];
- assign tl_sm1_37_us_h2d[0] = tl_s1n_29_ds_h2d[10];
- assign tl_s1n_29_ds_d2h[10] = tl_sm1_37_us_d2h[0];
+ assign tl_sm1_30_us_h2d[1] = tl_s1n_31_ds_h2d[10];
+ assign tl_s1n_31_ds_d2h[10] = tl_sm1_30_us_d2h[1];
- assign tl_sm1_38_us_h2d[0] = tl_s1n_29_ds_h2d[11];
- assign tl_s1n_29_ds_d2h[11] = tl_sm1_38_us_d2h[0];
+ assign tl_sm1_40_us_h2d[0] = tl_s1n_31_ds_h2d[11];
+ assign tl_s1n_31_ds_d2h[11] = tl_sm1_40_us_d2h[0];
- assign tl_sm1_39_us_h2d[0] = tl_s1n_29_ds_h2d[12];
- assign tl_s1n_29_ds_d2h[12] = tl_sm1_39_us_d2h[0];
+ assign tl_sm1_41_us_h2d[0] = tl_s1n_31_ds_h2d[12];
+ assign tl_s1n_31_ds_d2h[12] = tl_sm1_41_us_d2h[0];
- assign tl_sm1_40_us_h2d[0] = tl_s1n_29_ds_h2d[13];
- assign tl_s1n_29_ds_d2h[13] = tl_sm1_40_us_d2h[0];
+ assign tl_sm1_42_us_h2d[0] = tl_s1n_31_ds_h2d[13];
+ assign tl_s1n_31_ds_d2h[13] = tl_sm1_42_us_d2h[0];
- assign tl_sm1_41_us_h2d[0] = tl_s1n_29_ds_h2d[14];
- assign tl_s1n_29_ds_d2h[14] = tl_sm1_41_us_d2h[0];
+ assign tl_sm1_43_us_h2d[0] = tl_s1n_31_ds_h2d[14];
+ assign tl_s1n_31_ds_d2h[14] = tl_sm1_43_us_d2h[0];
- assign tl_sm1_42_us_h2d[0] = tl_s1n_29_ds_h2d[15];
- assign tl_s1n_29_ds_d2h[15] = tl_sm1_42_us_d2h[0];
+ assign tl_sm1_44_us_h2d[0] = tl_s1n_31_ds_h2d[15];
+ assign tl_s1n_31_ds_d2h[15] = tl_sm1_44_us_d2h[0];
- assign tl_sm1_43_us_h2d[0] = tl_s1n_29_ds_h2d[16];
- assign tl_s1n_29_ds_d2h[16] = tl_sm1_43_us_d2h[0];
+ assign tl_sm1_45_us_h2d[0] = tl_s1n_31_ds_h2d[16];
+ assign tl_s1n_31_ds_d2h[16] = tl_sm1_45_us_d2h[0];
- assign tl_sm1_44_us_h2d[0] = tl_s1n_29_ds_h2d[17];
- assign tl_s1n_29_ds_d2h[17] = tl_sm1_44_us_d2h[0];
+ assign tl_sm1_46_us_h2d[0] = tl_s1n_31_ds_h2d[17];
+ assign tl_s1n_31_ds_d2h[17] = tl_sm1_46_us_d2h[0];
- assign tl_sm1_45_us_h2d[0] = tl_s1n_29_ds_h2d[18];
- assign tl_s1n_29_ds_d2h[18] = tl_sm1_45_us_d2h[0];
+ assign tl_sm1_47_us_h2d[0] = tl_s1n_31_ds_h2d[18];
+ assign tl_s1n_31_ds_d2h[18] = tl_sm1_47_us_d2h[0];
- assign tl_sm1_46_us_h2d[0] = tl_s1n_29_ds_h2d[19];
- assign tl_s1n_29_ds_d2h[19] = tl_sm1_46_us_d2h[0];
+ assign tl_sm1_48_us_h2d[0] = tl_s1n_31_ds_h2d[19];
+ assign tl_s1n_31_ds_d2h[19] = tl_sm1_48_us_d2h[0];
- assign tl_sm1_47_us_h2d[0] = tl_s1n_29_ds_h2d[20];
- assign tl_s1n_29_ds_d2h[20] = tl_sm1_47_us_d2h[0];
+ assign tl_sm1_49_us_h2d[0] = tl_s1n_31_ds_h2d[20];
+ assign tl_s1n_31_ds_d2h[20] = tl_sm1_49_us_d2h[0];
- assign tl_sm1_25_us_h2d[2] = tl_s1n_48_ds_h2d[0];
- assign tl_s1n_48_ds_d2h[0] = tl_sm1_25_us_d2h[2];
+ assign tl_sm1_50_us_h2d[0] = tl_s1n_31_ds_h2d[21];
+ assign tl_s1n_31_ds_d2h[21] = tl_sm1_50_us_d2h[0];
- assign tl_sm1_30_us_h2d[1] = tl_s1n_48_ds_h2d[1];
- assign tl_s1n_48_ds_d2h[1] = tl_sm1_30_us_d2h[1];
+ assign tl_sm1_51_us_h2d[0] = tl_s1n_31_ds_h2d[22];
+ assign tl_s1n_31_ds_d2h[22] = tl_sm1_51_us_d2h[0];
- assign tl_sm1_31_us_h2d[1] = tl_s1n_48_ds_h2d[2];
- assign tl_s1n_48_ds_d2h[2] = tl_sm1_31_us_d2h[1];
+ assign tl_sm1_27_us_h2d[2] = tl_s1n_52_ds_h2d[0];
+ assign tl_s1n_52_ds_d2h[0] = tl_sm1_27_us_d2h[2];
- assign tl_sm1_27_us_h2d[2] = tl_s1n_48_ds_h2d[3];
- assign tl_s1n_48_ds_d2h[3] = tl_sm1_27_us_d2h[2];
+ assign tl_sm1_32_us_h2d[1] = tl_s1n_52_ds_h2d[1];
+ assign tl_s1n_52_ds_d2h[1] = tl_sm1_32_us_d2h[1];
- assign tl_sm1_33_us_h2d[1] = tl_s1n_48_ds_h2d[4];
- assign tl_s1n_48_ds_d2h[4] = tl_sm1_33_us_d2h[1];
+ assign tl_sm1_33_us_h2d[1] = tl_s1n_52_ds_h2d[2];
+ assign tl_s1n_52_ds_d2h[2] = tl_sm1_33_us_d2h[1];
- assign tl_sm1_34_us_h2d[1] = tl_s1n_48_ds_h2d[5];
- assign tl_s1n_48_ds_d2h[5] = tl_sm1_34_us_d2h[1];
+ assign tl_sm1_29_us_h2d[2] = tl_s1n_52_ds_h2d[3];
+ assign tl_s1n_52_ds_d2h[3] = tl_sm1_29_us_d2h[2];
- assign tl_sm1_35_us_h2d[1] = tl_s1n_48_ds_h2d[6];
- assign tl_s1n_48_ds_d2h[6] = tl_sm1_35_us_d2h[1];
+ assign tl_sm1_35_us_h2d[1] = tl_s1n_52_ds_h2d[4];
+ assign tl_s1n_52_ds_d2h[4] = tl_sm1_35_us_d2h[1];
- assign tl_sm1_28_us_h2d[2] = tl_s1n_48_ds_h2d[7];
- assign tl_s1n_48_ds_d2h[7] = tl_sm1_28_us_d2h[2];
+ assign tl_sm1_38_us_h2d[1] = tl_s1n_52_ds_h2d[5];
+ assign tl_s1n_52_ds_d2h[5] = tl_sm1_38_us_d2h[1];
- assign tl_sm1_36_us_h2d[1] = tl_s1n_48_ds_h2d[8];
- assign tl_s1n_48_ds_d2h[8] = tl_sm1_36_us_d2h[1];
+ assign tl_sm1_39_us_h2d[1] = tl_s1n_52_ds_h2d[6];
+ assign tl_s1n_52_ds_d2h[6] = tl_sm1_39_us_d2h[1];
+
+ assign tl_sm1_30_us_h2d[2] = tl_s1n_52_ds_h2d[7];
+ assign tl_s1n_52_ds_d2h[7] = tl_sm1_30_us_d2h[2];
+
+ assign tl_sm1_40_us_h2d[1] = tl_s1n_52_ds_h2d[8];
+ assign tl_s1n_52_ds_d2h[8] = tl_sm1_40_us_d2h[1];
+
+ assign tl_sm1_41_us_h2d[1] = tl_s1n_52_ds_h2d[9];
+ assign tl_s1n_52_ds_d2h[9] = tl_sm1_41_us_d2h[1];
+
+ assign tl_sm1_42_us_h2d[1] = tl_s1n_52_ds_h2d[10];
+ assign tl_s1n_52_ds_d2h[10] = tl_sm1_42_us_d2h[1];
- assign tl_sm1_37_us_h2d[1] = tl_s1n_48_ds_h2d[9];
- assign tl_s1n_48_ds_d2h[9] = tl_sm1_37_us_d2h[1];
+ assign tl_sm1_43_us_h2d[1] = tl_s1n_52_ds_h2d[11];
+ assign tl_s1n_52_ds_d2h[11] = tl_sm1_43_us_d2h[1];
- assign tl_sm1_38_us_h2d[1] = tl_s1n_48_ds_h2d[10];
- assign tl_s1n_48_ds_d2h[10] = tl_sm1_38_us_d2h[1];
+ assign tl_sm1_44_us_h2d[1] = tl_s1n_52_ds_h2d[12];
+ assign tl_s1n_52_ds_d2h[12] = tl_sm1_44_us_d2h[1];
- assign tl_sm1_39_us_h2d[1] = tl_s1n_48_ds_h2d[11];
- assign tl_s1n_48_ds_d2h[11] = tl_sm1_39_us_d2h[1];
+ assign tl_sm1_45_us_h2d[1] = tl_s1n_52_ds_h2d[13];
+ assign tl_s1n_52_ds_d2h[13] = tl_sm1_45_us_d2h[1];
- assign tl_sm1_40_us_h2d[1] = tl_s1n_48_ds_h2d[12];
- assign tl_s1n_48_ds_d2h[12] = tl_sm1_40_us_d2h[1];
+ assign tl_sm1_46_us_h2d[1] = tl_s1n_52_ds_h2d[14];
+ assign tl_s1n_52_ds_d2h[14] = tl_sm1_46_us_d2h[1];
- assign tl_sm1_41_us_h2d[1] = tl_s1n_48_ds_h2d[13];
- assign tl_s1n_48_ds_d2h[13] = tl_sm1_41_us_d2h[1];
+ assign tl_sm1_47_us_h2d[1] = tl_s1n_52_ds_h2d[15];
+ assign tl_s1n_52_ds_d2h[15] = tl_sm1_47_us_d2h[1];
- assign tl_sm1_42_us_h2d[1] = tl_s1n_48_ds_h2d[14];
- assign tl_s1n_48_ds_d2h[14] = tl_sm1_42_us_d2h[1];
+ assign tl_sm1_48_us_h2d[1] = tl_s1n_52_ds_h2d[16];
+ assign tl_s1n_52_ds_d2h[16] = tl_sm1_48_us_d2h[1];
- assign tl_sm1_43_us_h2d[1] = tl_s1n_48_ds_h2d[15];
- assign tl_s1n_48_ds_d2h[15] = tl_sm1_43_us_d2h[1];
+ assign tl_sm1_49_us_h2d[1] = tl_s1n_52_ds_h2d[17];
+ assign tl_s1n_52_ds_d2h[17] = tl_sm1_49_us_d2h[1];
- assign tl_sm1_44_us_h2d[1] = tl_s1n_48_ds_h2d[16];
- assign tl_s1n_48_ds_d2h[16] = tl_sm1_44_us_d2h[1];
+ assign tl_sm1_50_us_h2d[1] = tl_s1n_52_ds_h2d[18];
+ assign tl_s1n_52_ds_d2h[18] = tl_sm1_50_us_d2h[1];
- assign tl_sm1_45_us_h2d[1] = tl_s1n_48_ds_h2d[17];
- assign tl_s1n_48_ds_d2h[17] = tl_sm1_45_us_d2h[1];
+ assign tl_sm1_51_us_h2d[1] = tl_s1n_52_ds_h2d[19];
+ assign tl_s1n_52_ds_d2h[19] = tl_sm1_51_us_d2h[1];
- assign tl_sm1_46_us_h2d[1] = tl_s1n_48_ds_h2d[18];
- assign tl_s1n_48_ds_d2h[18] = tl_sm1_46_us_d2h[1];
+ assign tl_s1n_26_us_h2d = tl_rv_core_ibex__corei_i;
+ assign tl_rv_core_ibex__corei_o = tl_s1n_26_us_d2h;
- assign tl_sm1_47_us_h2d[1] = tl_s1n_48_ds_h2d[19];
- assign tl_s1n_48_ds_d2h[19] = tl_sm1_47_us_d2h[1];
+ assign tl_rom_ctrl__rom_o = tl_sm1_27_ds_h2d;
+ assign tl_sm1_27_ds_d2h = tl_rom_ctrl__rom_i;
- assign tl_s1n_24_us_h2d = tl_rv_core_ibex__corei_i;
- assign tl_rv_core_ibex__corei_o = tl_s1n_24_us_d2h;
+ assign tl_rv_dm__rom_o = tl_sm1_28_ds_h2d;
+ assign tl_sm1_28_ds_d2h = tl_rv_dm__rom_i;
- assign tl_rom_ctrl__rom_o = tl_sm1_25_ds_h2d;
- assign tl_sm1_25_ds_d2h = tl_rom_ctrl__rom_i;
+ assign tl_sram_ctrl_main__ram_o = tl_sm1_29_ds_h2d;
+ assign tl_sm1_29_ds_d2h = tl_sram_ctrl_main__ram_i;
- assign tl_rv_dm__rom_o = tl_sm1_26_ds_h2d;
- assign tl_sm1_26_ds_d2h = tl_rv_dm__rom_i;
+ assign tl_flash_ctrl__mem_o = tl_sm1_30_ds_h2d;
+ assign tl_sm1_30_ds_d2h = tl_flash_ctrl__mem_i;
- assign tl_sram_ctrl_main__ram_o = tl_sm1_27_ds_h2d;
- assign tl_sm1_27_ds_d2h = tl_sram_ctrl_main__ram_i;
+ assign tl_s1n_31_us_h2d = tl_rv_core_ibex__cored_i;
+ assign tl_rv_core_ibex__cored_o = tl_s1n_31_us_d2h;
- assign tl_flash_ctrl__mem_o = tl_sm1_28_ds_h2d;
- assign tl_sm1_28_ds_d2h = tl_flash_ctrl__mem_i;
+ assign tl_rom_ctrl__regs_o = tl_sm1_32_ds_h2d;
+ assign tl_sm1_32_ds_d2h = tl_rom_ctrl__regs_i;
- assign tl_s1n_29_us_h2d = tl_rv_core_ibex__cored_i;
- assign tl_rv_core_ibex__cored_o = tl_s1n_29_us_d2h;
+ assign tl_rv_dm__regs_o = tl_sm1_33_ds_h2d;
+ assign tl_sm1_33_ds_d2h = tl_rv_dm__regs_i;
- assign tl_rom_ctrl__regs_o = tl_sm1_30_ds_h2d;
- assign tl_sm1_30_ds_d2h = tl_rom_ctrl__regs_i;
+ assign tl_peri_o = tl_asf_34_ds_h2d;
+ assign tl_asf_34_ds_d2h = tl_peri_i;
- assign tl_rv_dm__regs_o = tl_sm1_31_ds_h2d;
- assign tl_sm1_31_ds_d2h = tl_rv_dm__regs_i;
+ assign tl_asf_34_us_h2d = tl_sm1_35_ds_h2d;
+ assign tl_sm1_35_ds_d2h = tl_asf_34_us_d2h;
- assign tl_peri_o = tl_asf_32_ds_h2d;
- assign tl_asf_32_ds_d2h = tl_peri_i;
+ assign tl_spi_host0_o = tl_asf_36_ds_h2d;
+ assign tl_asf_36_ds_d2h = tl_spi_host0_i;
- assign tl_asf_32_us_h2d = tl_sm1_33_ds_h2d;
- assign tl_sm1_33_ds_d2h = tl_asf_32_us_d2h;
+ assign tl_spi_host1_o = tl_asf_37_ds_h2d;
+ assign tl_asf_37_ds_d2h = tl_spi_host1_i;
- assign tl_flash_ctrl__core_o = tl_sm1_34_ds_h2d;
- assign tl_sm1_34_ds_d2h = tl_flash_ctrl__core_i;
+ assign tl_flash_ctrl__core_o = tl_sm1_38_ds_h2d;
+ assign tl_sm1_38_ds_d2h = tl_flash_ctrl__core_i;
- assign tl_flash_ctrl__prim_o = tl_sm1_35_ds_h2d;
- assign tl_sm1_35_ds_d2h = tl_flash_ctrl__prim_i;
+ assign tl_flash_ctrl__prim_o = tl_sm1_39_ds_h2d;
+ assign tl_sm1_39_ds_d2h = tl_flash_ctrl__prim_i;
- assign tl_aes_o = tl_sm1_36_ds_h2d;
- assign tl_sm1_36_ds_d2h = tl_aes_i;
+ assign tl_aes_o = tl_sm1_40_ds_h2d;
+ assign tl_sm1_40_ds_d2h = tl_aes_i;
- assign tl_entropy_src_o = tl_sm1_37_ds_h2d;
- assign tl_sm1_37_ds_d2h = tl_entropy_src_i;
+ assign tl_entropy_src_o = tl_sm1_41_ds_h2d;
+ assign tl_sm1_41_ds_d2h = tl_entropy_src_i;
- assign tl_csrng_o = tl_sm1_38_ds_h2d;
- assign tl_sm1_38_ds_d2h = tl_csrng_i;
+ assign tl_csrng_o = tl_sm1_42_ds_h2d;
+ assign tl_sm1_42_ds_d2h = tl_csrng_i;
- assign tl_edn0_o = tl_sm1_39_ds_h2d;
- assign tl_sm1_39_ds_d2h = tl_edn0_i;
+ assign tl_edn0_o = tl_sm1_43_ds_h2d;
+ assign tl_sm1_43_ds_d2h = tl_edn0_i;
- assign tl_edn1_o = tl_sm1_40_ds_h2d;
- assign tl_sm1_40_ds_d2h = tl_edn1_i;
+ assign tl_edn1_o = tl_sm1_44_ds_h2d;
+ assign tl_sm1_44_ds_d2h = tl_edn1_i;
- assign tl_hmac_o = tl_sm1_41_ds_h2d;
- assign tl_sm1_41_ds_d2h = tl_hmac_i;
+ assign tl_hmac_o = tl_sm1_45_ds_h2d;
+ assign tl_sm1_45_ds_d2h = tl_hmac_i;
- assign tl_rv_plic_o = tl_sm1_42_ds_h2d;
- assign tl_sm1_42_ds_d2h = tl_rv_plic_i;
+ assign tl_rv_plic_o = tl_sm1_46_ds_h2d;
+ assign tl_sm1_46_ds_d2h = tl_rv_plic_i;
- assign tl_otbn_o = tl_sm1_43_ds_h2d;
- assign tl_sm1_43_ds_d2h = tl_otbn_i;
+ assign tl_otbn_o = tl_sm1_47_ds_h2d;
+ assign tl_sm1_47_ds_d2h = tl_otbn_i;
- assign tl_keymgr_o = tl_sm1_44_ds_h2d;
- assign tl_sm1_44_ds_d2h = tl_keymgr_i;
+ assign tl_keymgr_o = tl_sm1_48_ds_h2d;
+ assign tl_sm1_48_ds_d2h = tl_keymgr_i;
- assign tl_kmac_o = tl_sm1_45_ds_h2d;
- assign tl_sm1_45_ds_d2h = tl_kmac_i;
+ assign tl_kmac_o = tl_sm1_49_ds_h2d;
+ assign tl_sm1_49_ds_d2h = tl_kmac_i;
- assign tl_sram_ctrl_main__regs_o = tl_sm1_46_ds_h2d;
- assign tl_sm1_46_ds_d2h = tl_sram_ctrl_main__regs_i;
+ assign tl_sram_ctrl_main__regs_o = tl_sm1_50_ds_h2d;
+ assign tl_sm1_50_ds_d2h = tl_sram_ctrl_main__regs_i;
- assign tl_rv_core_ibex__cfg_o = tl_sm1_47_ds_h2d;
- assign tl_sm1_47_ds_d2h = tl_rv_core_ibex__cfg_i;
+ assign tl_rv_core_ibex__cfg_o = tl_sm1_51_ds_h2d;
+ assign tl_sm1_51_ds_d2h = tl_rv_core_ibex__cfg_i;
- assign tl_s1n_48_us_h2d = tl_rv_dm__sba_i;
- assign tl_rv_dm__sba_o = tl_s1n_48_us_d2h;
+ assign tl_s1n_52_us_h2d = tl_rv_dm__sba_i;
+ assign tl_rv_dm__sba_o = tl_s1n_52_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_24 = 3'd4;
- if ((tl_s1n_24_us_h2d.a_address &
+ dev_sel_s1n_26 = 3'd4;
+ if ((tl_s1n_26_us_h2d.a_address &
~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin
- dev_sel_s1n_24 = 3'd0;
+ dev_sel_s1n_26 = 3'd0;
- end else if ((tl_s1n_24_us_h2d.a_address &
+ end else if ((tl_s1n_26_us_h2d.a_address &
~(ADDR_MASK_RV_DM__ROM)) == ADDR_SPACE_RV_DM__ROM) begin
- dev_sel_s1n_24 = 3'd1;
+ dev_sel_s1n_26 = 3'd1;
- end else if ((tl_s1n_24_us_h2d.a_address &
+ end else if ((tl_s1n_26_us_h2d.a_address &
~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
- dev_sel_s1n_24 = 3'd2;
+ dev_sel_s1n_26 = 3'd2;
- end else if ((tl_s1n_24_us_h2d.a_address &
+ end else if ((tl_s1n_26_us_h2d.a_address &
~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin
- dev_sel_s1n_24 = 3'd3;
+ dev_sel_s1n_26 = 3'd3;
end
end
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_29 = 5'd21;
- if ((tl_s1n_29_us_h2d.a_address &
+ dev_sel_s1n_31 = 5'd23;
+ if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin
- dev_sel_s1n_29 = 5'd0;
+ dev_sel_s1n_31 = 5'd0;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin
- dev_sel_s1n_29 = 5'd1;
+ dev_sel_s1n_31 = 5'd1;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_RV_DM__ROM)) == ADDR_SPACE_RV_DM__ROM) begin
- dev_sel_s1n_29 = 5'd2;
+ dev_sel_s1n_31 = 5'd2;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin
- dev_sel_s1n_29 = 5'd3;
+ dev_sel_s1n_31 = 5'd3;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
- dev_sel_s1n_29 = 5'd4;
+ dev_sel_s1n_31 = 5'd4;
- end else if ((tl_s1n_29_us_h2d.a_address &
- ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin
- dev_sel_s1n_29 = 5'd5;
+ end else if (
+ ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
+ ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1])
+ ) begin
+ dev_sel_s1n_31 = 5'd5;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
+ ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin
+ dev_sel_s1n_31 = 5'd6;
+
+ end else if ((tl_s1n_31_us_h2d.a_address &
+ ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin
+ dev_sel_s1n_31 = 5'd7;
+
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin
- dev_sel_s1n_29 = 5'd6;
+ dev_sel_s1n_31 = 5'd8;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin
- dev_sel_s1n_29 = 5'd7;
+ dev_sel_s1n_31 = 5'd9;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin
- dev_sel_s1n_29 = 5'd8;
+ dev_sel_s1n_31 = 5'd10;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
- dev_sel_s1n_29 = 5'd9;
+ dev_sel_s1n_31 = 5'd11;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin
- dev_sel_s1n_29 = 5'd10;
+ dev_sel_s1n_31 = 5'd12;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin
- dev_sel_s1n_29 = 5'd11;
+ dev_sel_s1n_31 = 5'd13;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin
- dev_sel_s1n_29 = 5'd12;
+ dev_sel_s1n_31 = 5'd14;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin
- dev_sel_s1n_29 = 5'd13;
+ dev_sel_s1n_31 = 5'd15;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
- dev_sel_s1n_29 = 5'd14;
+ dev_sel_s1n_31 = 5'd16;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
- dev_sel_s1n_29 = 5'd15;
+ dev_sel_s1n_31 = 5'd17;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
- dev_sel_s1n_29 = 5'd16;
+ dev_sel_s1n_31 = 5'd18;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin
- dev_sel_s1n_29 = 5'd17;
+ dev_sel_s1n_31 = 5'd19;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
- dev_sel_s1n_29 = 5'd18;
+ dev_sel_s1n_31 = 5'd20;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin
- dev_sel_s1n_29 = 5'd19;
+ dev_sel_s1n_31 = 5'd21;
- end else if ((tl_s1n_29_us_h2d.a_address &
+ end else if ((tl_s1n_31_us_h2d.a_address &
~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin
- dev_sel_s1n_29 = 5'd20;
+ dev_sel_s1n_31 = 5'd22;
end
end
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_48 = 5'd20;
- if ((tl_s1n_48_us_h2d.a_address &
+ dev_sel_s1n_52 = 5'd20;
+ if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin
- dev_sel_s1n_48 = 5'd0;
+ dev_sel_s1n_52 = 5'd0;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin
- dev_sel_s1n_48 = 5'd1;
+ dev_sel_s1n_52 = 5'd1;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin
- dev_sel_s1n_48 = 5'd2;
+ dev_sel_s1n_52 = 5'd2;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
- dev_sel_s1n_48 = 5'd3;
+ dev_sel_s1n_52 = 5'd3;
- end else if ((tl_s1n_48_us_h2d.a_address &
- ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin
- dev_sel_s1n_48 = 5'd4;
+ end else if (
+ ((tl_s1n_52_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
+ ((tl_s1n_52_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1])
+ ) begin
+ dev_sel_s1n_52 = 5'd4;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin
- dev_sel_s1n_48 = 5'd5;
+ dev_sel_s1n_52 = 5'd5;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin
- dev_sel_s1n_48 = 5'd6;
+ dev_sel_s1n_52 = 5'd6;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin
- dev_sel_s1n_48 = 5'd7;
+ dev_sel_s1n_52 = 5'd7;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
- dev_sel_s1n_48 = 5'd8;
+ dev_sel_s1n_52 = 5'd8;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin
- dev_sel_s1n_48 = 5'd9;
+ dev_sel_s1n_52 = 5'd9;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin
- dev_sel_s1n_48 = 5'd10;
+ dev_sel_s1n_52 = 5'd10;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin
- dev_sel_s1n_48 = 5'd11;
+ dev_sel_s1n_52 = 5'd11;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin
- dev_sel_s1n_48 = 5'd12;
+ dev_sel_s1n_52 = 5'd12;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
- dev_sel_s1n_48 = 5'd13;
+ dev_sel_s1n_52 = 5'd13;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
- dev_sel_s1n_48 = 5'd14;
+ dev_sel_s1n_52 = 5'd14;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
- dev_sel_s1n_48 = 5'd15;
+ dev_sel_s1n_52 = 5'd15;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin
- dev_sel_s1n_48 = 5'd16;
+ dev_sel_s1n_52 = 5'd16;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
- dev_sel_s1n_48 = 5'd17;
+ dev_sel_s1n_52 = 5'd17;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin
- dev_sel_s1n_48 = 5'd18;
+ dev_sel_s1n_52 = 5'd18;
- end else if ((tl_s1n_48_us_h2d.a_address &
+ end else if ((tl_s1n_52_us_h2d.a_address &
~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin
- dev_sel_s1n_48 = 5'd19;
+ dev_sel_s1n_52 = 5'd19;
end
end
@@ -771,42 +817,14 @@
.DReqDepth (16'h0),
.DRspDepth (16'h0),
.N (4)
- ) u_s1n_24 (
+ ) u_s1n_26 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_24_us_h2d),
- .tl_h_o (tl_s1n_24_us_d2h),
- .tl_d_o (tl_s1n_24_ds_h2d),
- .tl_d_i (tl_s1n_24_ds_d2h),
- .dev_select_i (dev_sel_s1n_24)
- );
- tlul_socket_m1 #(
- .HReqDepth (12'h0),
- .HRspDepth (12'h0),
- .DReqDepth (4'h0),
- .DRspDepth (4'h0),
- .M (3)
- ) u_sm1_25 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_25_us_h2d),
- .tl_h_o (tl_sm1_25_us_d2h),
- .tl_d_o (tl_sm1_25_ds_h2d),
- .tl_d_i (tl_sm1_25_ds_d2h)
- );
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_26 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_26_us_h2d),
- .tl_h_o (tl_sm1_26_us_d2h),
- .tl_d_o (tl_sm1_26_ds_h2d),
- .tl_d_i (tl_sm1_26_ds_d2h)
+ .tl_h_i (tl_s1n_26_us_h2d),
+ .tl_h_o (tl_s1n_26_us_d2h),
+ .tl_d_o (tl_s1n_26_ds_h2d),
+ .tl_d_i (tl_s1n_26_ds_d2h),
+ .dev_select_i (dev_sel_s1n_26)
);
tlul_socket_m1 #(
.HReqDepth (12'h0),
@@ -823,11 +841,11 @@
.tl_d_i (tl_sm1_27_ds_d2h)
);
tlul_socket_m1 #(
- .HReqDepth (12'h0),
- .HRspDepth (12'h0),
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
.DReqPass (1'b0),
.DRspPass (1'b0),
- .M (3)
+ .M (2)
) u_sm1_28 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -836,27 +854,26 @@
.tl_d_o (tl_sm1_28_ds_h2d),
.tl_d_i (tl_sm1_28_ds_d2h)
);
- tlul_socket_1n #(
- .HReqDepth (4'h0),
- .HRspDepth (4'h0),
- .DReqDepth (84'h0),
- .DRspDepth (84'h0),
- .N (21)
- ) u_s1n_29 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_29_us_h2d),
- .tl_h_o (tl_s1n_29_us_d2h),
- .tl_d_o (tl_s1n_29_ds_h2d),
- .tl_d_i (tl_s1n_29_ds_d2h),
- .dev_select_i (dev_sel_s1n_29)
- );
tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
+ .HReqDepth (12'h0),
+ .HRspDepth (12'h0),
.DReqDepth (4'h0),
.DRspDepth (4'h0),
- .M (2)
+ .M (3)
+ ) u_sm1_29 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_29_us_h2d),
+ .tl_h_o (tl_sm1_29_us_d2h),
+ .tl_d_o (tl_sm1_29_ds_h2d),
+ .tl_d_i (tl_sm1_29_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (12'h0),
+ .HRspDepth (12'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (3)
) u_sm1_30 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -865,32 +882,20 @@
.tl_d_o (tl_sm1_30_ds_h2d),
.tl_d_i (tl_sm1_30_ds_d2h)
);
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_31 (
+ tlul_socket_1n #(
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth (92'h0),
+ .DRspDepth (92'h0),
+ .N (23)
+ ) u_s1n_31 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_31_us_h2d),
- .tl_h_o (tl_sm1_31_us_d2h),
- .tl_d_o (tl_sm1_31_ds_h2d),
- .tl_d_i (tl_sm1_31_ds_d2h)
- );
- tlul_fifo_async #(
- .ReqDepth (4),// At least 4 to make async work
- .RspDepth (4) // At least 4 to make async work
- ) u_asf_32 (
- .clk_h_i (clk_main_i),
- .rst_h_ni (rst_main_ni),
- .clk_d_i (clk_fixed_i),
- .rst_d_ni (rst_fixed_ni),
- .tl_h_i (tl_asf_32_us_h2d),
- .tl_h_o (tl_asf_32_us_d2h),
- .tl_d_o (tl_asf_32_ds_h2d),
- .tl_d_i (tl_asf_32_ds_d2h)
+ .tl_h_i (tl_s1n_31_us_h2d),
+ .tl_h_o (tl_s1n_31_us_d2h),
+ .tl_d_o (tl_s1n_31_ds_h2d),
+ .tl_d_i (tl_s1n_31_ds_d2h),
+ .dev_select_i (dev_sel_s1n_31)
);
tlul_socket_m1 #(
.HReqDepth (8'h0),
@@ -898,6 +903,20 @@
.DReqDepth (4'h0),
.DRspDepth (4'h0),
.M (2)
+ ) u_sm1_32 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_32_us_h2d),
+ .tl_h_o (tl_sm1_32_us_d2h),
+ .tl_d_o (tl_sm1_32_ds_h2d),
+ .tl_d_i (tl_sm1_32_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
) u_sm1_33 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -906,25 +925,24 @@
.tl_d_o (tl_sm1_33_ds_h2d),
.tl_d_i (tl_sm1_33_ds_d2h)
);
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_34 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_34_us_h2d),
- .tl_h_o (tl_sm1_34_us_d2h),
- .tl_d_o (tl_sm1_34_ds_h2d),
- .tl_d_i (tl_sm1_34_ds_d2h)
+ tlul_fifo_async #(
+ .ReqDepth (4),// At least 4 to make async work
+ .RspDepth (4) // At least 4 to make async work
+ ) u_asf_34 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_fixed_i),
+ .rst_d_ni (rst_fixed_ni),
+ .tl_h_i (tl_asf_34_us_h2d),
+ .tl_h_o (tl_asf_34_us_d2h),
+ .tl_d_o (tl_asf_34_ds_h2d),
+ .tl_d_i (tl_asf_34_ds_d2h)
);
tlul_socket_m1 #(
.HReqDepth (8'h0),
.HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
.M (2)
) u_sm1_35 (
.clk_i (clk_main_i),
@@ -934,33 +952,31 @@
.tl_d_o (tl_sm1_35_ds_h2d),
.tl_d_i (tl_sm1_35_ds_d2h)
);
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_36 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_36_us_h2d),
- .tl_h_o (tl_sm1_36_us_d2h),
- .tl_d_o (tl_sm1_36_ds_h2d),
- .tl_d_i (tl_sm1_36_ds_d2h)
+ tlul_fifo_async #(
+ .ReqDepth (4),// At least 4 to make async work
+ .RspDepth (4) // At least 4 to make async work
+ ) u_asf_36 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_spi_host0_i),
+ .rst_d_ni (rst_spi_host0_ni),
+ .tl_h_i (tl_asf_36_us_h2d),
+ .tl_h_o (tl_asf_36_us_d2h),
+ .tl_d_o (tl_asf_36_ds_h2d),
+ .tl_d_i (tl_asf_36_ds_d2h)
);
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_37 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_37_us_h2d),
- .tl_h_o (tl_sm1_37_us_d2h),
- .tl_d_o (tl_sm1_37_ds_h2d),
- .tl_d_i (tl_sm1_37_ds_d2h)
+ tlul_fifo_async #(
+ .ReqDepth (4),// At least 4 to make async work
+ .RspDepth (4) // At least 4 to make async work
+ ) u_asf_37 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_spi_host1_i),
+ .rst_d_ni (rst_spi_host1_ni),
+ .tl_h_i (tl_asf_37_us_h2d),
+ .tl_h_o (tl_asf_37_us_d2h),
+ .tl_d_o (tl_asf_37_ds_h2d),
+ .tl_d_i (tl_asf_37_ds_d2h)
);
tlul_socket_m1 #(
.HReqDepth (8'h0),
@@ -1077,8 +1093,8 @@
tlul_socket_m1 #(
.HReqDepth (8'h0),
.HRspDepth (8'h0),
- .DReqDepth (4'h0),
- .DRspDepth (4'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
.M (2)
) u_sm1_46 (
.clk_i (clk_main_i),
@@ -1102,20 +1118,76 @@
.tl_d_o (tl_sm1_47_ds_h2d),
.tl_d_i (tl_sm1_47_ds_d2h)
);
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_48 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_48_us_h2d),
+ .tl_h_o (tl_sm1_48_us_d2h),
+ .tl_d_o (tl_sm1_48_ds_h2d),
+ .tl_d_i (tl_sm1_48_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_49 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_49_us_h2d),
+ .tl_h_o (tl_sm1_49_us_d2h),
+ .tl_d_o (tl_sm1_49_ds_h2d),
+ .tl_d_i (tl_sm1_49_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_50 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_50_us_h2d),
+ .tl_h_o (tl_sm1_50_us_d2h),
+ .tl_d_o (tl_sm1_50_ds_h2d),
+ .tl_d_i (tl_sm1_50_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_51 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_51_us_h2d),
+ .tl_h_o (tl_sm1_51_us_d2h),
+ .tl_d_o (tl_sm1_51_ds_h2d),
+ .tl_d_i (tl_sm1_51_ds_d2h)
+ );
tlul_socket_1n #(
.HReqPass (1'b0),
.HRspPass (1'b0),
.DReqDepth (80'h0),
.DRspDepth (80'h0),
.N (20)
- ) u_s1n_48 (
+ ) u_s1n_52 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_48_us_h2d),
- .tl_h_o (tl_s1n_48_us_d2h),
- .tl_d_o (tl_s1n_48_ds_h2d),
- .tl_d_i (tl_s1n_48_ds_d2h),
- .dev_select_i (dev_sel_s1n_48)
+ .tl_h_i (tl_s1n_52_us_h2d),
+ .tl_h_o (tl_s1n_52_us_d2h),
+ .tl_d_o (tl_s1n_52_ds_h2d),
+ .tl_d_i (tl_s1n_52_ds_d2h),
+ .dev_select_i (dev_sel_s1n_52)
);
endmodule
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index a773ca7..3523875 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -11,8 +11,6 @@
clock_srcs:
{
clk_peri_i: io_div4
- clk_spi_host0_i: io
- clk_spi_host1_i: io_div2
}
clock_group: infra
reset: rst_peri_ni
@@ -23,22 +21,10 @@
name: sys_io_div4
domain: "0"
}
- rst_spi_host0_ni:
- {
- name: spi_host0
- domain: "0"
- }
- rst_spi_host1_ni:
- {
- name: spi_host1
- domain: "0"
- }
}
clock_connections:
{
clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
- clk_spi_host0_i: clkmgr_aon_clocks.clk_io_infra
- clk_spi_host1_i: clkmgr_aon_clocks.clk_io_div2_infra
}
domain:
[
@@ -58,8 +44,6 @@
pattgen
gpio
spi_device
- spi_host0
- spi_host1
rv_timer
usbdev
pwrmgr_aon
@@ -292,42 +276,6 @@
pipeline_byp: "true"
}
{
- name: spi_host0
- type: device
- clock: clk_spi_host0_i
- reset: rst_spi_host0_ni
- pipeline: "false"
- inst_type: spi_host
- addr_range:
- [
- {
- base_addr: 0x40060000
- size_byte: 0x1000
- }
- ]
- xbar: false
- stub: false
- pipeline_byp: "true"
- }
- {
- name: spi_host1
- type: device
- clock: clk_spi_host1_i
- reset: rst_spi_host1_ni
- pipeline: "false"
- inst_type: spi_host
- addr_range:
- [
- {
- base_addr: 0x40070000
- size_byte: 0x1000
- }
- ]
- xbar: false
- stub: false
- pipeline_byp: "true"
- }
- {
name: rv_timer
type: device
clock: clk_peri_i
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
index 70e7409..30fafd0 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
@@ -87,18 +87,6 @@
}
{ struct: "tl"
type: "req_rsp"
- name: "tl_spi_host0"
- act: "req"
- package: "tlul_pkg"
- }
- { struct: "tl"
- type: "req_rsp"
- name: "tl_spi_host1"
- act: "req"
- package: "tlul_pkg"
- }
- { struct: "tl"
- type: "req_rsp"
name: "tl_rv_timer"
act: "req"
package: "tlul_pkg"
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
index 9e57327..f07b28c 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -7,17 +7,11 @@
xbar_peri dut();
`DRIVE_CLK(clk_peri_i)
-`DRIVE_CLK(clk_spi_host0_i)
-`DRIVE_CLK(clk_spi_host1_i)
initial force dut.clk_peri_i = clk_peri_i;
-initial force dut.clk_spi_host0_i = clk_spi_host0_i;
-initial force dut.clk_spi_host1_i = clk_spi_host1_i;
// TODO, all resets tie together
initial force dut.rst_peri_ni = rst_n;
-initial force dut.rst_spi_host0_ni = rst_n;
-initial force dut.rst_spi_host1_ni = rst_n;
// Host TileLink interface connections
`CONNECT_TL_HOST_IF(main, dut, clk_peri_i, rst_n)
@@ -34,8 +28,6 @@
`CONNECT_TL_DEVICE_IF(pwm_aon, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(gpio, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(spi_device, dut, clk_peri_i, rst_n)
-`CONNECT_TL_DEVICE_IF(spi_host0, dut, clk_spi_host0_i, rst_n)
-`CONNECT_TL_DEVICE_IF(spi_host1, dut, clk_spi_host1_i, rst_n)
`CONNECT_TL_DEVICE_IF(rv_timer, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(usbdev, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(pwrmgr_aon, dut, clk_peri_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
index 40cb8f2..b43fb45 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
@@ -51,12 +51,6 @@
-node tb.dut tl_spi_device_o.a_address[17:17]
-node tb.dut tl_spi_device_o.a_address[29:19]
-node tb.dut tl_spi_device_o.a_address[31:31]
--node tb.dut tl_spi_host0_o.a_address[16:12]
--node tb.dut tl_spi_host0_o.a_address[29:19]
--node tb.dut tl_spi_host0_o.a_address[31:31]
--node tb.dut tl_spi_host1_o.a_address[15:12]
--node tb.dut tl_spi_host1_o.a_address[29:19]
--node tb.dut tl_spi_host1_o.a_address[31:31]
-node tb.dut tl_rv_timer_o.a_address[19:12]
-node tb.dut tl_rv_timer_o.a_address[29:21]
-node tb.dut tl_rv_timer_o.a_address[31:31]
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
index 9a0440f..179ab01 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -40,12 +40,6 @@
'{"spi_device", '{
'{32'h40050000, 32'h40051fff}
}},
- '{"spi_host0", '{
- '{32'h40060000, 32'h40060fff}
- }},
- '{"spi_host1", '{
- '{32'h40070000, 32'h40070fff}
- }},
'{"rv_timer", '{
'{32'h40100000, 32'h40100fff}
}},
@@ -111,8 +105,6 @@
"pattgen",
"gpio",
"spi_device",
- "spi_host0",
- "spi_host1",
"rv_timer",
"usbdev",
"pwrmgr_aon",
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
index 9c78a74..2709911 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -80,18 +80,6 @@
.h2d (tl_spi_device_o),
.d2h (tl_spi_device_i)
);
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host0 (
- .clk_i (clk_spi_host0_i),
- .rst_ni (rst_spi_host0_ni),
- .h2d (tl_spi_host0_o),
- .d2h (tl_spi_host0_i)
- );
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host1 (
- .clk_i (clk_spi_host1_i),
- .rst_ni (rst_spi_host1_ni),
- .h2d (tl_spi_host1_o),
- .d2h (tl_spi_host1_i)
- );
bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_timer (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
index c98f96f..0823e18 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -17,8 +17,6 @@
localparam logic [31:0] ADDR_SPACE_PWM_AON = 32'h 40450000;
localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40040000;
localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40050000;
- localparam logic [31:0] ADDR_SPACE_SPI_HOST0 = 32'h 40060000;
- localparam logic [31:0] ADDR_SPACE_SPI_HOST1 = 32'h 40070000;
localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40100000;
localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 40110000;
localparam logic [31:0] ADDR_SPACE_PWRMGR_AON = 32'h 40400000;
@@ -48,8 +46,6 @@
localparam logic [31:0] ADDR_MASK_PWM_AON = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00001fff;
- localparam logic [31:0] ADDR_MASK_SPI_HOST0 = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_SPI_HOST1 = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_PWRMGR_AON = 32'h 00000fff;
@@ -69,7 +65,7 @@
localparam logic [31:0] ADDR_MASK_AST = 32'h 00000fff;
localparam int N_HOST = 1;
- localparam int N_DEVICE = 30;
+ localparam int N_DEVICE = 28;
typedef enum int {
TlUart0 = 0,
@@ -83,25 +79,23 @@
TlPwmAon = 8,
TlGpio = 9,
TlSpiDevice = 10,
- TlSpiHost0 = 11,
- TlSpiHost1 = 12,
- TlRvTimer = 13,
- TlUsbdev = 14,
- TlPwrmgrAon = 15,
- TlRstmgrAon = 16,
- TlClkmgrAon = 17,
- TlPinmuxAon = 18,
- TlOtpCtrlCore = 19,
- TlOtpCtrlPrim = 20,
- TlLcCtrl = 21,
- TlSensorCtrl = 22,
- TlAlertHandler = 23,
- TlSramCtrlRetAonRegs = 24,
- TlSramCtrlRetAonRam = 25,
- TlAonTimerAon = 26,
- TlSysrstCtrlAon = 27,
- TlAdcCtrlAon = 28,
- TlAst = 29
+ TlRvTimer = 11,
+ TlUsbdev = 12,
+ TlPwrmgrAon = 13,
+ TlRstmgrAon = 14,
+ TlClkmgrAon = 15,
+ TlPinmuxAon = 16,
+ TlOtpCtrlCore = 17,
+ TlOtpCtrlPrim = 18,
+ TlLcCtrl = 19,
+ TlSensorCtrl = 20,
+ TlAlertHandler = 21,
+ TlSramCtrlRetAonRegs = 22,
+ TlSramCtrlRetAonRam = 23,
+ TlAonTimerAon = 24,
+ TlSysrstCtrlAon = 25,
+ TlAdcCtrlAon = 26,
+ TlAst = 27
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
index fa0a8a3..e4e28f2 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -7,7 +7,7 @@
//
// Interconnect
// main
-// -> s1n_31
+// -> s1n_29
// -> uart0
// -> uart1
// -> uart2
@@ -18,10 +18,6 @@
// -> pattgen
// -> gpio
// -> spi_device
-// -> asf_32
-// -> spi_host0
-// -> asf_33
-// -> spi_host1
// -> rv_timer
// -> usbdev
// -> pwrmgr_aon
@@ -43,11 +39,7 @@
module xbar_peri (
input clk_peri_i,
- input clk_spi_host0_i,
- input clk_spi_host1_i,
input rst_peri_ni,
- input rst_spi_host0_ni,
- input rst_spi_host1_ni,
// Host interfaces
input tlul_pkg::tl_h2d_t tl_main_i,
@@ -76,10 +68,6 @@
input tlul_pkg::tl_d2h_t tl_gpio_i,
output tlul_pkg::tl_h2d_t tl_spi_device_o,
input tlul_pkg::tl_d2h_t tl_spi_device_i,
- output tlul_pkg::tl_h2d_t tl_spi_host0_o,
- input tlul_pkg::tl_d2h_t tl_spi_host0_i,
- output tlul_pkg::tl_h2d_t tl_spi_host1_o,
- input tlul_pkg::tl_d2h_t tl_spi_host1_i,
output tlul_pkg::tl_h2d_t tl_rv_timer_o,
input tlul_pkg::tl_d2h_t tl_rv_timer_i,
output tlul_pkg::tl_h2d_t tl_usbdev_o,
@@ -126,249 +114,219 @@
logic unused_scanmode;
assign unused_scanmode = ^scanmode_i;
- tl_h2d_t tl_s1n_31_us_h2d ;
- tl_d2h_t tl_s1n_31_us_d2h ;
+ tl_h2d_t tl_s1n_29_us_h2d ;
+ tl_d2h_t tl_s1n_29_us_d2h ;
- tl_h2d_t tl_s1n_31_ds_h2d [30];
- tl_d2h_t tl_s1n_31_ds_d2h [30];
+ tl_h2d_t tl_s1n_29_ds_h2d [28];
+ tl_d2h_t tl_s1n_29_ds_d2h [28];
// Create steering signal
- logic [4:0] dev_sel_s1n_31;
-
- tl_h2d_t tl_asf_32_us_h2d ;
- tl_d2h_t tl_asf_32_us_d2h ;
- tl_h2d_t tl_asf_32_ds_h2d ;
- tl_d2h_t tl_asf_32_ds_d2h ;
-
- tl_h2d_t tl_asf_33_us_h2d ;
- tl_d2h_t tl_asf_33_us_d2h ;
- tl_h2d_t tl_asf_33_ds_h2d ;
- tl_d2h_t tl_asf_33_ds_d2h ;
+ logic [4:0] dev_sel_s1n_29;
- assign tl_uart0_o = tl_s1n_31_ds_h2d[0];
- assign tl_s1n_31_ds_d2h[0] = tl_uart0_i;
+ assign tl_uart0_o = tl_s1n_29_ds_h2d[0];
+ assign tl_s1n_29_ds_d2h[0] = tl_uart0_i;
- assign tl_uart1_o = tl_s1n_31_ds_h2d[1];
- assign tl_s1n_31_ds_d2h[1] = tl_uart1_i;
+ assign tl_uart1_o = tl_s1n_29_ds_h2d[1];
+ assign tl_s1n_29_ds_d2h[1] = tl_uart1_i;
- assign tl_uart2_o = tl_s1n_31_ds_h2d[2];
- assign tl_s1n_31_ds_d2h[2] = tl_uart2_i;
+ assign tl_uart2_o = tl_s1n_29_ds_h2d[2];
+ assign tl_s1n_29_ds_d2h[2] = tl_uart2_i;
- assign tl_uart3_o = tl_s1n_31_ds_h2d[3];
- assign tl_s1n_31_ds_d2h[3] = tl_uart3_i;
+ assign tl_uart3_o = tl_s1n_29_ds_h2d[3];
+ assign tl_s1n_29_ds_d2h[3] = tl_uart3_i;
- assign tl_i2c0_o = tl_s1n_31_ds_h2d[4];
- assign tl_s1n_31_ds_d2h[4] = tl_i2c0_i;
+ assign tl_i2c0_o = tl_s1n_29_ds_h2d[4];
+ assign tl_s1n_29_ds_d2h[4] = tl_i2c0_i;
- assign tl_i2c1_o = tl_s1n_31_ds_h2d[5];
- assign tl_s1n_31_ds_d2h[5] = tl_i2c1_i;
+ assign tl_i2c1_o = tl_s1n_29_ds_h2d[5];
+ assign tl_s1n_29_ds_d2h[5] = tl_i2c1_i;
- assign tl_i2c2_o = tl_s1n_31_ds_h2d[6];
- assign tl_s1n_31_ds_d2h[6] = tl_i2c2_i;
+ assign tl_i2c2_o = tl_s1n_29_ds_h2d[6];
+ assign tl_s1n_29_ds_d2h[6] = tl_i2c2_i;
- assign tl_pattgen_o = tl_s1n_31_ds_h2d[7];
- assign tl_s1n_31_ds_d2h[7] = tl_pattgen_i;
+ assign tl_pattgen_o = tl_s1n_29_ds_h2d[7];
+ assign tl_s1n_29_ds_d2h[7] = tl_pattgen_i;
- assign tl_gpio_o = tl_s1n_31_ds_h2d[8];
- assign tl_s1n_31_ds_d2h[8] = tl_gpio_i;
+ assign tl_gpio_o = tl_s1n_29_ds_h2d[8];
+ assign tl_s1n_29_ds_d2h[8] = tl_gpio_i;
- assign tl_spi_device_o = tl_s1n_31_ds_h2d[9];
- assign tl_s1n_31_ds_d2h[9] = tl_spi_device_i;
+ assign tl_spi_device_o = tl_s1n_29_ds_h2d[9];
+ assign tl_s1n_29_ds_d2h[9] = tl_spi_device_i;
- assign tl_asf_32_us_h2d = tl_s1n_31_ds_h2d[10];
- assign tl_s1n_31_ds_d2h[10] = tl_asf_32_us_d2h;
+ assign tl_rv_timer_o = tl_s1n_29_ds_h2d[10];
+ assign tl_s1n_29_ds_d2h[10] = tl_rv_timer_i;
- assign tl_asf_33_us_h2d = tl_s1n_31_ds_h2d[11];
- assign tl_s1n_31_ds_d2h[11] = tl_asf_33_us_d2h;
+ assign tl_usbdev_o = tl_s1n_29_ds_h2d[11];
+ assign tl_s1n_29_ds_d2h[11] = tl_usbdev_i;
- assign tl_rv_timer_o = tl_s1n_31_ds_h2d[12];
- assign tl_s1n_31_ds_d2h[12] = tl_rv_timer_i;
+ assign tl_pwrmgr_aon_o = tl_s1n_29_ds_h2d[12];
+ assign tl_s1n_29_ds_d2h[12] = tl_pwrmgr_aon_i;
- assign tl_usbdev_o = tl_s1n_31_ds_h2d[13];
- assign tl_s1n_31_ds_d2h[13] = tl_usbdev_i;
+ assign tl_rstmgr_aon_o = tl_s1n_29_ds_h2d[13];
+ assign tl_s1n_29_ds_d2h[13] = tl_rstmgr_aon_i;
- assign tl_pwrmgr_aon_o = tl_s1n_31_ds_h2d[14];
- assign tl_s1n_31_ds_d2h[14] = tl_pwrmgr_aon_i;
+ assign tl_clkmgr_aon_o = tl_s1n_29_ds_h2d[14];
+ assign tl_s1n_29_ds_d2h[14] = tl_clkmgr_aon_i;
- assign tl_rstmgr_aon_o = tl_s1n_31_ds_h2d[15];
- assign tl_s1n_31_ds_d2h[15] = tl_rstmgr_aon_i;
+ assign tl_pinmux_aon_o = tl_s1n_29_ds_h2d[15];
+ assign tl_s1n_29_ds_d2h[15] = tl_pinmux_aon_i;
- assign tl_clkmgr_aon_o = tl_s1n_31_ds_h2d[16];
- assign tl_s1n_31_ds_d2h[16] = tl_clkmgr_aon_i;
+ assign tl_otp_ctrl__core_o = tl_s1n_29_ds_h2d[16];
+ assign tl_s1n_29_ds_d2h[16] = tl_otp_ctrl__core_i;
- assign tl_pinmux_aon_o = tl_s1n_31_ds_h2d[17];
- assign tl_s1n_31_ds_d2h[17] = tl_pinmux_aon_i;
+ assign tl_otp_ctrl__prim_o = tl_s1n_29_ds_h2d[17];
+ assign tl_s1n_29_ds_d2h[17] = tl_otp_ctrl__prim_i;
- assign tl_otp_ctrl__core_o = tl_s1n_31_ds_h2d[18];
- assign tl_s1n_31_ds_d2h[18] = tl_otp_ctrl__core_i;
+ assign tl_lc_ctrl_o = tl_s1n_29_ds_h2d[18];
+ assign tl_s1n_29_ds_d2h[18] = tl_lc_ctrl_i;
- assign tl_otp_ctrl__prim_o = tl_s1n_31_ds_h2d[19];
- assign tl_s1n_31_ds_d2h[19] = tl_otp_ctrl__prim_i;
+ assign tl_sensor_ctrl_o = tl_s1n_29_ds_h2d[19];
+ assign tl_s1n_29_ds_d2h[19] = tl_sensor_ctrl_i;
- assign tl_lc_ctrl_o = tl_s1n_31_ds_h2d[20];
- assign tl_s1n_31_ds_d2h[20] = tl_lc_ctrl_i;
+ assign tl_alert_handler_o = tl_s1n_29_ds_h2d[20];
+ assign tl_s1n_29_ds_d2h[20] = tl_alert_handler_i;
- assign tl_sensor_ctrl_o = tl_s1n_31_ds_h2d[21];
- assign tl_s1n_31_ds_d2h[21] = tl_sensor_ctrl_i;
+ assign tl_ast_o = tl_s1n_29_ds_h2d[21];
+ assign tl_s1n_29_ds_d2h[21] = tl_ast_i;
- assign tl_alert_handler_o = tl_s1n_31_ds_h2d[22];
- assign tl_s1n_31_ds_d2h[22] = tl_alert_handler_i;
+ assign tl_sram_ctrl_ret_aon__ram_o = tl_s1n_29_ds_h2d[22];
+ assign tl_s1n_29_ds_d2h[22] = tl_sram_ctrl_ret_aon__ram_i;
- assign tl_ast_o = tl_s1n_31_ds_h2d[23];
- assign tl_s1n_31_ds_d2h[23] = tl_ast_i;
+ assign tl_sram_ctrl_ret_aon__regs_o = tl_s1n_29_ds_h2d[23];
+ assign tl_s1n_29_ds_d2h[23] = tl_sram_ctrl_ret_aon__regs_i;
- assign tl_sram_ctrl_ret_aon__ram_o = tl_s1n_31_ds_h2d[24];
- assign tl_s1n_31_ds_d2h[24] = tl_sram_ctrl_ret_aon__ram_i;
+ assign tl_aon_timer_aon_o = tl_s1n_29_ds_h2d[24];
+ assign tl_s1n_29_ds_d2h[24] = tl_aon_timer_aon_i;
- assign tl_sram_ctrl_ret_aon__regs_o = tl_s1n_31_ds_h2d[25];
- assign tl_s1n_31_ds_d2h[25] = tl_sram_ctrl_ret_aon__regs_i;
+ assign tl_adc_ctrl_aon_o = tl_s1n_29_ds_h2d[25];
+ assign tl_s1n_29_ds_d2h[25] = tl_adc_ctrl_aon_i;
- assign tl_aon_timer_aon_o = tl_s1n_31_ds_h2d[26];
- assign tl_s1n_31_ds_d2h[26] = tl_aon_timer_aon_i;
+ assign tl_sysrst_ctrl_aon_o = tl_s1n_29_ds_h2d[26];
+ assign tl_s1n_29_ds_d2h[26] = tl_sysrst_ctrl_aon_i;
- assign tl_adc_ctrl_aon_o = tl_s1n_31_ds_h2d[27];
- assign tl_s1n_31_ds_d2h[27] = tl_adc_ctrl_aon_i;
+ assign tl_pwm_aon_o = tl_s1n_29_ds_h2d[27];
+ assign tl_s1n_29_ds_d2h[27] = tl_pwm_aon_i;
- assign tl_sysrst_ctrl_aon_o = tl_s1n_31_ds_h2d[28];
- assign tl_s1n_31_ds_d2h[28] = tl_sysrst_ctrl_aon_i;
-
- assign tl_pwm_aon_o = tl_s1n_31_ds_h2d[29];
- assign tl_s1n_31_ds_d2h[29] = tl_pwm_aon_i;
-
- assign tl_s1n_31_us_h2d = tl_main_i;
- assign tl_main_o = tl_s1n_31_us_d2h;
-
- assign tl_spi_host0_o = tl_asf_32_ds_h2d;
- assign tl_asf_32_ds_d2h = tl_spi_host0_i;
-
- assign tl_spi_host1_o = tl_asf_33_ds_h2d;
- assign tl_asf_33_ds_d2h = tl_spi_host1_i;
+ assign tl_s1n_29_us_h2d = tl_main_i;
+ assign tl_main_o = tl_s1n_29_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_31 = 5'd30;
- if ((tl_s1n_31_us_h2d.a_address &
+ dev_sel_s1n_29 = 5'd28;
+ if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin
- dev_sel_s1n_31 = 5'd0;
+ dev_sel_s1n_29 = 5'd0;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin
- dev_sel_s1n_31 = 5'd1;
+ dev_sel_s1n_29 = 5'd1;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin
- dev_sel_s1n_31 = 5'd2;
+ dev_sel_s1n_29 = 5'd2;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin
- dev_sel_s1n_31 = 5'd3;
+ dev_sel_s1n_29 = 5'd3;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin
- dev_sel_s1n_31 = 5'd4;
+ dev_sel_s1n_29 = 5'd4;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin
- dev_sel_s1n_31 = 5'd5;
+ dev_sel_s1n_29 = 5'd5;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin
- dev_sel_s1n_31 = 5'd6;
+ dev_sel_s1n_29 = 5'd6;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin
- dev_sel_s1n_31 = 5'd7;
+ dev_sel_s1n_29 = 5'd7;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
- dev_sel_s1n_31 = 5'd8;
+ dev_sel_s1n_29 = 5'd8;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
- dev_sel_s1n_31 = 5'd9;
+ dev_sel_s1n_29 = 5'd9;
- end else if ((tl_s1n_31_us_h2d.a_address &
- ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin
- dev_sel_s1n_31 = 5'd10;
-
- end else if ((tl_s1n_31_us_h2d.a_address &
- ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin
- dev_sel_s1n_31 = 5'd11;
-
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
- dev_sel_s1n_31 = 5'd12;
+ dev_sel_s1n_29 = 5'd10;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
- dev_sel_s1n_31 = 5'd13;
+ dev_sel_s1n_29 = 5'd11;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin
- dev_sel_s1n_31 = 5'd14;
+ dev_sel_s1n_29 = 5'd12;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin
- dev_sel_s1n_31 = 5'd15;
+ dev_sel_s1n_29 = 5'd13;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin
- dev_sel_s1n_31 = 5'd16;
+ dev_sel_s1n_29 = 5'd14;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin
- dev_sel_s1n_31 = 5'd17;
+ dev_sel_s1n_29 = 5'd15;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_OTP_CTRL__CORE)) == ADDR_SPACE_OTP_CTRL__CORE) begin
- dev_sel_s1n_31 = 5'd18;
+ dev_sel_s1n_29 = 5'd16;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_OTP_CTRL__PRIM)) == ADDR_SPACE_OTP_CTRL__PRIM) begin
- dev_sel_s1n_31 = 5'd19;
+ dev_sel_s1n_29 = 5'd17;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin
- dev_sel_s1n_31 = 5'd20;
+ dev_sel_s1n_29 = 5'd18;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin
- dev_sel_s1n_31 = 5'd21;
+ dev_sel_s1n_29 = 5'd19;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
- dev_sel_s1n_31 = 5'd22;
+ dev_sel_s1n_29 = 5'd20;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_AST)) == ADDR_SPACE_AST) begin
- dev_sel_s1n_31 = 5'd23;
+ dev_sel_s1n_29 = 5'd21;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == ADDR_SPACE_SRAM_CTRL_RET_AON__RAM) begin
- dev_sel_s1n_31 = 5'd24;
+ dev_sel_s1n_29 = 5'd22;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == ADDR_SPACE_SRAM_CTRL_RET_AON__REGS) begin
- dev_sel_s1n_31 = 5'd25;
+ dev_sel_s1n_29 = 5'd23;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_AON_TIMER_AON)) == ADDR_SPACE_AON_TIMER_AON) begin
- dev_sel_s1n_31 = 5'd26;
+ dev_sel_s1n_29 = 5'd24;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_ADC_CTRL_AON)) == ADDR_SPACE_ADC_CTRL_AON) begin
- dev_sel_s1n_31 = 5'd27;
+ dev_sel_s1n_29 = 5'd25;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_SYSRST_CTRL_AON)) == ADDR_SPACE_SYSRST_CTRL_AON) begin
- dev_sel_s1n_31 = 5'd28;
+ dev_sel_s1n_29 = 5'd26;
- end else if ((tl_s1n_31_us_h2d.a_address &
+ end else if ((tl_s1n_29_us_h2d.a_address &
~(ADDR_MASK_PWM_AON)) == ADDR_SPACE_PWM_AON) begin
- dev_sel_s1n_31 = 5'd29;
+ dev_sel_s1n_29 = 5'd27;
end
end
@@ -377,43 +335,17 @@
tlul_socket_1n #(
.HReqDepth (4'h0),
.HRspDepth (4'h0),
- .DReqDepth (120'h0),
- .DRspDepth (120'h0),
- .N (30)
- ) u_s1n_31 (
+ .DReqDepth (112'h0),
+ .DRspDepth (112'h0),
+ .N (28)
+ ) u_s1n_29 (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .tl_h_i (tl_s1n_31_us_h2d),
- .tl_h_o (tl_s1n_31_us_d2h),
- .tl_d_o (tl_s1n_31_ds_h2d),
- .tl_d_i (tl_s1n_31_ds_d2h),
- .dev_select_i (dev_sel_s1n_31)
- );
- tlul_fifo_async #(
- .ReqDepth (4),// At least 4 to make async work
- .RspDepth (4) // At least 4 to make async work
- ) u_asf_32 (
- .clk_h_i (clk_peri_i),
- .rst_h_ni (rst_peri_ni),
- .clk_d_i (clk_spi_host0_i),
- .rst_d_ni (rst_spi_host0_ni),
- .tl_h_i (tl_asf_32_us_h2d),
- .tl_h_o (tl_asf_32_us_d2h),
- .tl_d_o (tl_asf_32_ds_h2d),
- .tl_d_i (tl_asf_32_ds_d2h)
- );
- tlul_fifo_async #(
- .ReqDepth (4),// At least 4 to make async work
- .RspDepth (4) // At least 4 to make async work
- ) u_asf_33 (
- .clk_h_i (clk_peri_i),
- .rst_h_ni (rst_peri_ni),
- .clk_d_i (clk_spi_host1_i),
- .rst_d_ni (rst_spi_host1_ni),
- .tl_h_i (tl_asf_33_us_h2d),
- .tl_h_o (tl_asf_33_us_d2h),
- .tl_d_o (tl_asf_33_ds_h2d),
- .tl_d_i (tl_asf_33_ds_d2h)
+ .tl_h_i (tl_s1n_29_us_h2d),
+ .tl_h_o (tl_s1n_29_us_d2h),
+ .tl_d_o (tl_s1n_29_ds_h2d),
+ .tl_d_i (tl_s1n_29_ds_d2h),
+ .dev_select_i (dev_sel_s1n_29)
);
endmodule
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
index 0f1800e..25c8773 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
@@ -94,16 +94,16 @@
5'd10,
5'd10,
5'd9,
- 5'd9,
- 5'd9,
- 5'd9,
- 5'd9,
- 5'd9,
5'd8,
5'd7,
- 5'd0,
+ 5'd7,
+ 5'd7,
+ 5'd7,
+ 5'd7,
+ 5'd7,
5'd6,
5'd5,
+ 5'd0,
5'd4,
5'd3,
5'd2,
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
index 8810bf1..ecbb162 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
@@ -82,17 +82,17 @@
5'd2
5'd3
5'd4
+ 5'd0
5'd5
5'd6
- 5'd0
+ 5'd7
+ 5'd7
+ 5'd7
+ 5'd7
+ 5'd7
5'd7
5'd8
5'd9
- 5'd9
- 5'd9
- 5'd9
- 5'd9
- 5'd9
5'd10
5'd10
5'd10
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
index cd83f75..8f8fedc 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
@@ -50,16 +50,16 @@
5'd10,
5'd10,
5'd9,
- 5'd9,
- 5'd9,
- 5'd9,
- 5'd9,
- 5'd9,
5'd8,
5'd7,
- 5'd0,
+ 5'd7,
+ 5'd7,
+ 5'd7,
+ 5'd7,
+ 5'd7,
5'd6,
5'd5,
+ 5'd0,
5'd4,
5'd3,
5'd2,
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 7497f95..1ce79bd 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -19,8 +19,6 @@
// parameters for uart3
// parameters for gpio
// parameters for spi_device
- // parameters for spi_host0
- // parameters for spi_host1
// parameters for i2c0
// parameters for i2c1
// parameters for i2c2
@@ -31,6 +29,8 @@
parameter OtpCtrlMemInitFile = "",
// parameters for lc_ctrl
// parameters for alert_handler
+ // parameters for spi_host0
+ // parameters for spi_host1
// parameters for pwrmgr_aon
// parameters for rstmgr_aon
// parameters for clkmgr_aon
@@ -225,22 +225,6 @@
logic [3:0] cio_spi_device_sd_p2d;
logic [3:0] cio_spi_device_sd_d2p;
logic [3:0] cio_spi_device_sd_en_d2p;
- // spi_host0
- logic [3:0] cio_spi_host0_sd_p2d;
- logic cio_spi_host0_sck_d2p;
- logic cio_spi_host0_sck_en_d2p;
- logic cio_spi_host0_csb_d2p;
- logic cio_spi_host0_csb_en_d2p;
- logic [3:0] cio_spi_host0_sd_d2p;
- logic [3:0] cio_spi_host0_sd_en_d2p;
- // spi_host1
- logic [3:0] cio_spi_host1_sd_p2d;
- logic cio_spi_host1_sck_d2p;
- logic cio_spi_host1_sck_en_d2p;
- logic cio_spi_host1_csb_d2p;
- logic cio_spi_host1_csb_en_d2p;
- logic [3:0] cio_spi_host1_sd_d2p;
- logic [3:0] cio_spi_host1_sd_en_d2p;
// i2c0
logic cio_i2c0_sda_p2d;
logic cio_i2c0_scl_p2d;
@@ -300,6 +284,22 @@
logic [7:0] cio_otp_ctrl_test_en_d2p;
// lc_ctrl
// alert_handler
+ // spi_host0
+ logic [3:0] cio_spi_host0_sd_p2d;
+ logic cio_spi_host0_sck_d2p;
+ logic cio_spi_host0_sck_en_d2p;
+ logic cio_spi_host0_csb_d2p;
+ logic cio_spi_host0_csb_en_d2p;
+ logic [3:0] cio_spi_host0_sd_d2p;
+ logic [3:0] cio_spi_host0_sd_en_d2p;
+ // spi_host1
+ logic [3:0] cio_spi_host1_sd_p2d;
+ logic cio_spi_host1_sck_d2p;
+ logic cio_spi_host1_sck_en_d2p;
+ logic cio_spi_host1_csb_d2p;
+ logic cio_spi_host1_csb_en_d2p;
+ logic [3:0] cio_spi_host1_sd_d2p;
+ logic [3:0] cio_spi_host1_sd_en_d2p;
// pwrmgr_aon
// rstmgr_aon
// clkmgr_aon
@@ -401,10 +401,6 @@
logic intr_spi_device_rx_overflow;
logic intr_spi_device_tx_underflow;
logic intr_spi_device_tpm_header_not_empty;
- logic intr_spi_host0_error;
- logic intr_spi_host0_spi_event;
- logic intr_spi_host1_error;
- logic intr_spi_host1_spi_event;
logic intr_i2c0_fmt_watermark;
logic intr_i2c0_rx_watermark;
logic intr_i2c0_fmt_overflow;
@@ -479,6 +475,10 @@
logic intr_alert_handler_classb;
logic intr_alert_handler_classc;
logic intr_alert_handler_classd;
+ logic intr_spi_host0_error;
+ logic intr_spi_host0_spi_event;
+ logic intr_spi_host1_error;
+ logic intr_spi_host1_spi_event;
logic intr_pwrmgr_aon_wakeup;
logic intr_sysrst_ctrl_aon_sysrst_ctrl;
logic intr_adc_ctrl_aon_debug_cable;
@@ -622,6 +622,10 @@
tlul_pkg::tl_d2h_t rom_ctrl_regs_tl_rsp;
tlul_pkg::tl_h2d_t main_tl_peri_req;
tlul_pkg::tl_d2h_t main_tl_peri_rsp;
+ tlul_pkg::tl_h2d_t spi_host0_tl_req;
+ tlul_pkg::tl_d2h_t spi_host0_tl_rsp;
+ tlul_pkg::tl_h2d_t spi_host1_tl_req;
+ tlul_pkg::tl_d2h_t spi_host1_tl_rsp;
tlul_pkg::tl_h2d_t flash_ctrl_core_tl_req;
tlul_pkg::tl_d2h_t flash_ctrl_core_tl_rsp;
tlul_pkg::tl_h2d_t flash_ctrl_prim_tl_req;
@@ -676,10 +680,6 @@
tlul_pkg::tl_d2h_t gpio_tl_rsp;
tlul_pkg::tl_h2d_t spi_device_tl_req;
tlul_pkg::tl_d2h_t spi_device_tl_rsp;
- tlul_pkg::tl_h2d_t spi_host0_tl_req;
- tlul_pkg::tl_d2h_t spi_host0_tl_rsp;
- tlul_pkg::tl_h2d_t spi_host1_tl_req;
- tlul_pkg::tl_d2h_t spi_host1_tl_rsp;
tlul_pkg::tl_h2d_t rv_timer_tl_req;
tlul_pkg::tl_d2h_t rv_timer_tl_rsp;
tlul_pkg::tl_h2d_t usbdev_tl_req;
@@ -816,30 +816,30 @@
// peri_spi_device_0
assign lpg_cg_en[1] = clkmgr_aon_cg_en.io_div4_peri;
assign lpg_rst_en[1] = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::Domain0Sel];
- // peri_spi_host0_0
- assign lpg_cg_en[2] = clkmgr_aon_cg_en.io_peri;
- assign lpg_rst_en[2] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel];
- // peri_spi_host1_0
- assign lpg_cg_en[3] = clkmgr_aon_cg_en.io_div2_peri;
- assign lpg_rst_en[3] = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::Domain0Sel];
// peri_i2c0_0
- assign lpg_cg_en[4] = clkmgr_aon_cg_en.io_div4_peri;
- assign lpg_rst_en[4] = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::Domain0Sel];
+ assign lpg_cg_en[2] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[2] = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::Domain0Sel];
// peri_i2c1_0
- assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_peri;
- assign lpg_rst_en[5] = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::Domain0Sel];
+ assign lpg_cg_en[3] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[3] = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::Domain0Sel];
// peri_i2c2_0
- assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_peri;
- assign lpg_rst_en[6] = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::Domain0Sel];
+ assign lpg_cg_en[4] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[4] = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::Domain0Sel];
// timers_sys_io_div4_0
- assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_div4_timers;
- assign lpg_rst_en[7] = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel];
+ assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_timers;
+ assign lpg_rst_en[5] = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel];
// peri_usb_0
- assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_div4_peri;
- assign lpg_rst_en[8] = rstmgr_aon_rst_en.usb[rstmgr_pkg::Domain0Sel];
+ assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[6] = rstmgr_aon_rst_en.usb[rstmgr_pkg::Domain0Sel];
// secure_lc_io_div4_0
- assign lpg_cg_en[9] = clkmgr_aon_cg_en.io_div4_secure;
- assign lpg_rst_en[9] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
+ assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_div4_secure;
+ assign lpg_rst_en[7] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
+ // peri_spi_host0_0
+ assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_peri;
+ assign lpg_rst_en[8] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel];
+ // peri_spi_host1_0
+ assign lpg_cg_en[9] = clkmgr_aon_cg_en.io_div2_peri;
+ assign lpg_rst_en[9] = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::Domain0Sel];
// powerup_por_io_div4_Aon
assign lpg_cg_en[10] = clkmgr_aon_cg_en.io_div4_powerup;
assign lpg_rst_en[10] = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::DomainAonSel];
@@ -1169,72 +1169,8 @@
.scan_clk_i (clkmgr_aon_clocks.clk_io_div2_peri),
.rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel])
);
- spi_host #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[6:6])
- ) u_spi_host0 (
-
- // Input
- .cio_sd_i (cio_spi_host0_sd_p2d),
-
- // Output
- .cio_sck_o (cio_spi_host0_sck_d2p),
- .cio_sck_en_o (cio_spi_host0_sck_en_d2p),
- .cio_csb_o (cio_spi_host0_csb_d2p),
- .cio_csb_en_o (cio_spi_host0_csb_en_d2p),
- .cio_sd_o (cio_spi_host0_sd_d2p),
- .cio_sd_en_o (cio_spi_host0_sd_en_d2p),
-
- // Interrupt
- .intr_error_o (intr_spi_host0_error),
- .intr_spi_event_o (intr_spi_host0_spi_event),
- // [6]: fatal_fault
- .alert_tx_o ( alert_tx[6:6] ),
- .alert_rx_i ( alert_rx[6:6] ),
-
- // Inter-module signals
- .passthrough_i(spi_device_passthrough_req),
- .passthrough_o(spi_device_passthrough_rsp),
- .tl_i(spi_host0_tl_req),
- .tl_o(spi_host0_tl_rsp),
-
- // Clock and reset connections
- .clk_i (clkmgr_aon_clocks.clk_io_peri),
- .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel])
- );
- spi_host #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[7:7])
- ) u_spi_host1 (
-
- // Input
- .cio_sd_i (cio_spi_host1_sd_p2d),
-
- // Output
- .cio_sck_o (cio_spi_host1_sck_d2p),
- .cio_sck_en_o (cio_spi_host1_sck_en_d2p),
- .cio_csb_o (cio_spi_host1_csb_d2p),
- .cio_csb_en_o (cio_spi_host1_csb_en_d2p),
- .cio_sd_o (cio_spi_host1_sd_d2p),
- .cio_sd_en_o (cio_spi_host1_sd_en_d2p),
-
- // Interrupt
- .intr_error_o (intr_spi_host1_error),
- .intr_spi_event_o (intr_spi_host1_spi_event),
- // [7]: fatal_fault
- .alert_tx_o ( alert_tx[7:7] ),
- .alert_rx_i ( alert_rx[7:7] ),
-
- // Inter-module signals
- .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
- .passthrough_o(),
- .tl_i(spi_host1_tl_req),
- .tl_o(spi_host1_tl_rsp),
-
- // Clock and reset connections
- .clk_i (clkmgr_aon_clocks.clk_io_div2_peri),
- .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel])
- );
i2c #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:8])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[6:6])
) u_i2c0 (
// Input
@@ -1264,9 +1200,9 @@
.intr_acq_overflow_o (intr_i2c0_acq_overflow),
.intr_ack_stop_o (intr_i2c0_ack_stop),
.intr_host_timeout_o (intr_i2c0_host_timeout),
- // [8]: fatal_fault
- .alert_tx_o ( alert_tx[8:8] ),
- .alert_rx_i ( alert_rx[8:8] ),
+ // [6]: fatal_fault
+ .alert_tx_o ( alert_tx[6:6] ),
+ .alert_rx_i ( alert_rx[6:6] ),
// Inter-module signals
.tl_i(i2c0_tl_req),
@@ -1277,7 +1213,7 @@
.rst_ni (rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel])
);
i2c #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:9])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[7:7])
) u_i2c1 (
// Input
@@ -1307,9 +1243,9 @@
.intr_acq_overflow_o (intr_i2c1_acq_overflow),
.intr_ack_stop_o (intr_i2c1_ack_stop),
.intr_host_timeout_o (intr_i2c1_host_timeout),
- // [9]: fatal_fault
- .alert_tx_o ( alert_tx[9:9] ),
- .alert_rx_i ( alert_rx[9:9] ),
+ // [7]: fatal_fault
+ .alert_tx_o ( alert_tx[7:7] ),
+ .alert_rx_i ( alert_rx[7:7] ),
// Inter-module signals
.tl_i(i2c1_tl_req),
@@ -1320,7 +1256,7 @@
.rst_ni (rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel])
);
i2c #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:8])
) u_i2c2 (
// Input
@@ -1350,9 +1286,9 @@
.intr_acq_overflow_o (intr_i2c2_acq_overflow),
.intr_ack_stop_o (intr_i2c2_ack_stop),
.intr_host_timeout_o (intr_i2c2_host_timeout),
- // [10]: fatal_fault
- .alert_tx_o ( alert_tx[10:10] ),
- .alert_rx_i ( alert_rx[10:10] ),
+ // [8]: fatal_fault
+ .alert_tx_o ( alert_tx[8:8] ),
+ .alert_rx_i ( alert_rx[8:8] ),
// Inter-module signals
.tl_i(i2c2_tl_req),
@@ -1363,7 +1299,7 @@
.rst_ni (rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel])
);
pattgen #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[11:11])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:9])
) u_pattgen (
// Output
@@ -1379,9 +1315,9 @@
// Interrupt
.intr_done_ch0_o (intr_pattgen_done_ch0),
.intr_done_ch1_o (intr_pattgen_done_ch1),
- // [11]: fatal_fault
- .alert_tx_o ( alert_tx[11:11] ),
- .alert_rx_i ( alert_rx[11:11] ),
+ // [9]: fatal_fault
+ .alert_tx_o ( alert_tx[9:9] ),
+ .alert_rx_i ( alert_rx[9:9] ),
// Inter-module signals
.tl_i(pattgen_tl_req),
@@ -1392,14 +1328,14 @@
.rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
rv_timer #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[12:12])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10])
) u_rv_timer (
// Interrupt
.intr_timer_expired_hart0_timer0_o (intr_rv_timer_timer_expired_hart0_timer0),
- // [12]: fatal_fault
- .alert_tx_o ( alert_tx[12:12] ),
- .alert_rx_i ( alert_rx[12:12] ),
+ // [10]: fatal_fault
+ .alert_tx_o ( alert_tx[10:10] ),
+ .alert_rx_i ( alert_rx[10:10] ),
// Inter-module signals
.tl_i(rv_timer_tl_req),
@@ -1410,7 +1346,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
usbdev #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[13:13])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[11:11])
) u_usbdev (
// Input
@@ -1457,9 +1393,9 @@
.intr_frame_o (intr_usbdev_frame),
.intr_connected_o (intr_usbdev_connected),
.intr_link_out_err_o (intr_usbdev_link_out_err),
- // [13]: fatal_fault
- .alert_tx_o ( alert_tx[13:13] ),
- .alert_rx_i ( alert_rx[13:13] ),
+ // [11]: fatal_fault
+ .alert_tx_o ( alert_tx[11:11] ),
+ .alert_rx_i ( alert_rx[11:11] ),
// Inter-module signals
.usb_ref_val_o(usbdev_usb_ref_val_o),
@@ -1482,7 +1418,7 @@
.rst_usb_48mhz_ni (rstmgr_aon_resets.rst_usbif_n[rstmgr_pkg::Domain0Sel])
);
otp_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[16:14]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[14:12]),
.MemInitFile(OtpCtrlMemInitFile),
.RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
.RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm)
@@ -1495,11 +1431,11 @@
// Interrupt
.intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
.intr_otp_error_o (intr_otp_ctrl_otp_error),
- // [14]: fatal_macro_error
- // [15]: fatal_check_error
- // [16]: fatal_bus_integ_error
- .alert_tx_o ( alert_tx[16:14] ),
- .alert_rx_i ( alert_rx[16:14] ),
+ // [12]: fatal_macro_error
+ // [13]: fatal_check_error
+ // [14]: fatal_bus_integ_error
+ .alert_tx_o ( alert_tx[14:12] ),
+ .alert_rx_i ( alert_rx[14:12] ),
// Inter-module signals
.otp_ext_voltage_h_io(otp_ext_voltage_h_io),
@@ -1543,16 +1479,16 @@
.rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
lc_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:17]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[17:15]),
.RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
.RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma),
.RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction)
) u_lc_ctrl (
- // [17]: fatal_prog_error
- // [18]: fatal_state_error
- // [19]: fatal_bus_integ_error
- .alert_tx_o ( alert_tx[19:17] ),
- .alert_rx_i ( alert_rx[19:17] ),
+ // [15]: fatal_prog_error
+ // [16]: fatal_state_error
+ // [17]: fatal_bus_integ_error
+ .alert_tx_o ( alert_tx[17:15] ),
+ .alert_rx_i ( alert_rx[17:15] ),
// Inter-module signals
.jtag_i(pinmux_aon_lc_jtag_req),
@@ -1635,6 +1571,70 @@
.rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
.rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
+ spi_host #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:18])
+ ) u_spi_host0 (
+
+ // Input
+ .cio_sd_i (cio_spi_host0_sd_p2d),
+
+ // Output
+ .cio_sck_o (cio_spi_host0_sck_d2p),
+ .cio_sck_en_o (cio_spi_host0_sck_en_d2p),
+ .cio_csb_o (cio_spi_host0_csb_d2p),
+ .cio_csb_en_o (cio_spi_host0_csb_en_d2p),
+ .cio_sd_o (cio_spi_host0_sd_d2p),
+ .cio_sd_en_o (cio_spi_host0_sd_en_d2p),
+
+ // Interrupt
+ .intr_error_o (intr_spi_host0_error),
+ .intr_spi_event_o (intr_spi_host0_spi_event),
+ // [18]: fatal_fault
+ .alert_tx_o ( alert_tx[18:18] ),
+ .alert_rx_i ( alert_rx[18:18] ),
+
+ // Inter-module signals
+ .passthrough_i(spi_device_passthrough_req),
+ .passthrough_o(spi_device_passthrough_rsp),
+ .tl_i(spi_host0_tl_req),
+ .tl_o(spi_host0_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_peri),
+ .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel])
+ );
+ spi_host #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19])
+ ) u_spi_host1 (
+
+ // Input
+ .cio_sd_i (cio_spi_host1_sd_p2d),
+
+ // Output
+ .cio_sck_o (cio_spi_host1_sck_d2p),
+ .cio_sck_en_o (cio_spi_host1_sck_en_d2p),
+ .cio_csb_o (cio_spi_host1_csb_d2p),
+ .cio_csb_en_o (cio_spi_host1_csb_en_d2p),
+ .cio_sd_o (cio_spi_host1_sd_d2p),
+ .cio_sd_en_o (cio_spi_host1_sd_en_d2p),
+
+ // Interrupt
+ .intr_error_o (intr_spi_host1_error),
+ .intr_spi_event_o (intr_spi_host1_spi_event),
+ // [19]: fatal_fault
+ .alert_tx_o ( alert_tx[19:19] ),
+ .alert_rx_i ( alert_rx[19:19] ),
+
+ // Inter-module signals
+ .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
+ .passthrough_o(),
+ .tl_i(spi_host1_tl_req),
+ .tl_o(spi_host1_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div2_peri),
+ .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel])
+ );
pwrmgr #(
.AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20])
) u_pwrmgr_aon (
@@ -2549,84 +2549,84 @@
intr_adc_ctrl_aon_debug_cable, // IDs [152 +: 1]
intr_sysrst_ctrl_aon_sysrst_ctrl, // IDs [151 +: 1]
intr_pwrmgr_aon_wakeup, // IDs [150 +: 1]
- intr_alert_handler_classd, // IDs [149 +: 1]
- intr_alert_handler_classc, // IDs [148 +: 1]
- intr_alert_handler_classb, // IDs [147 +: 1]
- intr_alert_handler_classa, // IDs [146 +: 1]
- intr_otp_ctrl_otp_error, // IDs [145 +: 1]
- intr_otp_ctrl_otp_operation_done, // IDs [144 +: 1]
- intr_usbdev_link_out_err, // IDs [143 +: 1]
- intr_usbdev_connected, // IDs [142 +: 1]
- intr_usbdev_frame, // IDs [141 +: 1]
- intr_usbdev_rx_bitstuff_err, // IDs [140 +: 1]
- intr_usbdev_rx_pid_err, // IDs [139 +: 1]
- intr_usbdev_rx_crc_err, // IDs [138 +: 1]
- intr_usbdev_link_in_err, // IDs [137 +: 1]
- intr_usbdev_av_overflow, // IDs [136 +: 1]
- intr_usbdev_rx_full, // IDs [135 +: 1]
- intr_usbdev_av_empty, // IDs [134 +: 1]
- intr_usbdev_link_resume, // IDs [133 +: 1]
- intr_usbdev_link_suspend, // IDs [132 +: 1]
- intr_usbdev_link_reset, // IDs [131 +: 1]
- intr_usbdev_host_lost, // IDs [130 +: 1]
- intr_usbdev_disconnected, // IDs [129 +: 1]
- intr_usbdev_pkt_sent, // IDs [128 +: 1]
- intr_usbdev_pkt_received, // IDs [127 +: 1]
- intr_rv_timer_timer_expired_hart0_timer0, // IDs [126 +: 1]
- intr_pattgen_done_ch1, // IDs [125 +: 1]
- intr_pattgen_done_ch0, // IDs [124 +: 1]
- intr_i2c2_host_timeout, // IDs [123 +: 1]
- intr_i2c2_ack_stop, // IDs [122 +: 1]
- intr_i2c2_acq_overflow, // IDs [121 +: 1]
- intr_i2c2_tx_overflow, // IDs [120 +: 1]
- intr_i2c2_tx_nonempty, // IDs [119 +: 1]
- intr_i2c2_tx_empty, // IDs [118 +: 1]
- intr_i2c2_trans_complete, // IDs [117 +: 1]
- intr_i2c2_sda_unstable, // IDs [116 +: 1]
- intr_i2c2_stretch_timeout, // IDs [115 +: 1]
- intr_i2c2_sda_interference, // IDs [114 +: 1]
- intr_i2c2_scl_interference, // IDs [113 +: 1]
- intr_i2c2_nak, // IDs [112 +: 1]
- intr_i2c2_rx_overflow, // IDs [111 +: 1]
- intr_i2c2_fmt_overflow, // IDs [110 +: 1]
- intr_i2c2_rx_watermark, // IDs [109 +: 1]
- intr_i2c2_fmt_watermark, // IDs [108 +: 1]
- intr_i2c1_host_timeout, // IDs [107 +: 1]
- intr_i2c1_ack_stop, // IDs [106 +: 1]
- intr_i2c1_acq_overflow, // IDs [105 +: 1]
- intr_i2c1_tx_overflow, // IDs [104 +: 1]
- intr_i2c1_tx_nonempty, // IDs [103 +: 1]
- intr_i2c1_tx_empty, // IDs [102 +: 1]
- intr_i2c1_trans_complete, // IDs [101 +: 1]
- intr_i2c1_sda_unstable, // IDs [100 +: 1]
- intr_i2c1_stretch_timeout, // IDs [99 +: 1]
- intr_i2c1_sda_interference, // IDs [98 +: 1]
- intr_i2c1_scl_interference, // IDs [97 +: 1]
- intr_i2c1_nak, // IDs [96 +: 1]
- intr_i2c1_rx_overflow, // IDs [95 +: 1]
- intr_i2c1_fmt_overflow, // IDs [94 +: 1]
- intr_i2c1_rx_watermark, // IDs [93 +: 1]
- intr_i2c1_fmt_watermark, // IDs [92 +: 1]
- intr_i2c0_host_timeout, // IDs [91 +: 1]
- intr_i2c0_ack_stop, // IDs [90 +: 1]
- intr_i2c0_acq_overflow, // IDs [89 +: 1]
- intr_i2c0_tx_overflow, // IDs [88 +: 1]
- intr_i2c0_tx_nonempty, // IDs [87 +: 1]
- intr_i2c0_tx_empty, // IDs [86 +: 1]
- intr_i2c0_trans_complete, // IDs [85 +: 1]
- intr_i2c0_sda_unstable, // IDs [84 +: 1]
- intr_i2c0_stretch_timeout, // IDs [83 +: 1]
- intr_i2c0_sda_interference, // IDs [82 +: 1]
- intr_i2c0_scl_interference, // IDs [81 +: 1]
- intr_i2c0_nak, // IDs [80 +: 1]
- intr_i2c0_rx_overflow, // IDs [79 +: 1]
- intr_i2c0_fmt_overflow, // IDs [78 +: 1]
- intr_i2c0_rx_watermark, // IDs [77 +: 1]
- intr_i2c0_fmt_watermark, // IDs [76 +: 1]
- intr_spi_host1_spi_event, // IDs [75 +: 1]
- intr_spi_host1_error, // IDs [74 +: 1]
- intr_spi_host0_spi_event, // IDs [73 +: 1]
- intr_spi_host0_error, // IDs [72 +: 1]
+ intr_spi_host1_spi_event, // IDs [149 +: 1]
+ intr_spi_host1_error, // IDs [148 +: 1]
+ intr_spi_host0_spi_event, // IDs [147 +: 1]
+ intr_spi_host0_error, // IDs [146 +: 1]
+ intr_alert_handler_classd, // IDs [145 +: 1]
+ intr_alert_handler_classc, // IDs [144 +: 1]
+ intr_alert_handler_classb, // IDs [143 +: 1]
+ intr_alert_handler_classa, // IDs [142 +: 1]
+ intr_otp_ctrl_otp_error, // IDs [141 +: 1]
+ intr_otp_ctrl_otp_operation_done, // IDs [140 +: 1]
+ intr_usbdev_link_out_err, // IDs [139 +: 1]
+ intr_usbdev_connected, // IDs [138 +: 1]
+ intr_usbdev_frame, // IDs [137 +: 1]
+ intr_usbdev_rx_bitstuff_err, // IDs [136 +: 1]
+ intr_usbdev_rx_pid_err, // IDs [135 +: 1]
+ intr_usbdev_rx_crc_err, // IDs [134 +: 1]
+ intr_usbdev_link_in_err, // IDs [133 +: 1]
+ intr_usbdev_av_overflow, // IDs [132 +: 1]
+ intr_usbdev_rx_full, // IDs [131 +: 1]
+ intr_usbdev_av_empty, // IDs [130 +: 1]
+ intr_usbdev_link_resume, // IDs [129 +: 1]
+ intr_usbdev_link_suspend, // IDs [128 +: 1]
+ intr_usbdev_link_reset, // IDs [127 +: 1]
+ intr_usbdev_host_lost, // IDs [126 +: 1]
+ intr_usbdev_disconnected, // IDs [125 +: 1]
+ intr_usbdev_pkt_sent, // IDs [124 +: 1]
+ intr_usbdev_pkt_received, // IDs [123 +: 1]
+ intr_rv_timer_timer_expired_hart0_timer0, // IDs [122 +: 1]
+ intr_pattgen_done_ch1, // IDs [121 +: 1]
+ intr_pattgen_done_ch0, // IDs [120 +: 1]
+ intr_i2c2_host_timeout, // IDs [119 +: 1]
+ intr_i2c2_ack_stop, // IDs [118 +: 1]
+ intr_i2c2_acq_overflow, // IDs [117 +: 1]
+ intr_i2c2_tx_overflow, // IDs [116 +: 1]
+ intr_i2c2_tx_nonempty, // IDs [115 +: 1]
+ intr_i2c2_tx_empty, // IDs [114 +: 1]
+ intr_i2c2_trans_complete, // IDs [113 +: 1]
+ intr_i2c2_sda_unstable, // IDs [112 +: 1]
+ intr_i2c2_stretch_timeout, // IDs [111 +: 1]
+ intr_i2c2_sda_interference, // IDs [110 +: 1]
+ intr_i2c2_scl_interference, // IDs [109 +: 1]
+ intr_i2c2_nak, // IDs [108 +: 1]
+ intr_i2c2_rx_overflow, // IDs [107 +: 1]
+ intr_i2c2_fmt_overflow, // IDs [106 +: 1]
+ intr_i2c2_rx_watermark, // IDs [105 +: 1]
+ intr_i2c2_fmt_watermark, // IDs [104 +: 1]
+ intr_i2c1_host_timeout, // IDs [103 +: 1]
+ intr_i2c1_ack_stop, // IDs [102 +: 1]
+ intr_i2c1_acq_overflow, // IDs [101 +: 1]
+ intr_i2c1_tx_overflow, // IDs [100 +: 1]
+ intr_i2c1_tx_nonempty, // IDs [99 +: 1]
+ intr_i2c1_tx_empty, // IDs [98 +: 1]
+ intr_i2c1_trans_complete, // IDs [97 +: 1]
+ intr_i2c1_sda_unstable, // IDs [96 +: 1]
+ intr_i2c1_stretch_timeout, // IDs [95 +: 1]
+ intr_i2c1_sda_interference, // IDs [94 +: 1]
+ intr_i2c1_scl_interference, // IDs [93 +: 1]
+ intr_i2c1_nak, // IDs [92 +: 1]
+ intr_i2c1_rx_overflow, // IDs [91 +: 1]
+ intr_i2c1_fmt_overflow, // IDs [90 +: 1]
+ intr_i2c1_rx_watermark, // IDs [89 +: 1]
+ intr_i2c1_fmt_watermark, // IDs [88 +: 1]
+ intr_i2c0_host_timeout, // IDs [87 +: 1]
+ intr_i2c0_ack_stop, // IDs [86 +: 1]
+ intr_i2c0_acq_overflow, // IDs [85 +: 1]
+ intr_i2c0_tx_overflow, // IDs [84 +: 1]
+ intr_i2c0_tx_nonempty, // IDs [83 +: 1]
+ intr_i2c0_tx_empty, // IDs [82 +: 1]
+ intr_i2c0_trans_complete, // IDs [81 +: 1]
+ intr_i2c0_sda_unstable, // IDs [80 +: 1]
+ intr_i2c0_stretch_timeout, // IDs [79 +: 1]
+ intr_i2c0_sda_interference, // IDs [78 +: 1]
+ intr_i2c0_scl_interference, // IDs [77 +: 1]
+ intr_i2c0_nak, // IDs [76 +: 1]
+ intr_i2c0_rx_overflow, // IDs [75 +: 1]
+ intr_i2c0_fmt_overflow, // IDs [74 +: 1]
+ intr_i2c0_rx_watermark, // IDs [73 +: 1]
+ intr_i2c0_fmt_watermark, // IDs [72 +: 1]
intr_spi_device_tpm_header_not_empty, // IDs [71 +: 1]
intr_spi_device_tx_underflow, // IDs [70 +: 1]
intr_spi_device_rx_overflow, // IDs [69 +: 1]
@@ -2674,8 +2674,12 @@
xbar_main u_xbar_main (
.clk_main_i (clkmgr_aon_clocks.clk_main_infra),
.clk_fixed_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .clk_spi_host0_i (clkmgr_aon_clocks.clk_io_infra),
+ .clk_spi_host1_i (clkmgr_aon_clocks.clk_io_div2_infra),
.rst_main_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
.rst_fixed_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_spi_host0_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]),
+ .rst_spi_host1_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]),
// port: tl_rv_core_ibex__corei
.tl_rv_core_ibex__corei_i(main_tl_rv_core_ibex__corei_req),
@@ -2709,6 +2713,14 @@
.tl_peri_o(main_tl_peri_req),
.tl_peri_i(main_tl_peri_rsp),
+ // port: tl_spi_host0
+ .tl_spi_host0_o(spi_host0_tl_req),
+ .tl_spi_host0_i(spi_host0_tl_rsp),
+
+ // port: tl_spi_host1
+ .tl_spi_host1_o(spi_host1_tl_req),
+ .tl_spi_host1_i(spi_host1_tl_rsp),
+
// port: tl_flash_ctrl__core
.tl_flash_ctrl__core_o(flash_ctrl_core_tl_req),
.tl_flash_ctrl__core_i(flash_ctrl_core_tl_rsp),
@@ -2778,11 +2790,7 @@
);
xbar_peri u_xbar_peri (
.clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra),
- .clk_spi_host0_i (clkmgr_aon_clocks.clk_io_infra),
- .clk_spi_host1_i (clkmgr_aon_clocks.clk_io_div2_infra),
.rst_peri_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
- .rst_spi_host0_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]),
- .rst_spi_host1_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]),
// port: tl_main
.tl_main_i(main_tl_peri_req),
@@ -2832,14 +2840,6 @@
.tl_spi_device_o(spi_device_tl_req),
.tl_spi_device_i(spi_device_tl_rsp),
- // port: tl_spi_host0
- .tl_spi_host0_o(spi_host0_tl_req),
- .tl_spi_host0_i(spi_host0_tl_rsp),
-
- // port: tl_spi_host1
- .tl_spi_host1_o(spi_host1_tl_req),
- .tl_spi_host1_i(spi_host1_tl_rsp),
-
// port: tl_rv_timer
.tl_rv_timer_o(rv_timer_tl_req),
.tl_rv_timer_i(rv_timer_tl_rsp),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index d6297c7..2385491 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -71,26 +71,6 @@
parameter int unsigned TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES = 32'h2000;
/**
- * Peripheral base address for spi_host0 in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_SPI_HOST0_BASE_ADDR = 32'h40060000;
-
- /**
- * Peripheral size in bytes for spi_host0 in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_SPI_HOST0_SIZE_BYTES = 32'h1000;
-
- /**
- * Peripheral base address for spi_host1 in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_SPI_HOST1_BASE_ADDR = 32'h40070000;
-
- /**
- * Peripheral size in bytes for spi_host1 in top earlgrey.
- */
- parameter int unsigned TOP_EARLGREY_SPI_HOST1_SIZE_BYTES = 32'h1000;
-
- /**
* Peripheral base address for i2c0 in top earlgrey.
*/
parameter int unsigned TOP_EARLGREY_I2C0_BASE_ADDR = 32'h40080000;
@@ -191,6 +171,26 @@
parameter int unsigned TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES = 32'h1000;
/**
+ * Peripheral base address for spi_host0 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_SPI_HOST0_BASE_ADDR = 32'h40300000;
+
+ /**
+ * Peripheral size in bytes for spi_host0 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_SPI_HOST0_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for spi_host1 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_SPI_HOST1_BASE_ADDR = 32'h40310000;
+
+ /**
+ * Peripheral size in bytes for spi_host1 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_SPI_HOST1_SIZE_BYTES = 32'h1000;
+
+ /**
* Peripheral base address for pwrmgr_aon in top earlgrey.
*/
parameter int unsigned TOP_EARLGREY_PWRMGR_AON_BASE_ADDR = 32'h40400000;
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index dfc013f..41a4e06 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -84,10 +84,6 @@
[kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow] = kTopEarlgreyPlicPeripheralSpiDevice,
[kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow] = kTopEarlgreyPlicPeripheralSpiDevice,
[kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty] = kTopEarlgreyPlicPeripheralSpiDevice,
- [kTopEarlgreyPlicIrqIdSpiHost0Error] = kTopEarlgreyPlicPeripheralSpiHost0,
- [kTopEarlgreyPlicIrqIdSpiHost0SpiEvent] = kTopEarlgreyPlicPeripheralSpiHost0,
- [kTopEarlgreyPlicIrqIdSpiHost1Error] = kTopEarlgreyPlicPeripheralSpiHost1,
- [kTopEarlgreyPlicIrqIdSpiHost1SpiEvent] = kTopEarlgreyPlicPeripheralSpiHost1,
[kTopEarlgreyPlicIrqIdI2c0FmtWatermark] = kTopEarlgreyPlicPeripheralI2c0,
[kTopEarlgreyPlicIrqIdI2c0RxWatermark] = kTopEarlgreyPlicPeripheralI2c0,
[kTopEarlgreyPlicIrqIdI2c0FmtOverflow] = kTopEarlgreyPlicPeripheralI2c0,
@@ -162,6 +158,10 @@
[kTopEarlgreyPlicIrqIdAlertHandlerClassb] = kTopEarlgreyPlicPeripheralAlertHandler,
[kTopEarlgreyPlicIrqIdAlertHandlerClassc] = kTopEarlgreyPlicPeripheralAlertHandler,
[kTopEarlgreyPlicIrqIdAlertHandlerClassd] = kTopEarlgreyPlicPeripheralAlertHandler,
+ [kTopEarlgreyPlicIrqIdSpiHost0Error] = kTopEarlgreyPlicPeripheralSpiHost0,
+ [kTopEarlgreyPlicIrqIdSpiHost0SpiEvent] = kTopEarlgreyPlicPeripheralSpiHost0,
+ [kTopEarlgreyPlicIrqIdSpiHost1Error] = kTopEarlgreyPlicPeripheralSpiHost1,
+ [kTopEarlgreyPlicIrqIdSpiHost1SpiEvent] = kTopEarlgreyPlicPeripheralSpiHost1,
[kTopEarlgreyPlicIrqIdPwrmgrAonWakeup] = kTopEarlgreyPlicPeripheralPwrmgrAon,
[kTopEarlgreyPlicIrqIdSysrstCtrlAonSysrstCtrl] = kTopEarlgreyPlicPeripheralSysrstCtrlAon,
[kTopEarlgreyPlicIrqIdAdcCtrlAonDebugCable] = kTopEarlgreyPlicPeripheralAdcCtrlAon,
@@ -210,8 +210,6 @@
[kTopEarlgreyAlertIdUart3FatalFault] = kTopEarlgreyAlertPeripheralUart3,
[kTopEarlgreyAlertIdGpioFatalFault] = kTopEarlgreyAlertPeripheralGpio,
[kTopEarlgreyAlertIdSpiDeviceFatalFault] = kTopEarlgreyAlertPeripheralSpiDevice,
- [kTopEarlgreyAlertIdSpiHost0FatalFault] = kTopEarlgreyAlertPeripheralSpiHost0,
- [kTopEarlgreyAlertIdSpiHost1FatalFault] = kTopEarlgreyAlertPeripheralSpiHost1,
[kTopEarlgreyAlertIdI2c0FatalFault] = kTopEarlgreyAlertPeripheralI2c0,
[kTopEarlgreyAlertIdI2c1FatalFault] = kTopEarlgreyAlertPeripheralI2c1,
[kTopEarlgreyAlertIdI2c2FatalFault] = kTopEarlgreyAlertPeripheralI2c2,
@@ -224,6 +222,8 @@
[kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl,
[kTopEarlgreyAlertIdLcCtrlFatalStateError] = kTopEarlgreyAlertPeripheralLcCtrl,
[kTopEarlgreyAlertIdLcCtrlFatalBusIntegError] = kTopEarlgreyAlertPeripheralLcCtrl,
+ [kTopEarlgreyAlertIdSpiHost0FatalFault] = kTopEarlgreyAlertPeripheralSpiHost0,
+ [kTopEarlgreyAlertIdSpiHost1FatalFault] = kTopEarlgreyAlertPeripheralSpiHost1,
[kTopEarlgreyAlertIdPwrmgrAonFatalFault] = kTopEarlgreyAlertPeripheralPwrmgrAon,
[kTopEarlgreyAlertIdRstmgrAonFatalFault] = kTopEarlgreyAlertPeripheralRstmgrAon,
[kTopEarlgreyAlertIdClkmgrAonRecovFault] = kTopEarlgreyAlertPeripheralClkmgrAon,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 9f1f71b..ff5cd44 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -134,42 +134,6 @@
#define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x2000u
/**
- * Peripheral base address for spi_host0 in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40060000u
-
-/**
- * Peripheral size for spi_host0 in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_SPI_HOST0_BASE_ADDR and
- * `TOP_EARLGREY_SPI_HOST0_BASE_ADDR + TOP_EARLGREY_SPI_HOST0_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x1000u
-
-/**
- * Peripheral base address for spi_host1 in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40070000u
-
-/**
- * Peripheral size for spi_host1 in top earlgrey.
- *
- * This is the size (in bytes) of the peripheral's reserved memory area. All
- * memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_SPI_HOST1_BASE_ADDR and
- * `TOP_EARLGREY_SPI_HOST1_BASE_ADDR + TOP_EARLGREY_SPI_HOST1_SIZE_BYTES`.
- */
-#define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x1000u
-
-/**
* Peripheral base address for i2c0 in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -350,6 +314,42 @@
#define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x1000u
/**
+ * Peripheral base address for spi_host0 in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40300000u
+
+/**
+ * Peripheral size for spi_host0 in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_SPI_HOST0_BASE_ADDR and
+ * `TOP_EARLGREY_SPI_HOST0_BASE_ADDR + TOP_EARLGREY_SPI_HOST0_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for spi_host1 in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40310000u
+
+/**
+ * Peripheral size for spi_host1 in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_SPI_HOST1_BASE_ADDR and
+ * `TOP_EARLGREY_SPI_HOST1_BASE_ADDR + TOP_EARLGREY_SPI_HOST1_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x1000u
+
+/**
* Peripheral base address for pwrmgr_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -981,16 +981,16 @@
kTopEarlgreyPlicPeripheralUart3 = 4, /**< uart3 */
kTopEarlgreyPlicPeripheralGpio = 5, /**< gpio */
kTopEarlgreyPlicPeripheralSpiDevice = 6, /**< spi_device */
- kTopEarlgreyPlicPeripheralSpiHost0 = 7, /**< spi_host0 */
- kTopEarlgreyPlicPeripheralSpiHost1 = 8, /**< spi_host1 */
- kTopEarlgreyPlicPeripheralI2c0 = 9, /**< i2c0 */
- kTopEarlgreyPlicPeripheralI2c1 = 10, /**< i2c1 */
- kTopEarlgreyPlicPeripheralI2c2 = 11, /**< i2c2 */
- kTopEarlgreyPlicPeripheralPattgen = 12, /**< pattgen */
- kTopEarlgreyPlicPeripheralRvTimer = 13, /**< rv_timer */
- kTopEarlgreyPlicPeripheralUsbdev = 14, /**< usbdev */
- kTopEarlgreyPlicPeripheralOtpCtrl = 15, /**< otp_ctrl */
- kTopEarlgreyPlicPeripheralAlertHandler = 16, /**< alert_handler */
+ kTopEarlgreyPlicPeripheralI2c0 = 7, /**< i2c0 */
+ kTopEarlgreyPlicPeripheralI2c1 = 8, /**< i2c1 */
+ kTopEarlgreyPlicPeripheralI2c2 = 9, /**< i2c2 */
+ kTopEarlgreyPlicPeripheralPattgen = 10, /**< pattgen */
+ kTopEarlgreyPlicPeripheralRvTimer = 11, /**< rv_timer */
+ kTopEarlgreyPlicPeripheralUsbdev = 12, /**< usbdev */
+ kTopEarlgreyPlicPeripheralOtpCtrl = 13, /**< otp_ctrl */
+ kTopEarlgreyPlicPeripheralAlertHandler = 14, /**< alert_handler */
+ kTopEarlgreyPlicPeripheralSpiHost0 = 15, /**< spi_host0 */
+ kTopEarlgreyPlicPeripheralSpiHost1 = 16, /**< spi_host1 */
kTopEarlgreyPlicPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
kTopEarlgreyPlicPeripheralSysrstCtrlAon = 18, /**< sysrst_ctrl_aon */
kTopEarlgreyPlicPeripheralAdcCtrlAon = 19, /**< adc_ctrl_aon */
@@ -1086,84 +1086,84 @@
kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow = 69, /**< spi_device_rx_overflow */
kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow = 70, /**< spi_device_tx_underflow */
kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 71, /**< spi_device_tpm_header_not_empty */
- kTopEarlgreyPlicIrqIdSpiHost0Error = 72, /**< spi_host0_error */
- kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 73, /**< spi_host0_spi_event */
- kTopEarlgreyPlicIrqIdSpiHost1Error = 74, /**< spi_host1_error */
- kTopEarlgreyPlicIrqIdSpiHost1SpiEvent = 75, /**< spi_host1_spi_event */
- kTopEarlgreyPlicIrqIdI2c0FmtWatermark = 76, /**< i2c0_fmt_watermark */
- kTopEarlgreyPlicIrqIdI2c0RxWatermark = 77, /**< i2c0_rx_watermark */
- kTopEarlgreyPlicIrqIdI2c0FmtOverflow = 78, /**< i2c0_fmt_overflow */
- kTopEarlgreyPlicIrqIdI2c0RxOverflow = 79, /**< i2c0_rx_overflow */
- kTopEarlgreyPlicIrqIdI2c0Nak = 80, /**< i2c0_nak */
- kTopEarlgreyPlicIrqIdI2c0SclInterference = 81, /**< i2c0_scl_interference */
- kTopEarlgreyPlicIrqIdI2c0SdaInterference = 82, /**< i2c0_sda_interference */
- kTopEarlgreyPlicIrqIdI2c0StretchTimeout = 83, /**< i2c0_stretch_timeout */
- kTopEarlgreyPlicIrqIdI2c0SdaUnstable = 84, /**< i2c0_sda_unstable */
- kTopEarlgreyPlicIrqIdI2c0TransComplete = 85, /**< i2c0_trans_complete */
- kTopEarlgreyPlicIrqIdI2c0TxEmpty = 86, /**< i2c0_tx_empty */
- kTopEarlgreyPlicIrqIdI2c0TxNonempty = 87, /**< i2c0_tx_nonempty */
- kTopEarlgreyPlicIrqIdI2c0TxOverflow = 88, /**< i2c0_tx_overflow */
- kTopEarlgreyPlicIrqIdI2c0AcqOverflow = 89, /**< i2c0_acq_overflow */
- kTopEarlgreyPlicIrqIdI2c0AckStop = 90, /**< i2c0_ack_stop */
- kTopEarlgreyPlicIrqIdI2c0HostTimeout = 91, /**< i2c0_host_timeout */
- kTopEarlgreyPlicIrqIdI2c1FmtWatermark = 92, /**< i2c1_fmt_watermark */
- kTopEarlgreyPlicIrqIdI2c1RxWatermark = 93, /**< i2c1_rx_watermark */
- kTopEarlgreyPlicIrqIdI2c1FmtOverflow = 94, /**< i2c1_fmt_overflow */
- kTopEarlgreyPlicIrqIdI2c1RxOverflow = 95, /**< i2c1_rx_overflow */
- kTopEarlgreyPlicIrqIdI2c1Nak = 96, /**< i2c1_nak */
- kTopEarlgreyPlicIrqIdI2c1SclInterference = 97, /**< i2c1_scl_interference */
- kTopEarlgreyPlicIrqIdI2c1SdaInterference = 98, /**< i2c1_sda_interference */
- kTopEarlgreyPlicIrqIdI2c1StretchTimeout = 99, /**< i2c1_stretch_timeout */
- kTopEarlgreyPlicIrqIdI2c1SdaUnstable = 100, /**< i2c1_sda_unstable */
- kTopEarlgreyPlicIrqIdI2c1TransComplete = 101, /**< i2c1_trans_complete */
- kTopEarlgreyPlicIrqIdI2c1TxEmpty = 102, /**< i2c1_tx_empty */
- kTopEarlgreyPlicIrqIdI2c1TxNonempty = 103, /**< i2c1_tx_nonempty */
- kTopEarlgreyPlicIrqIdI2c1TxOverflow = 104, /**< i2c1_tx_overflow */
- kTopEarlgreyPlicIrqIdI2c1AcqOverflow = 105, /**< i2c1_acq_overflow */
- kTopEarlgreyPlicIrqIdI2c1AckStop = 106, /**< i2c1_ack_stop */
- kTopEarlgreyPlicIrqIdI2c1HostTimeout = 107, /**< i2c1_host_timeout */
- kTopEarlgreyPlicIrqIdI2c2FmtWatermark = 108, /**< i2c2_fmt_watermark */
- kTopEarlgreyPlicIrqIdI2c2RxWatermark = 109, /**< i2c2_rx_watermark */
- kTopEarlgreyPlicIrqIdI2c2FmtOverflow = 110, /**< i2c2_fmt_overflow */
- kTopEarlgreyPlicIrqIdI2c2RxOverflow = 111, /**< i2c2_rx_overflow */
- kTopEarlgreyPlicIrqIdI2c2Nak = 112, /**< i2c2_nak */
- kTopEarlgreyPlicIrqIdI2c2SclInterference = 113, /**< i2c2_scl_interference */
- kTopEarlgreyPlicIrqIdI2c2SdaInterference = 114, /**< i2c2_sda_interference */
- kTopEarlgreyPlicIrqIdI2c2StretchTimeout = 115, /**< i2c2_stretch_timeout */
- kTopEarlgreyPlicIrqIdI2c2SdaUnstable = 116, /**< i2c2_sda_unstable */
- kTopEarlgreyPlicIrqIdI2c2TransComplete = 117, /**< i2c2_trans_complete */
- kTopEarlgreyPlicIrqIdI2c2TxEmpty = 118, /**< i2c2_tx_empty */
- kTopEarlgreyPlicIrqIdI2c2TxNonempty = 119, /**< i2c2_tx_nonempty */
- kTopEarlgreyPlicIrqIdI2c2TxOverflow = 120, /**< i2c2_tx_overflow */
- kTopEarlgreyPlicIrqIdI2c2AcqOverflow = 121, /**< i2c2_acq_overflow */
- kTopEarlgreyPlicIrqIdI2c2AckStop = 122, /**< i2c2_ack_stop */
- kTopEarlgreyPlicIrqIdI2c2HostTimeout = 123, /**< i2c2_host_timeout */
- kTopEarlgreyPlicIrqIdPattgenDoneCh0 = 124, /**< pattgen_done_ch0 */
- kTopEarlgreyPlicIrqIdPattgenDoneCh1 = 125, /**< pattgen_done_ch1 */
- kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 126, /**< rv_timer_timer_expired_hart0_timer0 */
- kTopEarlgreyPlicIrqIdUsbdevPktReceived = 127, /**< usbdev_pkt_received */
- kTopEarlgreyPlicIrqIdUsbdevPktSent = 128, /**< usbdev_pkt_sent */
- kTopEarlgreyPlicIrqIdUsbdevDisconnected = 129, /**< usbdev_disconnected */
- kTopEarlgreyPlicIrqIdUsbdevHostLost = 130, /**< usbdev_host_lost */
- kTopEarlgreyPlicIrqIdUsbdevLinkReset = 131, /**< usbdev_link_reset */
- kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 132, /**< usbdev_link_suspend */
- kTopEarlgreyPlicIrqIdUsbdevLinkResume = 133, /**< usbdev_link_resume */
- kTopEarlgreyPlicIrqIdUsbdevAvEmpty = 134, /**< usbdev_av_empty */
- kTopEarlgreyPlicIrqIdUsbdevRxFull = 135, /**< usbdev_rx_full */
- kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 136, /**< usbdev_av_overflow */
- kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 137, /**< usbdev_link_in_err */
- kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 138, /**< usbdev_rx_crc_err */
- kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 139, /**< usbdev_rx_pid_err */
- kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 140, /**< usbdev_rx_bitstuff_err */
- kTopEarlgreyPlicIrqIdUsbdevFrame = 141, /**< usbdev_frame */
- kTopEarlgreyPlicIrqIdUsbdevConnected = 142, /**< usbdev_connected */
- kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 143, /**< usbdev_link_out_err */
- kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 144, /**< otp_ctrl_otp_operation_done */
- kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 145, /**< otp_ctrl_otp_error */
- kTopEarlgreyPlicIrqIdAlertHandlerClassa = 146, /**< alert_handler_classa */
- kTopEarlgreyPlicIrqIdAlertHandlerClassb = 147, /**< alert_handler_classb */
- kTopEarlgreyPlicIrqIdAlertHandlerClassc = 148, /**< alert_handler_classc */
- kTopEarlgreyPlicIrqIdAlertHandlerClassd = 149, /**< alert_handler_classd */
+ kTopEarlgreyPlicIrqIdI2c0FmtWatermark = 72, /**< i2c0_fmt_watermark */
+ kTopEarlgreyPlicIrqIdI2c0RxWatermark = 73, /**< i2c0_rx_watermark */
+ kTopEarlgreyPlicIrqIdI2c0FmtOverflow = 74, /**< i2c0_fmt_overflow */
+ kTopEarlgreyPlicIrqIdI2c0RxOverflow = 75, /**< i2c0_rx_overflow */
+ kTopEarlgreyPlicIrqIdI2c0Nak = 76, /**< i2c0_nak */
+ kTopEarlgreyPlicIrqIdI2c0SclInterference = 77, /**< i2c0_scl_interference */
+ kTopEarlgreyPlicIrqIdI2c0SdaInterference = 78, /**< i2c0_sda_interference */
+ kTopEarlgreyPlicIrqIdI2c0StretchTimeout = 79, /**< i2c0_stretch_timeout */
+ kTopEarlgreyPlicIrqIdI2c0SdaUnstable = 80, /**< i2c0_sda_unstable */
+ kTopEarlgreyPlicIrqIdI2c0TransComplete = 81, /**< i2c0_trans_complete */
+ kTopEarlgreyPlicIrqIdI2c0TxEmpty = 82, /**< i2c0_tx_empty */
+ kTopEarlgreyPlicIrqIdI2c0TxNonempty = 83, /**< i2c0_tx_nonempty */
+ kTopEarlgreyPlicIrqIdI2c0TxOverflow = 84, /**< i2c0_tx_overflow */
+ kTopEarlgreyPlicIrqIdI2c0AcqOverflow = 85, /**< i2c0_acq_overflow */
+ kTopEarlgreyPlicIrqIdI2c0AckStop = 86, /**< i2c0_ack_stop */
+ kTopEarlgreyPlicIrqIdI2c0HostTimeout = 87, /**< i2c0_host_timeout */
+ kTopEarlgreyPlicIrqIdI2c1FmtWatermark = 88, /**< i2c1_fmt_watermark */
+ kTopEarlgreyPlicIrqIdI2c1RxWatermark = 89, /**< i2c1_rx_watermark */
+ kTopEarlgreyPlicIrqIdI2c1FmtOverflow = 90, /**< i2c1_fmt_overflow */
+ kTopEarlgreyPlicIrqIdI2c1RxOverflow = 91, /**< i2c1_rx_overflow */
+ kTopEarlgreyPlicIrqIdI2c1Nak = 92, /**< i2c1_nak */
+ kTopEarlgreyPlicIrqIdI2c1SclInterference = 93, /**< i2c1_scl_interference */
+ kTopEarlgreyPlicIrqIdI2c1SdaInterference = 94, /**< i2c1_sda_interference */
+ kTopEarlgreyPlicIrqIdI2c1StretchTimeout = 95, /**< i2c1_stretch_timeout */
+ kTopEarlgreyPlicIrqIdI2c1SdaUnstable = 96, /**< i2c1_sda_unstable */
+ kTopEarlgreyPlicIrqIdI2c1TransComplete = 97, /**< i2c1_trans_complete */
+ kTopEarlgreyPlicIrqIdI2c1TxEmpty = 98, /**< i2c1_tx_empty */
+ kTopEarlgreyPlicIrqIdI2c1TxNonempty = 99, /**< i2c1_tx_nonempty */
+ kTopEarlgreyPlicIrqIdI2c1TxOverflow = 100, /**< i2c1_tx_overflow */
+ kTopEarlgreyPlicIrqIdI2c1AcqOverflow = 101, /**< i2c1_acq_overflow */
+ kTopEarlgreyPlicIrqIdI2c1AckStop = 102, /**< i2c1_ack_stop */
+ kTopEarlgreyPlicIrqIdI2c1HostTimeout = 103, /**< i2c1_host_timeout */
+ kTopEarlgreyPlicIrqIdI2c2FmtWatermark = 104, /**< i2c2_fmt_watermark */
+ kTopEarlgreyPlicIrqIdI2c2RxWatermark = 105, /**< i2c2_rx_watermark */
+ kTopEarlgreyPlicIrqIdI2c2FmtOverflow = 106, /**< i2c2_fmt_overflow */
+ kTopEarlgreyPlicIrqIdI2c2RxOverflow = 107, /**< i2c2_rx_overflow */
+ kTopEarlgreyPlicIrqIdI2c2Nak = 108, /**< i2c2_nak */
+ kTopEarlgreyPlicIrqIdI2c2SclInterference = 109, /**< i2c2_scl_interference */
+ kTopEarlgreyPlicIrqIdI2c2SdaInterference = 110, /**< i2c2_sda_interference */
+ kTopEarlgreyPlicIrqIdI2c2StretchTimeout = 111, /**< i2c2_stretch_timeout */
+ kTopEarlgreyPlicIrqIdI2c2SdaUnstable = 112, /**< i2c2_sda_unstable */
+ kTopEarlgreyPlicIrqIdI2c2TransComplete = 113, /**< i2c2_trans_complete */
+ kTopEarlgreyPlicIrqIdI2c2TxEmpty = 114, /**< i2c2_tx_empty */
+ kTopEarlgreyPlicIrqIdI2c2TxNonempty = 115, /**< i2c2_tx_nonempty */
+ kTopEarlgreyPlicIrqIdI2c2TxOverflow = 116, /**< i2c2_tx_overflow */
+ kTopEarlgreyPlicIrqIdI2c2AcqOverflow = 117, /**< i2c2_acq_overflow */
+ kTopEarlgreyPlicIrqIdI2c2AckStop = 118, /**< i2c2_ack_stop */
+ kTopEarlgreyPlicIrqIdI2c2HostTimeout = 119, /**< i2c2_host_timeout */
+ kTopEarlgreyPlicIrqIdPattgenDoneCh0 = 120, /**< pattgen_done_ch0 */
+ kTopEarlgreyPlicIrqIdPattgenDoneCh1 = 121, /**< pattgen_done_ch1 */
+ kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 122, /**< rv_timer_timer_expired_hart0_timer0 */
+ kTopEarlgreyPlicIrqIdUsbdevPktReceived = 123, /**< usbdev_pkt_received */
+ kTopEarlgreyPlicIrqIdUsbdevPktSent = 124, /**< usbdev_pkt_sent */
+ kTopEarlgreyPlicIrqIdUsbdevDisconnected = 125, /**< usbdev_disconnected */
+ kTopEarlgreyPlicIrqIdUsbdevHostLost = 126, /**< usbdev_host_lost */
+ kTopEarlgreyPlicIrqIdUsbdevLinkReset = 127, /**< usbdev_link_reset */
+ kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 128, /**< usbdev_link_suspend */
+ kTopEarlgreyPlicIrqIdUsbdevLinkResume = 129, /**< usbdev_link_resume */
+ kTopEarlgreyPlicIrqIdUsbdevAvEmpty = 130, /**< usbdev_av_empty */
+ kTopEarlgreyPlicIrqIdUsbdevRxFull = 131, /**< usbdev_rx_full */
+ kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 132, /**< usbdev_av_overflow */
+ kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 133, /**< usbdev_link_in_err */
+ kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 134, /**< usbdev_rx_crc_err */
+ kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 135, /**< usbdev_rx_pid_err */
+ kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 136, /**< usbdev_rx_bitstuff_err */
+ kTopEarlgreyPlicIrqIdUsbdevFrame = 137, /**< usbdev_frame */
+ kTopEarlgreyPlicIrqIdUsbdevConnected = 138, /**< usbdev_connected */
+ kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 139, /**< usbdev_link_out_err */
+ kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 140, /**< otp_ctrl_otp_operation_done */
+ kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 141, /**< otp_ctrl_otp_error */
+ kTopEarlgreyPlicIrqIdAlertHandlerClassa = 142, /**< alert_handler_classa */
+ kTopEarlgreyPlicIrqIdAlertHandlerClassb = 143, /**< alert_handler_classb */
+ kTopEarlgreyPlicIrqIdAlertHandlerClassc = 144, /**< alert_handler_classc */
+ kTopEarlgreyPlicIrqIdAlertHandlerClassd = 145, /**< alert_handler_classd */
+ kTopEarlgreyPlicIrqIdSpiHost0Error = 146, /**< spi_host0_error */
+ kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 147, /**< spi_host0_spi_event */
+ kTopEarlgreyPlicIrqIdSpiHost1Error = 148, /**< spi_host1_error */
+ kTopEarlgreyPlicIrqIdSpiHost1SpiEvent = 149, /**< spi_host1_spi_event */
kTopEarlgreyPlicIrqIdPwrmgrAonWakeup = 150, /**< pwrmgr_aon_wakeup */
kTopEarlgreyPlicIrqIdSysrstCtrlAonSysrstCtrl = 151, /**< sysrst_ctrl_aon_sysrst_ctrl */
kTopEarlgreyPlicIrqIdAdcCtrlAonDebugCable = 152, /**< adc_ctrl_aon_debug_cable */
@@ -1231,16 +1231,16 @@
kTopEarlgreyAlertPeripheralUart3 = 3, /**< uart3 */
kTopEarlgreyAlertPeripheralGpio = 4, /**< gpio */
kTopEarlgreyAlertPeripheralSpiDevice = 5, /**< spi_device */
- kTopEarlgreyAlertPeripheralSpiHost0 = 6, /**< spi_host0 */
- kTopEarlgreyAlertPeripheralSpiHost1 = 7, /**< spi_host1 */
- kTopEarlgreyAlertPeripheralI2c0 = 8, /**< i2c0 */
- kTopEarlgreyAlertPeripheralI2c1 = 9, /**< i2c1 */
- kTopEarlgreyAlertPeripheralI2c2 = 10, /**< i2c2 */
- kTopEarlgreyAlertPeripheralPattgen = 11, /**< pattgen */
- kTopEarlgreyAlertPeripheralRvTimer = 12, /**< rv_timer */
- kTopEarlgreyAlertPeripheralUsbdev = 13, /**< usbdev */
- kTopEarlgreyAlertPeripheralOtpCtrl = 14, /**< otp_ctrl */
- kTopEarlgreyAlertPeripheralLcCtrl = 15, /**< lc_ctrl */
+ kTopEarlgreyAlertPeripheralI2c0 = 6, /**< i2c0 */
+ kTopEarlgreyAlertPeripheralI2c1 = 7, /**< i2c1 */
+ kTopEarlgreyAlertPeripheralI2c2 = 8, /**< i2c2 */
+ kTopEarlgreyAlertPeripheralPattgen = 9, /**< pattgen */
+ kTopEarlgreyAlertPeripheralRvTimer = 10, /**< rv_timer */
+ kTopEarlgreyAlertPeripheralUsbdev = 11, /**< usbdev */
+ kTopEarlgreyAlertPeripheralOtpCtrl = 12, /**< otp_ctrl */
+ kTopEarlgreyAlertPeripheralLcCtrl = 13, /**< lc_ctrl */
+ kTopEarlgreyAlertPeripheralSpiHost0 = 14, /**< spi_host0 */
+ kTopEarlgreyAlertPeripheralSpiHost1 = 15, /**< spi_host1 */
kTopEarlgreyAlertPeripheralPwrmgrAon = 16, /**< pwrmgr_aon */
kTopEarlgreyAlertPeripheralRstmgrAon = 17, /**< rstmgr_aon */
kTopEarlgreyAlertPeripheralClkmgrAon = 18, /**< clkmgr_aon */
@@ -1282,20 +1282,20 @@
kTopEarlgreyAlertIdUart3FatalFault = 3, /**< uart3_fatal_fault */
kTopEarlgreyAlertIdGpioFatalFault = 4, /**< gpio_fatal_fault */
kTopEarlgreyAlertIdSpiDeviceFatalFault = 5, /**< spi_device_fatal_fault */
- kTopEarlgreyAlertIdSpiHost0FatalFault = 6, /**< spi_host0_fatal_fault */
- kTopEarlgreyAlertIdSpiHost1FatalFault = 7, /**< spi_host1_fatal_fault */
- kTopEarlgreyAlertIdI2c0FatalFault = 8, /**< i2c0_fatal_fault */
- kTopEarlgreyAlertIdI2c1FatalFault = 9, /**< i2c1_fatal_fault */
- kTopEarlgreyAlertIdI2c2FatalFault = 10, /**< i2c2_fatal_fault */
- kTopEarlgreyAlertIdPattgenFatalFault = 11, /**< pattgen_fatal_fault */
- kTopEarlgreyAlertIdRvTimerFatalFault = 12, /**< rv_timer_fatal_fault */
- kTopEarlgreyAlertIdUsbdevFatalFault = 13, /**< usbdev_fatal_fault */
- kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 14, /**< otp_ctrl_fatal_macro_error */
- kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 15, /**< otp_ctrl_fatal_check_error */
- kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 16, /**< otp_ctrl_fatal_bus_integ_error */
- kTopEarlgreyAlertIdLcCtrlFatalProgError = 17, /**< lc_ctrl_fatal_prog_error */
- kTopEarlgreyAlertIdLcCtrlFatalStateError = 18, /**< lc_ctrl_fatal_state_error */
- kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 19, /**< lc_ctrl_fatal_bus_integ_error */
+ kTopEarlgreyAlertIdI2c0FatalFault = 6, /**< i2c0_fatal_fault */
+ kTopEarlgreyAlertIdI2c1FatalFault = 7, /**< i2c1_fatal_fault */
+ kTopEarlgreyAlertIdI2c2FatalFault = 8, /**< i2c2_fatal_fault */
+ kTopEarlgreyAlertIdPattgenFatalFault = 9, /**< pattgen_fatal_fault */
+ kTopEarlgreyAlertIdRvTimerFatalFault = 10, /**< rv_timer_fatal_fault */
+ kTopEarlgreyAlertIdUsbdevFatalFault = 11, /**< usbdev_fatal_fault */
+ kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 12, /**< otp_ctrl_fatal_macro_error */
+ kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 13, /**< otp_ctrl_fatal_check_error */
+ kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 14, /**< otp_ctrl_fatal_bus_integ_error */
+ kTopEarlgreyAlertIdLcCtrlFatalProgError = 15, /**< lc_ctrl_fatal_prog_error */
+ kTopEarlgreyAlertIdLcCtrlFatalStateError = 16, /**< lc_ctrl_fatal_state_error */
+ kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 17, /**< lc_ctrl_fatal_bus_integ_error */
+ kTopEarlgreyAlertIdSpiHost0FatalFault = 18, /**< spi_host0_fatal_fault */
+ kTopEarlgreyAlertIdSpiHost1FatalFault = 19, /**< spi_host1_fatal_fault */
kTopEarlgreyAlertIdPwrmgrAonFatalFault = 20, /**< pwrmgr_aon_fatal_fault */
kTopEarlgreyAlertIdRstmgrAonFatalFault = 21, /**< rstmgr_aon_fatal_fault */
kTopEarlgreyAlertIdClkmgrAonRecovFault = 22, /**< clkmgr_aon_recov_fault */
@@ -1658,8 +1658,8 @@
typedef enum top_earlgrey_gateable_clocks {
kTopEarlgreyGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
kTopEarlgreyGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
- kTopEarlgreyGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
- kTopEarlgreyGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
+ kTopEarlgreyGateableClocksUsbPeri = 2, /**< Clock clk_usb_peri in group peri */
+ kTopEarlgreyGateableClocksIoPeri = 3, /**< Clock clk_io_peri in group peri */
kTopEarlgreyGateableClocksLast = 3, /**< \internal Last Valid Gateable Clock */
} top_earlgrey_gateable_clocks_t;
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
index be38c15..797608a 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
@@ -106,20 +106,6 @@
*/
#define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40050000
/**
- * Peripheral base address for spi_host0 in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40060000
-/**
- * Peripheral base address for spi_host1 in top earlgrey.
- *
- * This should be used with #mmio_region_from_addr to access the memory-mapped
- * registers associated with the peripheral (usually via a DIF).
- */
-#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40070000
-/**
* Peripheral base address for i2c0 in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -190,6 +176,20 @@
*/
#define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x40150000
/**
+ * Peripheral base address for spi_host0 in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40300000
+/**
+ * Peripheral base address for spi_host1 in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40310000
+/**
* Peripheral base address for pwrmgr_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
