[sw, flash_ctrl] Various flash fixes
- fix BANK_CFG multireg field offset
- add flash_cfg_bank_erase
diff --git a/hw/ip/flash_ctrl/doc/flash_ctrl.hjson b/hw/ip/flash_ctrl/doc/flash_ctrl.hjson
index 4074cb1..cc56e24 100644
--- a/hw/ip/flash_ctrl/doc/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/doc/flash_ctrl.hjson
@@ -275,7 +275,6 @@
],
},
-
{ multireg: {
cname: "FLASH_CTRL",
name: "MP_BANK_CFG",
@@ -285,7 +284,7 @@
hwaccess: "hro",
regwen: "BANK_CFG_REGWEN"
fields: [
- { bits: "1",
+ { bits: "0",
name: "ERASE_EN",
desc: '''
Bank wide erase enable
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_reg_block.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_reg_block.sv
index a196468..abeea1a 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_reg_block.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_reg_block.sv
@@ -1348,7 +1348,7 @@
erase_en0.configure(
.parent(this),
.size(1),
- .lsb_pos(1),
+ .lsb_pos(0),
.access("RW"),
.volatile(0),
.reset(0),
@@ -1359,7 +1359,7 @@
erase_en1.configure(
.parent(this),
.size(1),
- .lsb_pos(2),
+ .lsb_pos(1),
.access("RW"),
.volatile(0),
.reset(0),
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
index 030b23d..7a8dc1f 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
@@ -2567,7 +2567,7 @@
// Subregister 0 of Multireg mp_bank_cfg
// R[mp_bank_cfg]: V(False)
- // F[erase_en0]: 1:1
+ // F[erase_en0]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -2593,7 +2593,7 @@
);
- // F[erase_en1]: 2:2
+ // F[erase_en1]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -3171,10 +3171,10 @@
assign bank_cfg_regwen_wd = reg_wdata[0];
assign mp_bank_cfg_erase_en0_we = addr_hit[16] & reg_we & ~wr_err;
- assign mp_bank_cfg_erase_en0_wd = reg_wdata[1];
+ assign mp_bank_cfg_erase_en0_wd = reg_wdata[0];
assign mp_bank_cfg_erase_en1_we = addr_hit[16] & reg_we & ~wr_err;
- assign mp_bank_cfg_erase_en1_wd = reg_wdata[2];
+ assign mp_bank_cfg_erase_en1_wd = reg_wdata[1];
assign op_status_done_we = addr_hit[17] & reg_we & ~wr_err;
assign op_status_done_wd = reg_wdata[0];
@@ -3342,8 +3342,8 @@
end
addr_hit[16]: begin
- reg_rdata_next[1] = mp_bank_cfg_erase_en0_qs;
- reg_rdata_next[2] = mp_bank_cfg_erase_en1_qs;
+ reg_rdata_next[0] = mp_bank_cfg_erase_en0_qs;
+ reg_rdata_next[1] = mp_bank_cfg_erase_en1_qs;
end
addr_hit[17]: begin
diff --git a/hw/ip/flash_ctrl/sw/flash_ctrl_regs.h b/hw/ip/flash_ctrl/sw/flash_ctrl_regs.h
index ae9417d..aa49d08 100644
--- a/hw/ip/flash_ctrl/sw/flash_ctrl_regs.h
+++ b/hw/ip/flash_ctrl/sw/flash_ctrl_regs.h
@@ -164,8 +164,8 @@
// Memory protect bank configuration
#define FLASH_CTRL_MP_BANK_CFG(id) (FLASH_CTRL##id##_BASE_ADDR + 0x40)
-#define FLASH_CTRL_MP_BANK_CFG_ERASE_EN0 1
-#define FLASH_CTRL_MP_BANK_CFG_ERASE_EN1 2
+#define FLASH_CTRL_MP_BANK_CFG_ERASE_EN0 0
+#define FLASH_CTRL_MP_BANK_CFG_ERASE_EN1 1
// Flash Operation Status
#define FLASH_CTRL_OP_STATUS(id) (FLASH_CTRL##id##_BASE_ADDR + 0x44)
diff --git a/hw/top_earlgrey/dv/env/chip_reg_block.sv b/hw/top_earlgrey/dv/env/chip_reg_block.sv
index d4979a9..550f1ad 100644
--- a/hw/top_earlgrey/dv/env/chip_reg_block.sv
+++ b/hw/top_earlgrey/dv/env/chip_reg_block.sv
@@ -186,7 +186,6 @@
typedef class chip_mem_eflash;
typedef class chip_reg_block;
-
// Block: spi_device
// Class: spi_device_reg_intr_state
class spi_device_reg_intr_state extends dv_base_reg;
@@ -1074,7 +1073,6 @@
endfunction : build
endclass : spi_device_reg_block
-
// Block: flash_ctrl
// Class: flash_ctrl_reg_intr_state
class flash_ctrl_reg_intr_state extends dv_base_reg;
@@ -2392,7 +2390,7 @@
erase_en0.configure(
.parent(this),
.size(1),
- .lsb_pos(1),
+ .lsb_pos(0),
.access("RW"),
.volatile(0),
.reset(0),
@@ -2403,7 +2401,7 @@
erase_en1.configure(
.parent(this),
.size(1),
- .lsb_pos(2),
+ .lsb_pos(1),
.access("RW"),
.volatile(0),
.reset(0),
@@ -2844,7 +2842,6 @@
endfunction : build
endclass : flash_ctrl_reg_block
-
// Block: rv_timer
// Class: rv_timer_reg_ctrl
class rv_timer_reg_ctrl extends dv_base_reg;
@@ -3213,7 +3210,6 @@
endfunction : build
endclass : rv_timer_reg_block
-
// Block: gpio
// Class: gpio_reg_intr_state
class gpio_reg_intr_state extends dv_base_reg;
@@ -3840,7 +3836,6 @@
endfunction : build
endclass : gpio_reg_block
-
// Block: hmac
// Class: hmac_reg_intr_state
class hmac_reg_intr_state extends dv_base_reg;
@@ -4921,7 +4916,6 @@
endfunction : build
endclass : hmac_reg_block
-
// Block: uart
// Class: uart_reg_intr_state
class uart_reg_intr_state extends dv_base_reg;
@@ -5869,7 +5863,6 @@
endfunction : build
endclass : uart_reg_block
-
// Block: rv_plic
// Class: rv_plic_reg_ip0
class rv_plic_reg_ip0 extends dv_base_reg;
@@ -10096,7 +10089,6 @@
endfunction : build
endclass : rv_plic_reg_block
-
// Block: chip
// Class: chip_mem_rom
class chip_mem_rom extends dv_base_mem;
diff --git a/sw/lib/flash_ctrl.c b/sw/lib/flash_ctrl.c
index 163c772..e0c13ba 100644
--- a/sw/lib/flash_ctrl.c
+++ b/sw/lib/flash_ctrl.c
@@ -63,9 +63,7 @@
}
int flash_bank_erase(bank_index_t idx) {
- REG32(FLASH_CTRL_MP_BANK_CFG(0)) =
- 0x1 << ((idx == FLASH_BANK_0) ? FLASH_CTRL_MP_BANK_CFG_ERASE_EN0
- : FLASH_CTRL_MP_BANK_CFG_ERASE_EN1);
+ flash_cfg_bank_erase(idx, /*erase_en=*/true);
// TODO: Add timeout conditions and add error codes.
REG32(FLASH_CTRL_ADDR(0)) = (idx == FLASH_BANK_0)
@@ -77,9 +75,8 @@
0x1 << FLASH_CTRL_CONTROL_START);
wait_done_and_ack();
- REG32(FLASH_CTRL_MP_BANK_CFG(0)) =
- 0x0 << ((idx == FLASH_BANK_0) ? FLASH_CTRL_MP_BANK_CFG_ERASE_EN0
- : FLASH_CTRL_MP_BANK_CFG_ERASE_EN1);
+ flash_cfg_bank_erase(idx, /*erase_en=*/false);
+
return get_clr_err();
}
@@ -129,6 +126,12 @@
return get_clr_err();
}
+void flash_cfg_bank_erase(bank_index_t bank, bool erase_en) {
+ REG32(FLASH_CTRL_MP_BANK_CFG(0)) =
+ (erase_en) ? SETBIT(REG32(FLASH_CTRL_MP_BANK_CFG(0)), bank)
+ : CLRBIT(REG32(FLASH_CTRL_MP_BANK_CFG(0)), bank);
+}
+
void flash_default_region_access(bool rd_en, bool prog_en, bool erase_en) {
REG32(FLASH_CTRL_DEFAULT_REGION(0)) =
rd_en << FLASH_CTRL_DEFAULT_REGION_RD_EN |
diff --git a/sw/lib/flash_ctrl.h b/sw/lib/flash_ctrl.h
index 43eb18f..544afcc 100644
--- a/sw/lib/flash_ctrl.h
+++ b/sw/lib/flash_ctrl.h
@@ -71,6 +71,11 @@
int flash_read(uint32_t addr, uint32_t size, uint32_t *data);
/**
+ * Configure bank erase enable
+ */
+void flash_cfg_bank_erase(bank_index_t bank, bool erase_en);
+
+/**
* Set flash controller default permissions.
*
* @param rd_end Read enable.
diff --git a/sw/tests/flash_ctrl/flash_test.c b/sw/tests/flash_ctrl/flash_test.c
index 8128735..f52065a 100644
--- a/sw/tests/flash_ctrl/flash_test.c
+++ b/sw/tests/flash_ctrl/flash_test.c
@@ -66,6 +66,8 @@
flash_init_block();
// enable all access
+ flash_cfg_bank_erase(FLASH_BANK_0, /*erase_en=*/true);
+ flash_cfg_bank_erase(FLASH_BANK_1, /*erase_en=*/true);
flash_default_region_access(1, 1, 1);
break_on_error(flash_page_erase(bank1_addr));
flash_write_scratch_reg(0xFACEDEAD);
@@ -80,7 +82,7 @@
// do 4K programming
// employ the live programming method where overall payload >> flash fifo size
for (i = 0; i < ARRAYSIZE(prog_array); i++) {
- prog_array[i] = i + (i % 2) ? 0xA5A5A5A5 : 0x5A5A5A5A;
+ prog_array[i] = (i % 2) ? 0xA5A5A5A5 : 0x5A5A5A5A;
}
for (iteration = 0; iteration < 2; iteration++) {
@@ -154,6 +156,9 @@
}
}
+ flash_cfg_bank_erase(FLASH_BANK_0, /*erase_en=*/false);
+ flash_cfg_bank_erase(FLASH_BANK_1, /*erase_en=*/false);
+
// cleanly terminate execution
uart_send_str("PASS!\r\n");
__asm__ volatile("wfi;");
