[dv/dpi] Fix assignment to SystemVerilog chandle
Section 6.14 of the standard states that assignment to chandle can only
be made from `null` or an other chandle, not from an integer literal.
This patch allows the compilation of the simulation models with modelsim
Signed-off-by: Tarik Graba <tarik.graba@telecom-paris.fr>
diff --git a/hw/dv/dpi/dmidpi/dmidpi.sv b/hw/dv/dpi/dmidpi/dmidpi.sv
index 73fbb2e..cf79fef 100644
--- a/hw/dv/dpi/dmidpi/dmidpi.sv
+++ b/hw/dv/dpi/dmidpi/dmidpi.sv
@@ -43,7 +43,7 @@
final begin
dmidpi_close(ctx);
- ctx = 0;
+ ctx = null;
end
always_ff @(posedge clk_i, negedge rst_ni) begin
diff --git a/hw/dv/dpi/jtagdpi/jtagdpi.sv b/hw/dv/dpi/jtagdpi/jtagdpi.sv
index 50b0cca..e69d719 100644
--- a/hw/dv/dpi/jtagdpi/jtagdpi.sv
+++ b/hw/dv/dpi/jtagdpi/jtagdpi.sv
@@ -36,7 +36,7 @@
final begin
jtagdpi_close(ctx);
- ctx = 0;
+ ctx = null;
end
always_ff @(posedge clk_i, negedge rst_ni) begin
diff --git a/hw/dv/dpi/uartdpi/uartdpi.sv b/hw/dv/dpi/uartdpi/uartdpi.sv
index a293bc4..97fae47 100644
--- a/hw/dv/dpi/uartdpi/uartdpi.sv
+++ b/hw/dv/dpi/uartdpi/uartdpi.sv
@@ -44,7 +44,7 @@
final begin
uartdpi_close(ctx);
- ctx = 0;
+ ctx = null;
end
// TX
