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opensecura/3p/lowrisc/opentitan/c26f6dc94de1a1428bf068b532396d7e49b5f8a2/./util/topgen/templates
tree: 7c2b86a20ebb4b2bf69d7f8398d2052d6cb1b7d3 [path history] [tgz]
  1. alert_test.c.tpl
  2. BUILD.tpl
  3. chip_env_pkg__params.sv.tpl
  4. chiplevel.sv.tpl
  5. clang-format
  6. plic_all_irqs_test.c.tpl
  7. README.md
  8. tb__alert_handler_connect.sv.tpl
  9. tb__xbar_connect.sv.tpl
  10. toplevel.c.tpl
  11. toplevel.h.tpl
  12. toplevel.sv.tpl
  13. toplevel_memory.h.tpl
  14. toplevel_memory.ld.tpl
  15. toplevel_pkg.sv.tpl
  16. toplevel_rnd_cnst_pkg.sv.tpl
  17. xbar_env_pkg__params.sv.tpl
  18. xbar_tgl_excl.cfg.tpl
util/topgen/templates/README.md

OpenTitan topgen templates

This directory contains templates used by topgen to assembly a chip toplevel.