tree: 8cbd6ba7245da31e0f4e5404331b15a6f8f7cb8d [path history] [tgz]
  1. data/
  2. doc/
  3. fpv/
  4. lint/
  5. rtl/
  6. util/
  7. README.md
  8. rv_plic.core
  9. rv_plic_component.core
hw/ip/rv_plic/README.md

RISC-V Platform-Level Interrupt Controller

RV_PLIC module is to manage multiple interrupt events generated from the peripherals. It implements Platform-Level Interrupt Controller in RISC-V Privileges specification Section 7.

reg_rv_plic.py

The tool is to create register Hjson and top module rv_plic.sv files given values of number of sources, number of targets, and max value of priority. By default sources is 32, target is 1 and priority is 7 (8 level of priorities supported)

To change the value and to re-create hjson,

$ util/reg_rv_plic.py -s 32 -t 1 -p 7 data/rv_plic.hjson.tpl > data/rv_plic.hjson
$ util/reg_rv_plic.py -s 32 -t 1 -p 7 data/rv_plic.sv.tpl > rtl/rv_plic.sv