[top] Add partial SRAM scrambling device to top-level
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_pkg.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_pkg.sv
index c9bd504..90e75d0 100644
--- a/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_pkg.sv
+++ b/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_pkg.sv
@@ -6,6 +6,8 @@
package sram_ctrl_reg_pkg;
+ // Param list
+
////////////////////////////
// Typedefs for registers //
////////////////////////////
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 495a737..4be628a 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -342,13 +342,11 @@
.rerror_i (${m["name"]}_rerror)
);
- prim_ram_1p_adv #(
+ prim_ram_1p_scr #(
.Width(${data_width}),
.Depth(${sram_depth}),
.DataBitsPerMask(8),
- .CfgW(8),
- // TODO: enable parity once supported by the simulation infrastructure
- .EnableParity(0)
+ .CfgWidth(8)
) u_ram1p_${m["name"]} (
% for key in clocks:
.${key} (${clocks[key]}),
@@ -357,6 +355,9 @@
.${key} (${value}),
% endfor
+ .key_i ( '0 ),
+ .nonce_i ( '0 ),
+
.req_i (${m["name"]}_req),
.write_i (${m["name"]}_we),
.addr_i (${m["name"]}_addr),
@@ -365,8 +366,10 @@
.rdata_o (${m["name"]}_rdata),
.rvalid_o (${m["name"]}_rvalid),
.rerror_o (${m["name"]}_rerror),
+ .raddr_o ( ),
.cfg_i ('0)
);
+
% elif m["type"] == "rom":
<%
data_width = int(top["datawidth"])
diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh
index a400405..555853d 100644
--- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh
+++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh
@@ -9,8 +9,8 @@
`define SPI_DEVICE_HIER `CHIP_HIER.u_spi_device
`define ALERT_HANDLER_HIER `CHIP_HIER.u_alert_handler
`define CPU_HIER `CHIP_HIER.u_rv_core_ibex
-`define RAM_MAIN_HIER `CHIP_HIER.u_ram1p_ram_main.u_mem
-`define RAM_RET_HIER `CHIP_HIER.u_ram1p_ram_ret.u_mem
+`define RAM_MAIN_HIER `CHIP_HIER.u_ram1p_ram_main.u_prim_ram_1p_adv.u_mem
+`define RAM_RET_HIER `CHIP_HIER.u_ram1p_ram_ret.u_prim_ram_1p_adv.u_mem
`define ROM_HIER `CHIP_HIER.u_rom_rom.u_prim_rom
`define FLASH_HIER `CHIP_HIER.u_flash_eflash.u_flash
`define RSTMGR_HIER `CHIP_HIER.u_rstmgr
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 9b14726..71ca674 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -574,17 +574,18 @@
.rerror_i (ram_main_rerror)
);
- prim_ram_1p_adv #(
+ prim_ram_1p_scr #(
.Width(32),
.Depth(16384),
.DataBitsPerMask(8),
- .CfgW(8),
- // TODO: enable parity once supported by the simulation infrastructure
- .EnableParity(0)
+ .CfgWidth(8)
) u_ram1p_ram_main (
.clk_i (clkmgr_clocks.clk_main_infra),
.rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .key_i ( '0 ),
+ .nonce_i ( '0 ),
+
.req_i (ram_main_req),
.write_i (ram_main_we),
.addr_i (ram_main_addr),
@@ -593,8 +594,10 @@
.rdata_o (ram_main_rdata),
.rvalid_o (ram_main_rvalid),
.rerror_o (ram_main_rerror),
+ .raddr_o ( ),
.cfg_i ('0)
);
+
// sram device
logic ram_ret_req;
logic ram_ret_we;
@@ -626,17 +629,18 @@
.rerror_i (ram_ret_rerror)
);
- prim_ram_1p_adv #(
+ prim_ram_1p_scr #(
.Width(32),
.Depth(1024),
.DataBitsPerMask(8),
- .CfgW(8),
- // TODO: enable parity once supported by the simulation infrastructure
- .EnableParity(0)
+ .CfgWidth(8)
) u_ram1p_ram_ret (
.clk_i (clkmgr_clocks.clk_io_div4_infra),
.rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .key_i ( '0 ),
+ .nonce_i ( '0 ),
+
.req_i (ram_ret_req),
.write_i (ram_ret_we),
.addr_i (ram_ret_addr),
@@ -645,9 +649,11 @@
.rdata_o (ram_ret_rdata),
.rvalid_o (ram_ret_rvalid),
.rerror_o (ram_ret_rerror),
+ .raddr_o ( ),
.cfg_i ('0)
);
+
// host to flash communication
logic flash_host_req;
logic flash_host_req_rdy;
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core
index 0617cc2..aa417fb 100644
--- a/hw/top_earlgrey/top_earlgrey.core
+++ b/hw/top_earlgrey/top_earlgrey.core
@@ -28,7 +28,7 @@
- lowrisc:ip:hmac
- lowrisc:ip:kmac
- lowrisc:ip:otbn
- - lowrisc:prim:ram_1p_adv
+ - lowrisc:prim:ram_1p_scr
- lowrisc:prim:rom_adv
- lowrisc:prim:flash
- lowrisc:ip:flash_ctrl
diff --git a/hw/top_earlgrey/top_earlgrey_verilator.cc b/hw/top_earlgrey/top_earlgrey_verilator.cc
index cf8a1f5..45f8325 100644
--- a/hw/top_earlgrey/top_earlgrey_verilator.cc
+++ b/hw/top_earlgrey/top_earlgrey_verilator.cc
@@ -21,8 +21,8 @@
"gen_generic.u_impl_generic");
memutil.RegisterMemoryArea(
"ram",
- "TOP.top_earlgrey_verilator.top_earlgrey.u_ram1p_ram_main.u_mem."
- "gen_generic.u_impl_generic");
+ "TOP.top_earlgrey_verilator.top_earlgrey.u_ram1p_ram_main."
+ "u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic");
memutil.RegisterMemoryArea(
"flash",
("TOP.top_earlgrey_verilator.top_earlgrey.u_flash_eflash.u_flash."
