[aes] Add shadow CTRL register, interface with alert handler
This commit adds a shadow CTRL register according to @tjaychen's Shadow
Register RFC:
- If the content of the staged register and the value written to the
actual register do not match, this causes an update error and triggers
an alert. The register is not updated.
- If the contents of actual and shadow registers differ, this causes a
storage error and triggers an alert.
- Invalid mode field values are resolved to the new reset value
AES_NONE = 4'b1000.
- The cipher core is not allowed to start or finish unless the mode field
is set to a valid value.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 035da53..2507a0d 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -723,7 +723,15 @@
available_output_list: []
available_inout_list: []
interrupt_list: []
- alert_list: []
+ alert_list:
+ [
+ {
+ name: ctrl_err
+ width: 1
+ type: alert
+ async: 0
+ }
+ ]
wakeup_list: []
scan: "false"
scan_reset: "false"
@@ -3278,12 +3286,20 @@
]
alert_module:
[
+ aes
hmac
otbn
]
alert:
[
{
+ name: aes_ctrl_err
+ width: 1
+ type: alert
+ async: 0
+ module_name: aes
+ }
+ {
name: hmac_msg_push_sha_disabled
width: 1
type: alert
