[reggen] Fix name for "u_reg" backdoor in RAL code
The generated RAL code needs to know where to find the generated
register in the design. Before this patch, we had it hardcoded as
"u_reg" but that isn't going to work if there are multiple register
blocks in the design(!).
Here, we use the same naming convention as the rest of the reggen
code: if a device interface has an explicit name, "foo", we assume
things relating to the interface get a "_foo" suffix.
Also fix the name of the one example in the tree (in rom_ctrl.sv) to
match this convention.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/ip/rom_ctrl/rtl/rom_ctrl.sv b/hw/ip/rom_ctrl/rtl/rom_ctrl.sv
index 2bd197f..77f2677 100644
--- a/hw/ip/rom_ctrl/rtl/rom_ctrl.sv
+++ b/hw/ip/rom_ctrl/rtl/rom_ctrl.sv
@@ -119,7 +119,7 @@
rom_ctrl_regs_hw2reg_t hw2reg;
logic reg_integrity_error;
- rom_ctrl_regs_reg_top u_reg_top (
+ rom_ctrl_regs_reg_top u_reg_regs (
.clk_i (clk_i),
.rst_ni (rst_ni),
.tl_i (regs_tl_i),
diff --git a/util/reggen/gen_dv.py b/util/reggen/gen_dv.py
index f2d8aee..763d172 100644
--- a/util/reggen/gen_dv.py
+++ b/util/reggen/gen_dv.py
@@ -91,10 +91,10 @@
lblock = block.name.lower()
for if_name, rb in block.reg_blocks.items():
- if if_name is None:
- mod_base = lblock
- else:
- mod_base = lblock + '_' + if_name.lower()
+ hier_path = '' if block.hier_path is None else block.hier_path + '.'
+ if_suffix = '' if if_name is None else '_' + if_name.lower()
+ mod_base = lblock + if_suffix
+ reg_block_path = hier_path + 'u_reg' + if_suffix
file_name = mod_base + '_ral_pkg.sv'
generated.append(file_name)
@@ -104,6 +104,7 @@
fout.write(uvm_reg_tpl.render(rb=rb,
block=block,
esc_if_name=mod_base,
+ reg_block_path=reg_block_path,
dv_base_prefix=dv_base_prefix))
except: # noqa F722 for template Exception handling
log.error(exceptions.text_error_template().render())
diff --git a/util/reggen/top_uvm_reg.sv.tpl b/util/reggen/top_uvm_reg.sv.tpl
index b36edf5..5e4d9b9 100644
--- a/util/reggen/top_uvm_reg.sv.tpl
+++ b/util/reggen/top_uvm_reg.sv.tpl
@@ -35,9 +35,10 @@
if_suffix = '' if if_name is None else '_' + if_name
esc_if_name = block.name.lower() + if_suffix
if_desc = '' if if_name is None else '; interface {}'.format(if_name)
+ reg_block_path = 'u_reg' + if_suffix
%>\
// Block: ${block.name.lower()}${if_desc}
-${make_ral_pkg(dv_base_prefix, top.regwidth, '', rb, esc_if_name)}
+${make_ral_pkg(dv_base_prefix, top.regwidth, reg_block_path, rb, esc_if_name)}
% endfor
% endfor
##
diff --git a/util/reggen/uvm_reg.sv.tpl b/util/reggen/uvm_reg.sv.tpl
index 378b747..9d8d9dc 100644
--- a/util/reggen/uvm_reg.sv.tpl
+++ b/util/reggen/uvm_reg.sv.tpl
@@ -11,7 +11,4 @@
<%namespace file="uvm_reg_base.sv.tpl" import="*"/>\
##
##
-<%
- hier_path = '' if block.hier_path is None else block.hier_path + "."
-%>\
-${make_ral_pkg(dv_base_prefix, block.regwidth, hier_path, rb, esc_if_name)}
+${make_ral_pkg(dv_base_prefix, block.regwidth, reg_block_path, rb, esc_if_name)}
diff --git a/util/reggen/uvm_reg_base.sv.tpl b/util/reggen/uvm_reg_base.sv.tpl
index a67faf3..d4391ab 100644
--- a/util/reggen/uvm_reg_base.sv.tpl
+++ b/util/reggen/uvm_reg_base.sv.tpl
@@ -18,8 +18,8 @@
##
## reg_width an integer giving the width of registers in bits
##
-## hier_path a string giving the hierarchical path to the block
-## containing this device interface.
+## reg_block_path the hierarchical path to the relevant register block in the
+## design
##
## rb a RegBlock object
##
@@ -28,14 +28,14 @@
## this will be bar__foo. For an unnamed interface
## on block BAR, this will be just bar.
##
-<%def name="make_ral_pkg(dv_base_prefix, reg_width, hier_path, rb, esc_if_name)">\
+<%def name="make_ral_pkg(dv_base_prefix, reg_width, reg_block_path, rb, esc_if_name)">\
package ${esc_if_name}_ral_pkg;
${make_ral_pkg_hdr(dv_base_prefix, [])}
${make_ral_pkg_fwd_decls(esc_if_name, rb.flat_regs, rb.windows)}
% for reg in rb.flat_regs:
-${make_ral_pkg_reg_class(dv_base_prefix, reg_width, esc_if_name, hier_path, reg)}
+${make_ral_pkg_reg_class(dv_base_prefix, reg_width, esc_if_name, reg_block_path, reg)}
% endfor
% for window in rb.windows:
@@ -207,10 +207,10 @@
##
## esc_if_name as for make_ral_pkg
##
-## hier_path as for make_ral_pkg
+## reg_block_path as for make_ral_pkg
##
## reg a Register object
-<%def name="make_ral_pkg_reg_class(dv_base_prefix, reg_width, esc_if_name, hier_path, reg)">\
+<%def name="make_ral_pkg_reg_class(dv_base_prefix, reg_width, esc_if_name, reg_block_path, reg)">\
<%
reg_name = reg.name.lower()
@@ -246,7 +246,7 @@
else:
reg_field_name = reg_name + "_" + field.name.lower()
%>\
-${_create_reg_field(dv_base_prefix, reg_width, hier_path, reg.shadowed, reg.hwext, reg_field_name, field)}
+${_create_reg_field(dv_base_prefix, reg_width, reg_block_path, reg.shadowed, reg.hwext, reg_field_name, field)}
% endfor
% if reg.shadowed and reg.hwext:
<%
@@ -286,7 +286,7 @@
##
## reg_width as for make_ral_pkg
##
-## hier_path as for make_ral_pkg
+## reg_block_path as for make_ral_pkg
##
## shadowed true if the field's register is shadowed
##
@@ -295,7 +295,7 @@
## reg_field_name a string with the name to give the field in the HDL
##
## field a Field object
-<%def name="_create_reg_field(dv_base_prefix, reg_width, hier_path, shadowed, hwext, reg_field_name, field)">\
+<%def name="_create_reg_field(dv_base_prefix, reg_width, reg_block_path, shadowed, hwext, reg_field_name, field)">\
<%
field_size = field.bits.width()
if field.swaccess.key == "r0w1c":
@@ -327,13 +327,13 @@
field.swaccess.swrd() == SwRdAccess.RD and\
not field.swaccess.allows_write())):
// constant reg
- add_hdl_path_slice("${hier_path}u_reg.${reg_field_name}_qs", ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtl");
+ add_hdl_path_slice("${reg_block_path}.${reg_field_name}_qs", ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtl");
% else:
- add_hdl_path_slice("${hier_path}u_reg.u_${reg_field_name}.q${"s" if hwext else ""}", ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtl");
+ add_hdl_path_slice("${reg_block_path}.u_${reg_field_name}.q${"s" if hwext else ""}", ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtl");
% endif
% if shadowed and not hwext:
- add_hdl_path_slice("${hier_path}u_reg.u_${reg_field_name}.committed_reg.q", ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtlCommitted");
- add_hdl_path_slice("${hier_path}u_reg.u_${reg_field_name}.shadow_reg.q", ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtlShadow");
+ add_hdl_path_slice("${reg_block_path}.u_${reg_field_name}.committed_reg.q", ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtlCommitted");
+ add_hdl_path_slice("${reg_block_path}.u_${reg_field_name}.shadow_reg.q", ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtlShadow");
% endif
% if field_tags:
// create field tags
