[spi_host] Wire up integrity alert Signed-off-by: Michael Schaffner <msf@opentitan.org>

commit: bd21d5a2994b71fb16c70ce283a0c67e03d3e354 [log] [tgz]
author: Michael Schaffner <msf@opentitan.org> Mon Jun 07 16:38:34 2021 -0700
committer: Michael Schaffner <msf@google.com> Tue Jun 08 12:50:59 2021 -0700
tree: ed399daa836b009c9af7acc3623d389be6881814
parent: 8a6bedc600ccb8f690724f6a71b96c0fce166a9b [diff]
diff --git a/hw/ip/spi_host/data/spi_host.hjson b/hw/ip/spi_host/data/spi_host.hjson
index ef60a96..5fa1bd4 100644
--- a/hw/ip/spi_host/data/spi_host.hjson
+++ b/hw/ip/spi_host/data/spi_host.hjson

@@ -72,6 +72,13 @@
                information.'''
     }
   ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the HMAC unit.
+      '''
+    }
+  ],
   registers: [
     { name: "CONTROL",
       desc: "Control register",

diff --git a/hw/ip/spi_host/dv/env/spi_host_env_cfg.sv b/hw/ip/spi_host/dv/env/spi_host_env_cfg.sv
index 567bde2..5e14803 100644
--- a/hw/ip/spi_host/dv/env/spi_host_env_cfg.sv
+++ b/hw/ip/spi_host/dv/env/spi_host_env_cfg.sv

@@ -20,6 +20,7 @@
   virtual clk_rst_if clk_rst_core_vif;
 
   virtual function void initialize(bit [31:0] csr_base_addr = '1);
+    list_of_alerts = spi_host_env_pkg::LIST_OF_ALERTS;
     super.initialize(csr_base_addr);
 
     // create spi_host agent config obj

diff --git a/hw/ip/spi_host/dv/env/spi_host_env_pkg.sv b/hw/ip/spi_host/dv/env/spi_host_env_pkg.sv
index eb6adb3..41d6e87 100644
--- a/hw/ip/spi_host/dv/env/spi_host_env_pkg.sv
+++ b/hw/ip/spi_host/dv/env/spi_host_env_pkg.sv

@@ -28,6 +28,10 @@
     NumSpiHostIntr   = 2
   } spi_host_intr_e;
 
+  // alerts
+  parameter uint NUM_ALERTS = 1;
+  parameter string LIST_OF_ALERTS[] = {"fatal_fault"};
+
   // functions
 
   // package sources

diff --git a/hw/ip/spi_host/dv/tb.sv b/hw/ip/spi_host/dv/tb.sv
index 158505a..161101f 100644
--- a/hw/ip/spi_host/dv/tb.sv
+++ b/hw/ip/spi_host/dv/tb.sv

@@ -40,6 +40,8 @@
   tl_if        tl_if(.clk(clk), .rst_n(rst_n));
   spi_if       spi_if(.rst_n(rst_core_n));
 
+  `DV_ALERT_IF_CONNECT
+
   // dut
   spi_host spi_host (
     .clk_i                (clk),
@@ -48,6 +50,9 @@
     // tl i/f
     .tl_i                 (tl_if.h2d),
     .tl_o                 (tl_if.d2h),
+    // alerts
+    .alert_rx_i           (alert_rx),
+    .alert_tx_o           (alert_tx),
     // scan mode
     .clk_core_i           (clk_core),
     .rst_core_ni          (rst_core_n),

diff --git a/hw/ip/spi_host/rtl/spi_host.sv b/hw/ip/spi_host/rtl/spi_host.sv
index 6694d3b..703ef60 100644
--- a/hw/ip/spi_host/rtl/spi_host.sv
+++ b/hw/ip/spi_host/rtl/spi_host.sv

@@ -10,7 +10,9 @@
 
 module spi_host
   import spi_host_reg_pkg::*;
- (
+#(
+  parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
   input              clk_i,
   input              rst_ni,
   input              clk_core_i,
@@ -22,6 +24,10 @@
   input              tlul_pkg::tl_h2d_t tl_i,
   output             tlul_pkg::tl_d2h_t tl_o,
 
+  // Alerts
+  input  prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+  output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
   // SPI Interface
   output logic             cio_sck_o,
   output logic             cio_sck_en_o,
@@ -48,6 +54,7 @@
   tlul_pkg::tl_d2h_t fifo_win_d2h [1];
 
   // Register module
+  logic [NumAlerts-1:0] alert_test, alerts;
   spi_host_reg_top u_reg (
     .clk_i,
     .rst_ni,
@@ -57,10 +64,31 @@
     .tl_win_i   (fifo_win_d2h),
     .reg2hw,
     .hw2reg,
-    .intg_err_o (),
+    .intg_err_o (alerts[0]),
     .devmode_i  (1'b1)
   );
 
+  // Alerts
+  assign alert_test = {
+    reg2hw.alert_test.q &
+    reg2hw.alert_test.qe
+  };
+
+  for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+    prim_alert_sender #(
+      .AsyncOn(AlertAsyncOn[i]),
+      .IsFatal(i)
+    ) u_prim_alert_sender (
+      .clk_i,
+      .rst_ni,
+      .alert_test_i  ( alert_test[i] ),
+      .alert_req_i   ( alerts[0]     ),
+      .alert_ack_o   (               ),
+      .alert_state_o (               ),
+      .alert_rx_i    ( alert_rx_i[i] ),
+      .alert_tx_o    ( alert_tx_o[i] )
+    );
+  end
 
   logic             sck;
   logic [NumCS-1:0] csb;
@@ -563,6 +591,7 @@
 
   `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
   `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
+  `ASSERT_KNOWN(AlertKnownO_A, alert_tx_o)
   `ASSERT_KNOWN(CioSckKnownO_A, cio_sck_o)
   `ASSERT_KNOWN(CioSckEnKnownO_A, cio_sck_en_o)
   `ASSERT_KNOWN(CioCsbKnownO_A, cio_csb_o)

diff --git a/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv b/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv
index 29be731..56c5d86 100644
--- a/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv
+++ b/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv

@@ -11,6 +11,7 @@
   parameter int NumCS = 1;
   parameter int TxDepth = 72;
   parameter int RxDepth = 64;
+  parameter int NumAlerts = 1;
 
   // Address widths within the block
   parameter int BlockAw = 6;
@@ -49,6 +50,11 @@
   } spi_host_reg2hw_intr_test_reg_t;
 
   typedef struct packed {
+    logic        q;
+    logic        qe;
+  } spi_host_reg2hw_alert_test_reg_t;
+
+  typedef struct packed {
     struct packed {
       logic [7:0]  q;
     } rx_watermark;
@@ -261,9 +267,10 @@
 
   // Register -> HW type
   typedef struct packed {
-    spi_host_reg2hw_intr_state_reg_t intr_state; // [123:122]
-    spi_host_reg2hw_intr_enable_reg_t intr_enable; // [121:120]
-    spi_host_reg2hw_intr_test_reg_t intr_test; // [119:116]
+    spi_host_reg2hw_intr_state_reg_t intr_state; // [125:124]
+    spi_host_reg2hw_intr_enable_reg_t intr_enable; // [123:122]
+    spi_host_reg2hw_intr_test_reg_t intr_test; // [121:118]
+    spi_host_reg2hw_alert_test_reg_t alert_test; // [117:116]
     spi_host_reg2hw_control_reg_t control; // [115:97]
     spi_host_reg2hw_configopts_mreg_t [0:0] configopts; // [96:66]
     spi_host_reg2hw_csid_reg_t csid; // [65:34]
@@ -284,22 +291,25 @@
   parameter logic [BlockAw-1:0] SPI_HOST_INTR_STATE_OFFSET = 6'h 0;
   parameter logic [BlockAw-1:0] SPI_HOST_INTR_ENABLE_OFFSET = 6'h 4;
   parameter logic [BlockAw-1:0] SPI_HOST_INTR_TEST_OFFSET = 6'h 8;
-  parameter logic [BlockAw-1:0] SPI_HOST_CONTROL_OFFSET = 6'h c;
-  parameter logic [BlockAw-1:0] SPI_HOST_STATUS_OFFSET = 6'h 10;
-  parameter logic [BlockAw-1:0] SPI_HOST_CONFIGOPTS_OFFSET = 6'h 14;
-  parameter logic [BlockAw-1:0] SPI_HOST_CSID_OFFSET = 6'h 18;
-  parameter logic [BlockAw-1:0] SPI_HOST_COMMAND_OFFSET = 6'h 1c;
-  parameter logic [BlockAw-1:0] SPI_HOST_ERROR_ENABLE_OFFSET = 6'h 24;
-  parameter logic [BlockAw-1:0] SPI_HOST_ERROR_STATUS_OFFSET = 6'h 28;
-  parameter logic [BlockAw-1:0] SPI_HOST_EVENT_ENABLE_OFFSET = 6'h 2c;
+  parameter logic [BlockAw-1:0] SPI_HOST_ALERT_TEST_OFFSET = 6'h c;
+  parameter logic [BlockAw-1:0] SPI_HOST_CONTROL_OFFSET = 6'h 10;
+  parameter logic [BlockAw-1:0] SPI_HOST_STATUS_OFFSET = 6'h 14;
+  parameter logic [BlockAw-1:0] SPI_HOST_CONFIGOPTS_OFFSET = 6'h 18;
+  parameter logic [BlockAw-1:0] SPI_HOST_CSID_OFFSET = 6'h 1c;
+  parameter logic [BlockAw-1:0] SPI_HOST_COMMAND_OFFSET = 6'h 20;
+  parameter logic [BlockAw-1:0] SPI_HOST_ERROR_ENABLE_OFFSET = 6'h 28;
+  parameter logic [BlockAw-1:0] SPI_HOST_ERROR_STATUS_OFFSET = 6'h 2c;
+  parameter logic [BlockAw-1:0] SPI_HOST_EVENT_ENABLE_OFFSET = 6'h 30;
 
   // Reset values for hwext registers and their fields
   parameter logic [1:0] SPI_HOST_INTR_TEST_RESVAL = 2'h 0;
   parameter logic [0:0] SPI_HOST_INTR_TEST_ERROR_RESVAL = 1'h 0;
   parameter logic [0:0] SPI_HOST_INTR_TEST_SPI_EVENT_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_HOST_ALERT_TEST_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_HOST_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
 
   // Window parameters
-  parameter logic [BlockAw-1:0] SPI_HOST_DATA_OFFSET = 6'h 20;
+  parameter logic [BlockAw-1:0] SPI_HOST_DATA_OFFSET = 6'h 24;
   parameter int unsigned        SPI_HOST_DATA_SIZE   = 'h 4;
 
   // Register index
@@ -307,6 +317,7 @@
     SPI_HOST_INTR_STATE,
     SPI_HOST_INTR_ENABLE,
     SPI_HOST_INTR_TEST,
+    SPI_HOST_ALERT_TEST,
     SPI_HOST_CONTROL,
     SPI_HOST_STATUS,
     SPI_HOST_CONFIGOPTS,
@@ -318,18 +329,19 @@
   } spi_host_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] SPI_HOST_PERMIT [11] = '{
+  parameter logic [3:0] SPI_HOST_PERMIT [12] = '{
     4'b 0001, // index[ 0] SPI_HOST_INTR_STATE
     4'b 0001, // index[ 1] SPI_HOST_INTR_ENABLE
     4'b 0001, // index[ 2] SPI_HOST_INTR_TEST
-    4'b 1111, // index[ 3] SPI_HOST_CONTROL
-    4'b 1111, // index[ 4] SPI_HOST_STATUS
-    4'b 1111, // index[ 5] SPI_HOST_CONFIGOPTS
-    4'b 1111, // index[ 6] SPI_HOST_CSID
-    4'b 0011, // index[ 7] SPI_HOST_COMMAND
-    4'b 0001, // index[ 8] SPI_HOST_ERROR_ENABLE
-    4'b 0001, // index[ 9] SPI_HOST_ERROR_STATUS
-    4'b 0001  // index[10] SPI_HOST_EVENT_ENABLE
+    4'b 0001, // index[ 3] SPI_HOST_ALERT_TEST
+    4'b 1111, // index[ 4] SPI_HOST_CONTROL
+    4'b 1111, // index[ 5] SPI_HOST_STATUS
+    4'b 1111, // index[ 6] SPI_HOST_CONFIGOPTS
+    4'b 1111, // index[ 7] SPI_HOST_CSID
+    4'b 0011, // index[ 8] SPI_HOST_COMMAND
+    4'b 0001, // index[ 9] SPI_HOST_ERROR_ENABLE
+    4'b 0001, // index[10] SPI_HOST_ERROR_STATUS
+    4'b 0001  // index[11] SPI_HOST_EVENT_ENABLE
   };
 
 endpackage

diff --git a/hw/ip/spi_host/rtl/spi_host_reg_top.sv b/hw/ip/spi_host/rtl/spi_host_reg_top.sv
index be22487..82b9855 100644
--- a/hw/ip/spi_host/rtl/spi_host_reg_top.sv
+++ b/hw/ip/spi_host/rtl/spi_host_reg_top.sv

@@ -118,7 +118,7 @@
     reg_steer = 1;       // Default set to register
 
     // TODO: Can below codes be unique case () inside ?
-    if (tl_i.a_address[AW-1:0] >= 32 && tl_i.a_address[AW-1:0] < 36) begin
+    if (tl_i.a_address[AW-1:0] >= 36 && tl_i.a_address[AW-1:0] < 40) begin
       reg_steer = 0;
     end
     if (intg_err) begin
@@ -168,6 +168,8 @@
   logic intr_test_error_we;
   logic intr_test_spi_event_wd;
   logic intr_test_spi_event_we;
+  logic alert_test_wd;
+  logic alert_test_we;
   logic [7:0] control_rx_watermark_qs;
   logic [7:0] control_rx_watermark_wd;
   logic control_rx_watermark_we;
@@ -422,6 +424,22 @@
   );
 
 
+  // R[alert_test]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_alert_test (
+    .re     (1'b0),
+    .we     (alert_test_we),
+    .wd     (alert_test_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (reg2hw.alert_test.qe),
+    .q      (reg2hw.alert_test.q ),
+    .qs     ()
+  );
+
+
   // R[control]: V(False)
 
   //   F[rx_watermark]: 7:0
@@ -1625,20 +1643,21 @@
 
 
 
-  logic [10:0] addr_hit;
+  logic [11:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[ 0] = (reg_addr == SPI_HOST_INTR_STATE_OFFSET);
     addr_hit[ 1] = (reg_addr == SPI_HOST_INTR_ENABLE_OFFSET);
     addr_hit[ 2] = (reg_addr == SPI_HOST_INTR_TEST_OFFSET);
-    addr_hit[ 3] = (reg_addr == SPI_HOST_CONTROL_OFFSET);
-    addr_hit[ 4] = (reg_addr == SPI_HOST_STATUS_OFFSET);
-    addr_hit[ 5] = (reg_addr == SPI_HOST_CONFIGOPTS_OFFSET);
-    addr_hit[ 6] = (reg_addr == SPI_HOST_CSID_OFFSET);
-    addr_hit[ 7] = (reg_addr == SPI_HOST_COMMAND_OFFSET);
-    addr_hit[ 8] = (reg_addr == SPI_HOST_ERROR_ENABLE_OFFSET);
-    addr_hit[ 9] = (reg_addr == SPI_HOST_ERROR_STATUS_OFFSET);
-    addr_hit[10] = (reg_addr == SPI_HOST_EVENT_ENABLE_OFFSET);
+    addr_hit[ 3] = (reg_addr == SPI_HOST_ALERT_TEST_OFFSET);
+    addr_hit[ 4] = (reg_addr == SPI_HOST_CONTROL_OFFSET);
+    addr_hit[ 5] = (reg_addr == SPI_HOST_STATUS_OFFSET);
+    addr_hit[ 6] = (reg_addr == SPI_HOST_CONFIGOPTS_OFFSET);
+    addr_hit[ 7] = (reg_addr == SPI_HOST_CSID_OFFSET);
+    addr_hit[ 8] = (reg_addr == SPI_HOST_COMMAND_OFFSET);
+    addr_hit[ 9] = (reg_addr == SPI_HOST_ERROR_ENABLE_OFFSET);
+    addr_hit[10] = (reg_addr == SPI_HOST_ERROR_STATUS_OFFSET);
+    addr_hit[11] = (reg_addr == SPI_HOST_EVENT_ENABLE_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -1656,7 +1675,8 @@
                (addr_hit[ 7] & (|(SPI_HOST_PERMIT[ 7] & ~reg_be))) |
                (addr_hit[ 8] & (|(SPI_HOST_PERMIT[ 8] & ~reg_be))) |
                (addr_hit[ 9] & (|(SPI_HOST_PERMIT[ 9] & ~reg_be))) |
-               (addr_hit[10] & (|(SPI_HOST_PERMIT[10] & ~reg_be)))));
+               (addr_hit[10] & (|(SPI_HOST_PERMIT[10] & ~reg_be))) |
+               (addr_hit[11] & (|(SPI_HOST_PERMIT[11] & ~reg_be)))));
   end
 
   assign intr_state_error_we = addr_hit[0] & reg_we & !reg_error;
@@ -1677,103 +1697,106 @@
   assign intr_test_spi_event_we = addr_hit[2] & reg_we & !reg_error;
   assign intr_test_spi_event_wd = reg_wdata[1];
 
-  assign control_rx_watermark_we = addr_hit[3] & reg_we & !reg_error;
+  assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+  assign alert_test_wd = reg_wdata[0];
+
+  assign control_rx_watermark_we = addr_hit[4] & reg_we & !reg_error;
   assign control_rx_watermark_wd = reg_wdata[7:0];
 
-  assign control_tx_watermark_we = addr_hit[3] & reg_we & !reg_error;
+  assign control_tx_watermark_we = addr_hit[4] & reg_we & !reg_error;
   assign control_tx_watermark_wd = reg_wdata[15:8];
 
-  assign control_passthru_we = addr_hit[3] & reg_we & !reg_error;
+  assign control_passthru_we = addr_hit[4] & reg_we & !reg_error;
   assign control_passthru_wd = reg_wdata[29];
 
-  assign control_sw_rst_we = addr_hit[3] & reg_we & !reg_error;
+  assign control_sw_rst_we = addr_hit[4] & reg_we & !reg_error;
   assign control_sw_rst_wd = reg_wdata[30];
 
-  assign control_spien_we = addr_hit[3] & reg_we & !reg_error;
+  assign control_spien_we = addr_hit[4] & reg_we & !reg_error;
   assign control_spien_wd = reg_wdata[31];
 
-  assign configopts_clkdiv_0_we = addr_hit[5] & reg_we & !reg_error;
+  assign configopts_clkdiv_0_we = addr_hit[6] & reg_we & !reg_error;
   assign configopts_clkdiv_0_wd = reg_wdata[15:0];
 
-  assign configopts_csnidle_0_we = addr_hit[5] & reg_we & !reg_error;
+  assign configopts_csnidle_0_we = addr_hit[6] & reg_we & !reg_error;
   assign configopts_csnidle_0_wd = reg_wdata[19:16];
 
-  assign configopts_csntrail_0_we = addr_hit[5] & reg_we & !reg_error;
+  assign configopts_csntrail_0_we = addr_hit[6] & reg_we & !reg_error;
   assign configopts_csntrail_0_wd = reg_wdata[23:20];
 
-  assign configopts_csnlead_0_we = addr_hit[5] & reg_we & !reg_error;
+  assign configopts_csnlead_0_we = addr_hit[6] & reg_we & !reg_error;
   assign configopts_csnlead_0_wd = reg_wdata[27:24];
 
-  assign configopts_fullcyc_0_we = addr_hit[5] & reg_we & !reg_error;
+  assign configopts_fullcyc_0_we = addr_hit[6] & reg_we & !reg_error;
   assign configopts_fullcyc_0_wd = reg_wdata[29];
 
-  assign configopts_cpha_0_we = addr_hit[5] & reg_we & !reg_error;
+  assign configopts_cpha_0_we = addr_hit[6] & reg_we & !reg_error;
   assign configopts_cpha_0_wd = reg_wdata[30];
 
-  assign configopts_cpol_0_we = addr_hit[5] & reg_we & !reg_error;
+  assign configopts_cpol_0_we = addr_hit[6] & reg_we & !reg_error;
   assign configopts_cpol_0_wd = reg_wdata[31];
 
-  assign csid_we = addr_hit[6] & reg_we & !reg_error;
+  assign csid_we = addr_hit[7] & reg_we & !reg_error;
   assign csid_wd = reg_wdata[31:0];
 
-  assign command_len_we = addr_hit[7] & reg_we & !reg_error;
+  assign command_len_we = addr_hit[8] & reg_we & !reg_error;
   assign command_len_wd = reg_wdata[8:0];
 
-  assign command_csaat_we = addr_hit[7] & reg_we & !reg_error;
+  assign command_csaat_we = addr_hit[8] & reg_we & !reg_error;
   assign command_csaat_wd = reg_wdata[9];
 
-  assign command_speed_we = addr_hit[7] & reg_we & !reg_error;
+  assign command_speed_we = addr_hit[8] & reg_we & !reg_error;
   assign command_speed_wd = reg_wdata[11:10];
 
-  assign command_direction_we = addr_hit[7] & reg_we & !reg_error;
+  assign command_direction_we = addr_hit[8] & reg_we & !reg_error;
   assign command_direction_wd = reg_wdata[13:12];
 
-  assign error_enable_cmdbusy_we = addr_hit[8] & reg_we & !reg_error;
+  assign error_enable_cmdbusy_we = addr_hit[9] & reg_we & !reg_error;
   assign error_enable_cmdbusy_wd = reg_wdata[0];
 
-  assign error_enable_overflow_we = addr_hit[8] & reg_we & !reg_error;
+  assign error_enable_overflow_we = addr_hit[9] & reg_we & !reg_error;
   assign error_enable_overflow_wd = reg_wdata[1];
 
-  assign error_enable_underflow_we = addr_hit[8] & reg_we & !reg_error;
+  assign error_enable_underflow_we = addr_hit[9] & reg_we & !reg_error;
   assign error_enable_underflow_wd = reg_wdata[2];
 
-  assign error_enable_cmdinval_we = addr_hit[8] & reg_we & !reg_error;
+  assign error_enable_cmdinval_we = addr_hit[9] & reg_we & !reg_error;
   assign error_enable_cmdinval_wd = reg_wdata[3];
 
-  assign error_enable_csidinval_we = addr_hit[8] & reg_we & !reg_error;
+  assign error_enable_csidinval_we = addr_hit[9] & reg_we & !reg_error;
   assign error_enable_csidinval_wd = reg_wdata[4];
 
-  assign error_status_cmdbusy_we = addr_hit[9] & reg_we & !reg_error;
+  assign error_status_cmdbusy_we = addr_hit[10] & reg_we & !reg_error;
   assign error_status_cmdbusy_wd = reg_wdata[0];
 
-  assign error_status_overflow_we = addr_hit[9] & reg_we & !reg_error;
+  assign error_status_overflow_we = addr_hit[10] & reg_we & !reg_error;
   assign error_status_overflow_wd = reg_wdata[1];
 
-  assign error_status_underflow_we = addr_hit[9] & reg_we & !reg_error;
+  assign error_status_underflow_we = addr_hit[10] & reg_we & !reg_error;
   assign error_status_underflow_wd = reg_wdata[2];
 
-  assign error_status_cmdinval_we = addr_hit[9] & reg_we & !reg_error;
+  assign error_status_cmdinval_we = addr_hit[10] & reg_we & !reg_error;
   assign error_status_cmdinval_wd = reg_wdata[3];
 
-  assign error_status_csidinval_we = addr_hit[9] & reg_we & !reg_error;
+  assign error_status_csidinval_we = addr_hit[10] & reg_we & !reg_error;
   assign error_status_csidinval_wd = reg_wdata[4];
 
-  assign event_enable_rxfull_we = addr_hit[10] & reg_we & !reg_error;
+  assign event_enable_rxfull_we = addr_hit[11] & reg_we & !reg_error;
   assign event_enable_rxfull_wd = reg_wdata[0];
 
-  assign event_enable_txempty_we = addr_hit[10] & reg_we & !reg_error;
+  assign event_enable_txempty_we = addr_hit[11] & reg_we & !reg_error;
   assign event_enable_txempty_wd = reg_wdata[1];
 
-  assign event_enable_rxwm_we = addr_hit[10] & reg_we & !reg_error;
+  assign event_enable_rxwm_we = addr_hit[11] & reg_we & !reg_error;
   assign event_enable_rxwm_wd = reg_wdata[2];
 
-  assign event_enable_txwm_we = addr_hit[10] & reg_we & !reg_error;
+  assign event_enable_txwm_we = addr_hit[11] & reg_we & !reg_error;
   assign event_enable_txwm_wd = reg_wdata[3];
 
-  assign event_enable_ready_we = addr_hit[10] & reg_we & !reg_error;
+  assign event_enable_ready_we = addr_hit[11] & reg_we & !reg_error;
   assign event_enable_ready_wd = reg_wdata[4];
 
-  assign event_enable_idle_we = addr_hit[10] & reg_we & !reg_error;
+  assign event_enable_idle_we = addr_hit[11] & reg_we & !reg_error;
   assign event_enable_idle_wd = reg_wdata[5];
 
   // Read data return
@@ -1796,6 +1819,10 @@
       end
 
       addr_hit[3]: begin
+        reg_rdata_next[0] = '0;
+      end
+
+      addr_hit[4]: begin
         reg_rdata_next[7:0] = control_rx_watermark_qs;
         reg_rdata_next[15:8] = control_tx_watermark_qs;
         reg_rdata_next[29] = control_passthru_qs;
@@ -1803,7 +1830,7 @@
         reg_rdata_next[31] = control_spien_qs;
       end
 
-      addr_hit[4]: begin
+      addr_hit[5]: begin
         reg_rdata_next[7:0] = status_txqd_qs;
         reg_rdata_next[15:8] = status_rxqd_qs;
         reg_rdata_next[20] = status_rxwm_qs;
@@ -1819,7 +1846,7 @@
         reg_rdata_next[31] = status_ready_qs;
       end
 
-      addr_hit[5]: begin
+      addr_hit[6]: begin
         reg_rdata_next[15:0] = configopts_clkdiv_0_qs;
         reg_rdata_next[19:16] = configopts_csnidle_0_qs;
         reg_rdata_next[23:20] = configopts_csntrail_0_qs;
@@ -1829,18 +1856,18 @@
         reg_rdata_next[31] = configopts_cpol_0_qs;
       end
 
-      addr_hit[6]: begin
+      addr_hit[7]: begin
         reg_rdata_next[31:0] = csid_qs;
       end
 
-      addr_hit[7]: begin
+      addr_hit[8]: begin
         reg_rdata_next[8:0] = command_len_qs;
         reg_rdata_next[9] = command_csaat_qs;
         reg_rdata_next[11:10] = command_speed_qs;
         reg_rdata_next[13:12] = command_direction_qs;
       end
 
-      addr_hit[8]: begin
+      addr_hit[9]: begin
         reg_rdata_next[0] = error_enable_cmdbusy_qs;
         reg_rdata_next[1] = error_enable_overflow_qs;
         reg_rdata_next[2] = error_enable_underflow_qs;
@@ -1848,7 +1875,7 @@
         reg_rdata_next[4] = error_enable_csidinval_qs;
       end
 
-      addr_hit[9]: begin
+      addr_hit[10]: begin
         reg_rdata_next[0] = error_status_cmdbusy_qs;
         reg_rdata_next[1] = error_status_overflow_qs;
         reg_rdata_next[2] = error_status_underflow_qs;
@@ -1856,7 +1883,7 @@
         reg_rdata_next[4] = error_status_csidinval_qs;
       end
 
-      addr_hit[10]: begin
+      addr_hit[11]: begin
         reg_rdata_next[0] = event_enable_rxfull_qs;
         reg_rdata_next[1] = event_enable_txempty_qs;
         reg_rdata_next[2] = event_enable_rxwm_qs;

diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 065fd09..978e8d2 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson

@@ -11530,6 +11530,8 @@
   ]
   alert_module:
   [
+    spi_host0
+    spi_host1
     otp_ctrl
     lc_ctrl
     sensor_ctrl_aon
@@ -11550,6 +11552,20 @@
   alert:
   [
     {
+      name: spi_host0_fatal_fault
+      width: 1
+      type: alert
+      async: "0"
+      module_name: spi_host0
+    }
+    {
+      name: spi_host1_fatal_fault
+      width: 1
+      type: alert
+      async: "0"
+      module_name: spi_host1
+    }
+    {
       name: otp_ctrl_fatal_macro_error
       width: 1
       type: alert

diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index b35200f..463011c 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv

@@ -4,40 +4,42 @@
 //
 // tb__alert_handler_connect.sv is auto-generated by `topgen.py` tool
 
-assign alert_if[0].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
-assign alert_if[1].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
-assign alert_if[2].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
-assign alert_if[3].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
-assign alert_if[4].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
-assign alert_if[5].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
-assign alert_if[6].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
-assign alert_if[7].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
-assign alert_if[8].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
-assign alert_if[9].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
-assign alert_if[10].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
-assign alert_if[11].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
-assign alert_if[12].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
-assign alert_if[13].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
-assign alert_if[14].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
-assign alert_if[15].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
-assign alert_if[16].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
-assign alert_if[17].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
-assign alert_if[18].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
-assign alert_if[20].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
-assign alert_if[21].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[22].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[23].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
-assign alert_if[24].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
-assign alert_if[25].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[26].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[27].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[28].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[29].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[30].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[31].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[32].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[33].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
-assign alert_if[34].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[35].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[36].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[0].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0];
+assign alert_if[1].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0];
+assign alert_if[2].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
+assign alert_if[3].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
+assign alert_if[4].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
+assign alert_if[5].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
+assign alert_if[6].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
+assign alert_if[7].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
+assign alert_if[8].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
+assign alert_if[9].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
+assign alert_if[10].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
+assign alert_if[11].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
+assign alert_if[12].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
+assign alert_if[13].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
+assign alert_if[14].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
+assign alert_if[15].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
+assign alert_if[16].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
+assign alert_if[17].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
+assign alert_if[20].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
+assign alert_if[21].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[22].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
+assign alert_if[23].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[24].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[25].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
+assign alert_if[26].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
+assign alert_if[27].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[28].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[29].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[30].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[31].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[32].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[33].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[34].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[35].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
+assign alert_if[36].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[37].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[38].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];

diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index 06b76ee..83bfc70 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv

@@ -5,6 +5,8 @@
 // Generated by topgen.py
 
 parameter string LIST_OF_ALERTS[] = {
+  "spi_host0_fatal_fault",
+  "spi_host1_fatal_fault",
   "otp_ctrl_fatal_macro_error",
   "otp_ctrl_fatal_check_error",
   "lc_ctrl_fatal_prog_error",
@@ -44,4 +46,4 @@
   "rom_ctrl_fatal"
 };
 
-parameter uint NUM_ALERTS = 37;
+parameter uint NUM_ALERTS = 39;

diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index c4bda45..8b95259 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson

@@ -48,7 +48,7 @@
     { name: "NAlerts",
       desc: "Number of peripheral inputs",
       type: "int",
-      default: "37",
+      default: "39",
       local: "true"
     },
     { name: "EscCntDw",
@@ -66,7 +66,7 @@
     { name: "AsyncOn",
       desc: "Number of peripheral outputs",
       type: "logic [NAlerts-1:0]",
-      default: "37'b1111111111111111111100000000000000000",
+      default: "39'b111111111111111111110000000000000000000",
       local: "true"
     },
     { name: "N_CLASSES",

diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index f2220c6..cabb7c1 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv

@@ -7,10 +7,10 @@
 package alert_handler_reg_pkg;
 
   // Param list
-  parameter int NAlerts = 37;
+  parameter int NAlerts = 39;
   parameter int EscCntDw = 32;
   parameter int AccuCntDw = 16;
-  parameter logic [NAlerts-1:0] AsyncOn = 37'b1111111111111111111100000000000000000;
+  parameter logic [NAlerts-1:0] AsyncOn = 39'b111111111111111111110000000000000000000;
   parameter int N_CLASSES = 4;
   parameter int N_ESC_SEV = 4;
   parameter int N_PHASES = 4;
@@ -20,7 +20,7 @@
   parameter int CLASS_DW = 2;
 
   // Address widths within the block
-  parameter int BlockAw = 10;
+  parameter int BlockAw = 11;
 
   ////////////////////////////
   // Typedefs for registers //
@@ -458,15 +458,15 @@
 
   // Register -> HW type
   typedef struct packed {
-    alert_handler_reg2hw_intr_state_reg_t intr_state; // [1009:1006]
-    alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1005:1002]
-    alert_handler_reg2hw_intr_test_reg_t intr_test; // [1001:994]
-    alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [993:970]
-    alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [969:969]
-    alert_handler_reg2hw_alert_regwen_mreg_t [36:0] alert_regwen; // [968:932]
-    alert_handler_reg2hw_alert_en_mreg_t [36:0] alert_en; // [931:895]
-    alert_handler_reg2hw_alert_class_mreg_t [36:0] alert_class; // [894:821]
-    alert_handler_reg2hw_alert_cause_mreg_t [36:0] alert_cause; // [820:784]
+    alert_handler_reg2hw_intr_state_reg_t intr_state; // [1019:1016]
+    alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1015:1012]
+    alert_handler_reg2hw_intr_test_reg_t intr_test; // [1011:1004]
+    alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1003:980]
+    alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [979:979]
+    alert_handler_reg2hw_alert_regwen_mreg_t [38:0] alert_regwen; // [978:940]
+    alert_handler_reg2hw_alert_en_mreg_t [38:0] alert_en; // [939:901]
+    alert_handler_reg2hw_alert_class_mreg_t [38:0] alert_class; // [900:823]
+    alert_handler_reg2hw_alert_cause_mreg_t [38:0] alert_cause; // [822:784]
     alert_handler_reg2hw_loc_alert_en_mreg_t [3:0] loc_alert_en; // [783:780]
     alert_handler_reg2hw_loc_alert_class_mreg_t [3:0] loc_alert_class; // [779:772]
     alert_handler_reg2hw_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [771:768]
@@ -506,8 +506,8 @@
 
   // HW -> register type
   typedef struct packed {
-    alert_handler_hw2reg_intr_state_reg_t intr_state; // [301:294]
-    alert_handler_hw2reg_alert_cause_mreg_t [36:0] alert_cause; // [293:220]
+    alert_handler_hw2reg_intr_state_reg_t intr_state; // [305:298]
+    alert_handler_hw2reg_alert_cause_mreg_t [38:0] alert_cause; // [297:220]
     alert_handler_hw2reg_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [219:212]
     alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
     alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -528,261 +528,271 @@
   } alert_handler_hw2reg_t;
 
   // Register offsets
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_STATE_OFFSET = 10'h 0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_ENABLE_OFFSET = 10'h 4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_TEST_OFFSET = 10'h 8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET = 10'h c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET = 10'h 10;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_EN_OFFSET = 10'h 14;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_0_OFFSET = 10'h 18;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_1_OFFSET = 10'h 1c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_2_OFFSET = 10'h 20;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_3_OFFSET = 10'h 24;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_4_OFFSET = 10'h 28;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_5_OFFSET = 10'h 2c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_6_OFFSET = 10'h 30;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_7_OFFSET = 10'h 34;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_8_OFFSET = 10'h 38;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_9_OFFSET = 10'h 3c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_10_OFFSET = 10'h 40;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_11_OFFSET = 10'h 44;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_12_OFFSET = 10'h 48;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_13_OFFSET = 10'h 4c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_14_OFFSET = 10'h 50;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_15_OFFSET = 10'h 54;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_16_OFFSET = 10'h 58;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_17_OFFSET = 10'h 5c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_18_OFFSET = 10'h 60;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_19_OFFSET = 10'h 64;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_20_OFFSET = 10'h 68;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_21_OFFSET = 10'h 6c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_22_OFFSET = 10'h 70;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_23_OFFSET = 10'h 74;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_24_OFFSET = 10'h 78;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_25_OFFSET = 10'h 7c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_26_OFFSET = 10'h 80;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_27_OFFSET = 10'h 84;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_28_OFFSET = 10'h 88;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_29_OFFSET = 10'h 8c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_30_OFFSET = 10'h 90;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_31_OFFSET = 10'h 94;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_32_OFFSET = 10'h 98;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_33_OFFSET = 10'h 9c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_34_OFFSET = 10'h a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_35_OFFSET = 10'h a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_36_OFFSET = 10'h a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 10'h ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 10'h b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 10'h b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 10'h b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 10'h bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 10'h c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 10'h c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 10'h c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 10'h cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 10'h d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 10'h d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 10'h d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 10'h dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 10'h e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 10'h e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 10'h e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 10'h ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 10'h f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 10'h f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 10'h f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 10'h fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 10'h 100;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 10'h 104;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 10'h 108;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 10'h 10c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 10'h 110;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 10'h 114;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 10'h 118;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 10'h 11c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 10'h 120;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 10'h 124;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 10'h 128;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 10'h 12c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 10'h 130;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 10'h 134;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 10'h 138;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 10'h 13c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 10'h 140;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 10'h 144;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 10'h 148;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 10'h 14c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 10'h 150;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 10'h 154;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 10'h 158;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 10'h 15c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 10'h 160;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 10'h 164;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 10'h 168;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 10'h 16c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 10'h 170;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 10'h 174;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 10'h 178;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 10'h 17c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 10'h 180;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 10'h 184;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 10'h 188;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 10'h 18c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 10'h 190;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 10'h 194;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 10'h 198;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 10'h 19c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 10'h 1a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 10'h 1a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 10'h 1a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 10'h 1ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 10'h 1b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 10'h 1b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 10'h 1b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 10'h 1bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 10'h 1c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 10'h 1c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 10'h 1c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 10'h 1cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 10'h 1d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 10'h 1d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 10'h 1d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 10'h 1dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 10'h 1e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 10'h 1e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 10'h 1e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 10'h 1ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 10'h 1f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 10'h 1f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 10'h 1f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 10'h 1fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 10'h 200;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 10'h 204;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 10'h 208;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 10'h 20c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 10'h 210;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 10'h 214;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 10'h 218;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 10'h 21c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 10'h 220;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 10'h 224;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 10'h 228;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 10'h 22c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 10'h 230;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 10'h 234;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 10'h 238;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 10'h 23c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 10'h 240;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 10'h 244;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 10'h 248;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 10'h 24c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 10'h 250;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 10'h 254;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 10'h 258;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 10'h 25c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 10'h 260;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 10'h 264;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 10'h 268;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 10'h 26c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 10'h 270;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 10'h 274;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 10'h 278;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 10'h 27c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 10'h 280;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_7_OFFSET = 10'h 284;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_8_OFFSET = 10'h 288;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_9_OFFSET = 10'h 28c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_10_OFFSET = 10'h 290;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_11_OFFSET = 10'h 294;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_12_OFFSET = 10'h 298;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_13_OFFSET = 10'h 29c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_14_OFFSET = 10'h 2a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_15_OFFSET = 10'h 2a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_16_OFFSET = 10'h 2a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_17_OFFSET = 10'h 2ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_18_OFFSET = 10'h 2b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_19_OFFSET = 10'h 2b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_20_OFFSET = 10'h 2b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_21_OFFSET = 10'h 2bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_22_OFFSET = 10'h 2c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_23_OFFSET = 10'h 2c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_24_OFFSET = 10'h 2c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_25_OFFSET = 10'h 2cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_26_OFFSET = 10'h 2d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_27_OFFSET = 10'h 2d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_28_OFFSET = 10'h 2d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_29_OFFSET = 10'h 2dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_30_OFFSET = 10'h 2e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_31_OFFSET = 10'h 2e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_32_OFFSET = 10'h 2e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_33_OFFSET = 10'h 2ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_34_OFFSET = 10'h 2f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_35_OFFSET = 10'h 2f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_36_OFFSET = 10'h 2f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 10'h 2fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 10'h 300;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 10'h 304;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 10'h 308;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 10'h 30c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 10'h 310;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 10'h 314;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 10'h 318;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 10'h 31c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 10'h 320;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 10'h 324;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 10'h 328;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 10'h 32c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 10'h 330;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 10'h 334;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 10'h 338;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 10'h 33c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 10'h 340;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 10'h 344;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 10'h 348;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 10'h 34c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 10'h 350;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 10'h 354;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 10'h 358;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 10'h 35c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 10'h 360;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 10'h 364;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 10'h 368;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 10'h 36c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 10'h 370;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 10'h 374;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 10'h 378;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 10'h 37c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 10'h 380;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 10'h 384;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 10'h 388;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 10'h 38c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 10'h 390;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 10'h 394;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 10'h 398;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 10'h 39c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 10'h 3a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 10'h 3a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 10'h 3a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 10'h 3ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 10'h 3b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 10'h 3b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 10'h 3b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 10'h 3bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 10'h 3c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 10'h 3c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 10'h 3c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 10'h 3cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 10'h 3d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 10'h 3d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 10'h 3d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 10'h 3dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 10'h 3e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 10'h 3e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 10'h 3e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 10'h 3ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 10'h 3f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 10'h 3f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 10'h 3f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_STATE_OFFSET = 11'h 0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_ENABLE_OFFSET = 11'h 4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_TEST_OFFSET = 11'h 8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET = 11'h c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET = 11'h 10;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_EN_OFFSET = 11'h 14;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_0_OFFSET = 11'h 18;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_1_OFFSET = 11'h 1c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_2_OFFSET = 11'h 20;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_3_OFFSET = 11'h 24;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_4_OFFSET = 11'h 28;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_5_OFFSET = 11'h 2c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_6_OFFSET = 11'h 30;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_7_OFFSET = 11'h 34;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_8_OFFSET = 11'h 38;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_9_OFFSET = 11'h 3c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_10_OFFSET = 11'h 40;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_11_OFFSET = 11'h 44;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_12_OFFSET = 11'h 48;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_13_OFFSET = 11'h 4c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_14_OFFSET = 11'h 50;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_15_OFFSET = 11'h 54;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_16_OFFSET = 11'h 58;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_17_OFFSET = 11'h 5c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_18_OFFSET = 11'h 60;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_19_OFFSET = 11'h 64;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_20_OFFSET = 11'h 68;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_21_OFFSET = 11'h 6c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_22_OFFSET = 11'h 70;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_23_OFFSET = 11'h 74;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_24_OFFSET = 11'h 78;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_25_OFFSET = 11'h 7c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_26_OFFSET = 11'h 80;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_27_OFFSET = 11'h 84;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_28_OFFSET = 11'h 88;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_29_OFFSET = 11'h 8c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_30_OFFSET = 11'h 90;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_31_OFFSET = 11'h 94;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_32_OFFSET = 11'h 98;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_33_OFFSET = 11'h 9c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_34_OFFSET = 11'h a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_35_OFFSET = 11'h a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_36_OFFSET = 11'h a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_37_OFFSET = 11'h ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_38_OFFSET = 11'h b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 11'h b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 11'h b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 11'h bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 11'h c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 11'h c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 11'h c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 11'h cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 11'h d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 11'h d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 11'h d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 11'h dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 11'h e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 11'h e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 11'h e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 11'h ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 11'h f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 11'h f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 11'h f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 11'h fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 11'h 100;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 11'h 104;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 11'h 108;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 11'h 10c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 11'h 110;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 11'h 114;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 11'h 118;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 11'h 11c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 11'h 120;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 11'h 124;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 11'h 128;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 11'h 12c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 11'h 130;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 11'h 134;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 11'h 138;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 11'h 13c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 11'h 140;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 11'h 144;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 11'h 148;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 11'h 14c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 11'h 150;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 11'h 154;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 11'h 158;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 11'h 15c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 11'h 160;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 11'h 164;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 11'h 168;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 11'h 16c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 11'h 170;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 11'h 174;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 11'h 178;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 11'h 17c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 11'h 180;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 11'h 184;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 11'h 188;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 11'h 18c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 11'h 190;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 11'h 194;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 11'h 198;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 11'h 19c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 11'h 1a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 11'h 1a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 11'h 1a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 11'h 1ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 11'h 1b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 11'h 1b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 11'h 1b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 11'h 1bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 11'h 1c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 11'h 1c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 11'h 1c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 11'h 1cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 11'h 1d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 11'h 1d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 11'h 1d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 11'h 1dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 11'h 1e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 11'h 1e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 11'h 1e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 1ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 1f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 1f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 1f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 1fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 200;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 204;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 208;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 20c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 210;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 214;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 218;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 21c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 220;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 224;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 228;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 22c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 230;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 234;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 238;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 23c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 240;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 244;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 248;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 24c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 250;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 254;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 258;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 25c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 260;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 264;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 268;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 26c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 270;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 274;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 278;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 27c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 280;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 284;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 288;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 28c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 290;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 294;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 298;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 29c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 2a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_7_OFFSET = 11'h 2a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_8_OFFSET = 11'h 2a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_9_OFFSET = 11'h 2ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_10_OFFSET = 11'h 2b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_11_OFFSET = 11'h 2b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_12_OFFSET = 11'h 2b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_13_OFFSET = 11'h 2bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_14_OFFSET = 11'h 2c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_15_OFFSET = 11'h 2c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_16_OFFSET = 11'h 2c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_17_OFFSET = 11'h 2cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_18_OFFSET = 11'h 2d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_19_OFFSET = 11'h 2d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_20_OFFSET = 11'h 2d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_21_OFFSET = 11'h 2dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_22_OFFSET = 11'h 2e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_23_OFFSET = 11'h 2e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_24_OFFSET = 11'h 2e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_25_OFFSET = 11'h 2ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_26_OFFSET = 11'h 2f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_27_OFFSET = 11'h 2f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_28_OFFSET = 11'h 2f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_29_OFFSET = 11'h 2fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_30_OFFSET = 11'h 300;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_31_OFFSET = 11'h 304;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_32_OFFSET = 11'h 308;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_33_OFFSET = 11'h 30c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_34_OFFSET = 11'h 310;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_35_OFFSET = 11'h 314;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_36_OFFSET = 11'h 318;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_37_OFFSET = 11'h 31c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_38_OFFSET = 11'h 320;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 11'h 324;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 11'h 328;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 11'h 32c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 11'h 330;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 11'h 334;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 11'h 338;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 11'h 33c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 11'h 340;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 344;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 348;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 34c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 350;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 354;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 11'h 358;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 35c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 11'h 360;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 364;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 11'h 368;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 11'h 36c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 11'h 370;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 11'h 374;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 11'h 378;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 11'h 37c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 380;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 384;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 388;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 11'h 38c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 390;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 11'h 394;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 398;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 11'h 39c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 11'h 3a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 11'h 3a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 11'h 3a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 11'h 3ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 11'h 3b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 3b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 3b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 3bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 11'h 3c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 3c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 11'h 3c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 3cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 11'h 3d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 11'h 3d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 11'h 3d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 11'h 3dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 11'h 3e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 11'h 3e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 3e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 3ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 3f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 11'h 3f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 3f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 11'h 3fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 400;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 11'h 404;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 11'h 408;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 11'h 40c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 11'h 410;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 11'h 414;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 11'h 418;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 41c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 420;
 
   // Reset values for hwext registers and their fields
   parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
@@ -848,6 +858,8 @@
     ALERT_HANDLER_ALERT_REGWEN_34,
     ALERT_HANDLER_ALERT_REGWEN_35,
     ALERT_HANDLER_ALERT_REGWEN_36,
+    ALERT_HANDLER_ALERT_REGWEN_37,
+    ALERT_HANDLER_ALERT_REGWEN_38,
     ALERT_HANDLER_ALERT_EN_0,
     ALERT_HANDLER_ALERT_EN_1,
     ALERT_HANDLER_ALERT_EN_2,
@@ -885,6 +897,8 @@
     ALERT_HANDLER_ALERT_EN_34,
     ALERT_HANDLER_ALERT_EN_35,
     ALERT_HANDLER_ALERT_EN_36,
+    ALERT_HANDLER_ALERT_EN_37,
+    ALERT_HANDLER_ALERT_EN_38,
     ALERT_HANDLER_ALERT_CLASS_0,
     ALERT_HANDLER_ALERT_CLASS_1,
     ALERT_HANDLER_ALERT_CLASS_2,
@@ -922,6 +936,8 @@
     ALERT_HANDLER_ALERT_CLASS_34,
     ALERT_HANDLER_ALERT_CLASS_35,
     ALERT_HANDLER_ALERT_CLASS_36,
+    ALERT_HANDLER_ALERT_CLASS_37,
+    ALERT_HANDLER_ALERT_CLASS_38,
     ALERT_HANDLER_ALERT_CAUSE_0,
     ALERT_HANDLER_ALERT_CAUSE_1,
     ALERT_HANDLER_ALERT_CAUSE_2,
@@ -959,6 +975,8 @@
     ALERT_HANDLER_ALERT_CAUSE_34,
     ALERT_HANDLER_ALERT_CAUSE_35,
     ALERT_HANDLER_ALERT_CAUSE_36,
+    ALERT_HANDLER_ALERT_CAUSE_37,
+    ALERT_HANDLER_ALERT_CAUSE_38,
     ALERT_HANDLER_LOC_ALERT_REGWEN_0,
     ALERT_HANDLER_LOC_ALERT_REGWEN_1,
     ALERT_HANDLER_LOC_ALERT_REGWEN_2,
@@ -996,6 +1014,8 @@
     ALERT_HANDLER_LOC_ALERT_REGWEN_34,
     ALERT_HANDLER_LOC_ALERT_REGWEN_35,
     ALERT_HANDLER_LOC_ALERT_REGWEN_36,
+    ALERT_HANDLER_LOC_ALERT_REGWEN_37,
+    ALERT_HANDLER_LOC_ALERT_REGWEN_38,
     ALERT_HANDLER_LOC_ALERT_EN_0,
     ALERT_HANDLER_LOC_ALERT_EN_1,
     ALERT_HANDLER_LOC_ALERT_EN_2,
@@ -1063,7 +1083,7 @@
   } alert_handler_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] ALERT_HANDLER_PERMIT [255] = '{
+  parameter logic [3:0] ALERT_HANDLER_PERMIT [265] = '{
     4'b 0001, // index[  0] ALERT_HANDLER_INTR_STATE
     4'b 0001, // index[  1] ALERT_HANDLER_INTR_ENABLE
     4'b 0001, // index[  2] ALERT_HANDLER_INTR_TEST
@@ -1107,218 +1127,228 @@
     4'b 0001, // index[ 40] ALERT_HANDLER_ALERT_REGWEN_34
     4'b 0001, // index[ 41] ALERT_HANDLER_ALERT_REGWEN_35
     4'b 0001, // index[ 42] ALERT_HANDLER_ALERT_REGWEN_36
-    4'b 0001, // index[ 43] ALERT_HANDLER_ALERT_EN_0
-    4'b 0001, // index[ 44] ALERT_HANDLER_ALERT_EN_1
-    4'b 0001, // index[ 45] ALERT_HANDLER_ALERT_EN_2
-    4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_EN_3
-    4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_EN_4
-    4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_EN_5
-    4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_EN_6
-    4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_EN_7
-    4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_EN_8
-    4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_EN_9
-    4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_EN_10
-    4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_11
-    4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_12
-    4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_13
-    4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_14
-    4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_15
-    4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_16
-    4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_17
-    4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_18
-    4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_19
-    4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_20
-    4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_21
-    4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_22
-    4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_23
-    4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_24
-    4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_25
-    4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_26
-    4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_27
-    4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_28
-    4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_29
-    4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_30
-    4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_31
-    4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_32
-    4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_33
-    4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_34
-    4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_35
-    4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_36
-    4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_CLASS_0
-    4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_CLASS_1
-    4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_CLASS_2
-    4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_CLASS_3
-    4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_CLASS_4
-    4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_CLASS_5
-    4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_CLASS_6
-    4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_CLASS_7
-    4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_CLASS_8
-    4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_CLASS_9
-    4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_CLASS_10
-    4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_CLASS_11
-    4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_CLASS_12
-    4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_CLASS_13
-    4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_CLASS_14
-    4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_CLASS_15
-    4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_CLASS_16
-    4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_CLASS_17
-    4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_CLASS_18
-    4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_CLASS_19
-    4'b 0001, // index[100] ALERT_HANDLER_ALERT_CLASS_20
-    4'b 0001, // index[101] ALERT_HANDLER_ALERT_CLASS_21
-    4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_22
-    4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_23
-    4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_24
-    4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_25
-    4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_26
-    4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_27
-    4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_28
-    4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_29
-    4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_30
-    4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_31
-    4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_32
-    4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_33
-    4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_34
-    4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_35
-    4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_36
-    4'b 0001, // index[117] ALERT_HANDLER_ALERT_CAUSE_0
-    4'b 0001, // index[118] ALERT_HANDLER_ALERT_CAUSE_1
-    4'b 0001, // index[119] ALERT_HANDLER_ALERT_CAUSE_2
-    4'b 0001, // index[120] ALERT_HANDLER_ALERT_CAUSE_3
-    4'b 0001, // index[121] ALERT_HANDLER_ALERT_CAUSE_4
-    4'b 0001, // index[122] ALERT_HANDLER_ALERT_CAUSE_5
-    4'b 0001, // index[123] ALERT_HANDLER_ALERT_CAUSE_6
-    4'b 0001, // index[124] ALERT_HANDLER_ALERT_CAUSE_7
-    4'b 0001, // index[125] ALERT_HANDLER_ALERT_CAUSE_8
-    4'b 0001, // index[126] ALERT_HANDLER_ALERT_CAUSE_9
-    4'b 0001, // index[127] ALERT_HANDLER_ALERT_CAUSE_10
-    4'b 0001, // index[128] ALERT_HANDLER_ALERT_CAUSE_11
-    4'b 0001, // index[129] ALERT_HANDLER_ALERT_CAUSE_12
-    4'b 0001, // index[130] ALERT_HANDLER_ALERT_CAUSE_13
-    4'b 0001, // index[131] ALERT_HANDLER_ALERT_CAUSE_14
-    4'b 0001, // index[132] ALERT_HANDLER_ALERT_CAUSE_15
-    4'b 0001, // index[133] ALERT_HANDLER_ALERT_CAUSE_16
-    4'b 0001, // index[134] ALERT_HANDLER_ALERT_CAUSE_17
-    4'b 0001, // index[135] ALERT_HANDLER_ALERT_CAUSE_18
-    4'b 0001, // index[136] ALERT_HANDLER_ALERT_CAUSE_19
-    4'b 0001, // index[137] ALERT_HANDLER_ALERT_CAUSE_20
-    4'b 0001, // index[138] ALERT_HANDLER_ALERT_CAUSE_21
-    4'b 0001, // index[139] ALERT_HANDLER_ALERT_CAUSE_22
-    4'b 0001, // index[140] ALERT_HANDLER_ALERT_CAUSE_23
-    4'b 0001, // index[141] ALERT_HANDLER_ALERT_CAUSE_24
-    4'b 0001, // index[142] ALERT_HANDLER_ALERT_CAUSE_25
-    4'b 0001, // index[143] ALERT_HANDLER_ALERT_CAUSE_26
-    4'b 0001, // index[144] ALERT_HANDLER_ALERT_CAUSE_27
-    4'b 0001, // index[145] ALERT_HANDLER_ALERT_CAUSE_28
-    4'b 0001, // index[146] ALERT_HANDLER_ALERT_CAUSE_29
-    4'b 0001, // index[147] ALERT_HANDLER_ALERT_CAUSE_30
-    4'b 0001, // index[148] ALERT_HANDLER_ALERT_CAUSE_31
-    4'b 0001, // index[149] ALERT_HANDLER_ALERT_CAUSE_32
-    4'b 0001, // index[150] ALERT_HANDLER_ALERT_CAUSE_33
-    4'b 0001, // index[151] ALERT_HANDLER_ALERT_CAUSE_34
-    4'b 0001, // index[152] ALERT_HANDLER_ALERT_CAUSE_35
-    4'b 0001, // index[153] ALERT_HANDLER_ALERT_CAUSE_36
-    4'b 0001, // index[154] ALERT_HANDLER_LOC_ALERT_REGWEN_0
-    4'b 0001, // index[155] ALERT_HANDLER_LOC_ALERT_REGWEN_1
-    4'b 0001, // index[156] ALERT_HANDLER_LOC_ALERT_REGWEN_2
-    4'b 0001, // index[157] ALERT_HANDLER_LOC_ALERT_REGWEN_3
-    4'b 0001, // index[158] ALERT_HANDLER_LOC_ALERT_REGWEN_4
-    4'b 0001, // index[159] ALERT_HANDLER_LOC_ALERT_REGWEN_5
-    4'b 0001, // index[160] ALERT_HANDLER_LOC_ALERT_REGWEN_6
-    4'b 0001, // index[161] ALERT_HANDLER_LOC_ALERT_REGWEN_7
-    4'b 0001, // index[162] ALERT_HANDLER_LOC_ALERT_REGWEN_8
-    4'b 0001, // index[163] ALERT_HANDLER_LOC_ALERT_REGWEN_9
-    4'b 0001, // index[164] ALERT_HANDLER_LOC_ALERT_REGWEN_10
-    4'b 0001, // index[165] ALERT_HANDLER_LOC_ALERT_REGWEN_11
-    4'b 0001, // index[166] ALERT_HANDLER_LOC_ALERT_REGWEN_12
-    4'b 0001, // index[167] ALERT_HANDLER_LOC_ALERT_REGWEN_13
-    4'b 0001, // index[168] ALERT_HANDLER_LOC_ALERT_REGWEN_14
-    4'b 0001, // index[169] ALERT_HANDLER_LOC_ALERT_REGWEN_15
-    4'b 0001, // index[170] ALERT_HANDLER_LOC_ALERT_REGWEN_16
-    4'b 0001, // index[171] ALERT_HANDLER_LOC_ALERT_REGWEN_17
-    4'b 0001, // index[172] ALERT_HANDLER_LOC_ALERT_REGWEN_18
-    4'b 0001, // index[173] ALERT_HANDLER_LOC_ALERT_REGWEN_19
-    4'b 0001, // index[174] ALERT_HANDLER_LOC_ALERT_REGWEN_20
-    4'b 0001, // index[175] ALERT_HANDLER_LOC_ALERT_REGWEN_21
-    4'b 0001, // index[176] ALERT_HANDLER_LOC_ALERT_REGWEN_22
-    4'b 0001, // index[177] ALERT_HANDLER_LOC_ALERT_REGWEN_23
-    4'b 0001, // index[178] ALERT_HANDLER_LOC_ALERT_REGWEN_24
-    4'b 0001, // index[179] ALERT_HANDLER_LOC_ALERT_REGWEN_25
-    4'b 0001, // index[180] ALERT_HANDLER_LOC_ALERT_REGWEN_26
-    4'b 0001, // index[181] ALERT_HANDLER_LOC_ALERT_REGWEN_27
-    4'b 0001, // index[182] ALERT_HANDLER_LOC_ALERT_REGWEN_28
-    4'b 0001, // index[183] ALERT_HANDLER_LOC_ALERT_REGWEN_29
-    4'b 0001, // index[184] ALERT_HANDLER_LOC_ALERT_REGWEN_30
-    4'b 0001, // index[185] ALERT_HANDLER_LOC_ALERT_REGWEN_31
-    4'b 0001, // index[186] ALERT_HANDLER_LOC_ALERT_REGWEN_32
-    4'b 0001, // index[187] ALERT_HANDLER_LOC_ALERT_REGWEN_33
-    4'b 0001, // index[188] ALERT_HANDLER_LOC_ALERT_REGWEN_34
-    4'b 0001, // index[189] ALERT_HANDLER_LOC_ALERT_REGWEN_35
-    4'b 0001, // index[190] ALERT_HANDLER_LOC_ALERT_REGWEN_36
-    4'b 0001, // index[191] ALERT_HANDLER_LOC_ALERT_EN_0
-    4'b 0001, // index[192] ALERT_HANDLER_LOC_ALERT_EN_1
-    4'b 0001, // index[193] ALERT_HANDLER_LOC_ALERT_EN_2
-    4'b 0001, // index[194] ALERT_HANDLER_LOC_ALERT_EN_3
-    4'b 0001, // index[195] ALERT_HANDLER_LOC_ALERT_CLASS_0
-    4'b 0001, // index[196] ALERT_HANDLER_LOC_ALERT_CLASS_1
-    4'b 0001, // index[197] ALERT_HANDLER_LOC_ALERT_CLASS_2
-    4'b 0001, // index[198] ALERT_HANDLER_LOC_ALERT_CLASS_3
-    4'b 0001, // index[199] ALERT_HANDLER_LOC_ALERT_CAUSE_0
-    4'b 0001, // index[200] ALERT_HANDLER_LOC_ALERT_CAUSE_1
-    4'b 0001, // index[201] ALERT_HANDLER_LOC_ALERT_CAUSE_2
-    4'b 0001, // index[202] ALERT_HANDLER_LOC_ALERT_CAUSE_3
-    4'b 0001, // index[203] ALERT_HANDLER_CLASSA_REGWEN
-    4'b 0011, // index[204] ALERT_HANDLER_CLASSA_CTRL
-    4'b 0001, // index[205] ALERT_HANDLER_CLASSA_CLR_REGWEN
-    4'b 0001, // index[206] ALERT_HANDLER_CLASSA_CLR
-    4'b 0011, // index[207] ALERT_HANDLER_CLASSA_ACCUM_CNT
-    4'b 0011, // index[208] ALERT_HANDLER_CLASSA_ACCUM_THRESH
-    4'b 1111, // index[209] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
-    4'b 1111, // index[210] ALERT_HANDLER_CLASSA_PHASE0_CYC
-    4'b 1111, // index[211] ALERT_HANDLER_CLASSA_PHASE1_CYC
-    4'b 1111, // index[212] ALERT_HANDLER_CLASSA_PHASE2_CYC
-    4'b 1111, // index[213] ALERT_HANDLER_CLASSA_PHASE3_CYC
-    4'b 1111, // index[214] ALERT_HANDLER_CLASSA_ESC_CNT
-    4'b 0001, // index[215] ALERT_HANDLER_CLASSA_STATE
-    4'b 0001, // index[216] ALERT_HANDLER_CLASSB_REGWEN
-    4'b 0011, // index[217] ALERT_HANDLER_CLASSB_CTRL
-    4'b 0001, // index[218] ALERT_HANDLER_CLASSB_CLR_REGWEN
-    4'b 0001, // index[219] ALERT_HANDLER_CLASSB_CLR
-    4'b 0011, // index[220] ALERT_HANDLER_CLASSB_ACCUM_CNT
-    4'b 0011, // index[221] ALERT_HANDLER_CLASSB_ACCUM_THRESH
-    4'b 1111, // index[222] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
-    4'b 1111, // index[223] ALERT_HANDLER_CLASSB_PHASE0_CYC
-    4'b 1111, // index[224] ALERT_HANDLER_CLASSB_PHASE1_CYC
-    4'b 1111, // index[225] ALERT_HANDLER_CLASSB_PHASE2_CYC
-    4'b 1111, // index[226] ALERT_HANDLER_CLASSB_PHASE3_CYC
-    4'b 1111, // index[227] ALERT_HANDLER_CLASSB_ESC_CNT
-    4'b 0001, // index[228] ALERT_HANDLER_CLASSB_STATE
-    4'b 0001, // index[229] ALERT_HANDLER_CLASSC_REGWEN
-    4'b 0011, // index[230] ALERT_HANDLER_CLASSC_CTRL
-    4'b 0001, // index[231] ALERT_HANDLER_CLASSC_CLR_REGWEN
-    4'b 0001, // index[232] ALERT_HANDLER_CLASSC_CLR
-    4'b 0011, // index[233] ALERT_HANDLER_CLASSC_ACCUM_CNT
-    4'b 0011, // index[234] ALERT_HANDLER_CLASSC_ACCUM_THRESH
-    4'b 1111, // index[235] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
-    4'b 1111, // index[236] ALERT_HANDLER_CLASSC_PHASE0_CYC
-    4'b 1111, // index[237] ALERT_HANDLER_CLASSC_PHASE1_CYC
-    4'b 1111, // index[238] ALERT_HANDLER_CLASSC_PHASE2_CYC
-    4'b 1111, // index[239] ALERT_HANDLER_CLASSC_PHASE3_CYC
-    4'b 1111, // index[240] ALERT_HANDLER_CLASSC_ESC_CNT
-    4'b 0001, // index[241] ALERT_HANDLER_CLASSC_STATE
-    4'b 0001, // index[242] ALERT_HANDLER_CLASSD_REGWEN
-    4'b 0011, // index[243] ALERT_HANDLER_CLASSD_CTRL
-    4'b 0001, // index[244] ALERT_HANDLER_CLASSD_CLR_REGWEN
-    4'b 0001, // index[245] ALERT_HANDLER_CLASSD_CLR
-    4'b 0011, // index[246] ALERT_HANDLER_CLASSD_ACCUM_CNT
-    4'b 0011, // index[247] ALERT_HANDLER_CLASSD_ACCUM_THRESH
-    4'b 1111, // index[248] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
-    4'b 1111, // index[249] ALERT_HANDLER_CLASSD_PHASE0_CYC
-    4'b 1111, // index[250] ALERT_HANDLER_CLASSD_PHASE1_CYC
-    4'b 1111, // index[251] ALERT_HANDLER_CLASSD_PHASE2_CYC
-    4'b 1111, // index[252] ALERT_HANDLER_CLASSD_PHASE3_CYC
-    4'b 1111, // index[253] ALERT_HANDLER_CLASSD_ESC_CNT
-    4'b 0001  // index[254] ALERT_HANDLER_CLASSD_STATE
+    4'b 0001, // index[ 43] ALERT_HANDLER_ALERT_REGWEN_37
+    4'b 0001, // index[ 44] ALERT_HANDLER_ALERT_REGWEN_38
+    4'b 0001, // index[ 45] ALERT_HANDLER_ALERT_EN_0
+    4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_EN_1
+    4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_EN_2
+    4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_EN_3
+    4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_EN_4
+    4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_EN_5
+    4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_EN_6
+    4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_EN_7
+    4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_EN_8
+    4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_9
+    4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_10
+    4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_11
+    4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_12
+    4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_13
+    4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_14
+    4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_15
+    4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_16
+    4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_17
+    4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_18
+    4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_19
+    4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_20
+    4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_21
+    4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_22
+    4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_23
+    4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_24
+    4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_25
+    4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_26
+    4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_27
+    4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_28
+    4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_29
+    4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_30
+    4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_31
+    4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_32
+    4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_33
+    4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_34
+    4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_35
+    4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_36
+    4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_37
+    4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_38
+    4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_CLASS_0
+    4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_CLASS_1
+    4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_CLASS_2
+    4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_CLASS_3
+    4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_CLASS_4
+    4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_CLASS_5
+    4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_CLASS_6
+    4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_CLASS_7
+    4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_CLASS_8
+    4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_CLASS_9
+    4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_CLASS_10
+    4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_CLASS_11
+    4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_CLASS_12
+    4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_CLASS_13
+    4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_CLASS_14
+    4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_CLASS_15
+    4'b 0001, // index[100] ALERT_HANDLER_ALERT_CLASS_16
+    4'b 0001, // index[101] ALERT_HANDLER_ALERT_CLASS_17
+    4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_18
+    4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_19
+    4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_20
+    4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_21
+    4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_22
+    4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_23
+    4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_24
+    4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_25
+    4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_26
+    4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_27
+    4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_28
+    4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_29
+    4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_30
+    4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_31
+    4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_32
+    4'b 0001, // index[117] ALERT_HANDLER_ALERT_CLASS_33
+    4'b 0001, // index[118] ALERT_HANDLER_ALERT_CLASS_34
+    4'b 0001, // index[119] ALERT_HANDLER_ALERT_CLASS_35
+    4'b 0001, // index[120] ALERT_HANDLER_ALERT_CLASS_36
+    4'b 0001, // index[121] ALERT_HANDLER_ALERT_CLASS_37
+    4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_38
+    4'b 0001, // index[123] ALERT_HANDLER_ALERT_CAUSE_0
+    4'b 0001, // index[124] ALERT_HANDLER_ALERT_CAUSE_1
+    4'b 0001, // index[125] ALERT_HANDLER_ALERT_CAUSE_2
+    4'b 0001, // index[126] ALERT_HANDLER_ALERT_CAUSE_3
+    4'b 0001, // index[127] ALERT_HANDLER_ALERT_CAUSE_4
+    4'b 0001, // index[128] ALERT_HANDLER_ALERT_CAUSE_5
+    4'b 0001, // index[129] ALERT_HANDLER_ALERT_CAUSE_6
+    4'b 0001, // index[130] ALERT_HANDLER_ALERT_CAUSE_7
+    4'b 0001, // index[131] ALERT_HANDLER_ALERT_CAUSE_8
+    4'b 0001, // index[132] ALERT_HANDLER_ALERT_CAUSE_9
+    4'b 0001, // index[133] ALERT_HANDLER_ALERT_CAUSE_10
+    4'b 0001, // index[134] ALERT_HANDLER_ALERT_CAUSE_11
+    4'b 0001, // index[135] ALERT_HANDLER_ALERT_CAUSE_12
+    4'b 0001, // index[136] ALERT_HANDLER_ALERT_CAUSE_13
+    4'b 0001, // index[137] ALERT_HANDLER_ALERT_CAUSE_14
+    4'b 0001, // index[138] ALERT_HANDLER_ALERT_CAUSE_15
+    4'b 0001, // index[139] ALERT_HANDLER_ALERT_CAUSE_16
+    4'b 0001, // index[140] ALERT_HANDLER_ALERT_CAUSE_17
+    4'b 0001, // index[141] ALERT_HANDLER_ALERT_CAUSE_18
+    4'b 0001, // index[142] ALERT_HANDLER_ALERT_CAUSE_19
+    4'b 0001, // index[143] ALERT_HANDLER_ALERT_CAUSE_20
+    4'b 0001, // index[144] ALERT_HANDLER_ALERT_CAUSE_21
+    4'b 0001, // index[145] ALERT_HANDLER_ALERT_CAUSE_22
+    4'b 0001, // index[146] ALERT_HANDLER_ALERT_CAUSE_23
+    4'b 0001, // index[147] ALERT_HANDLER_ALERT_CAUSE_24
+    4'b 0001, // index[148] ALERT_HANDLER_ALERT_CAUSE_25
+    4'b 0001, // index[149] ALERT_HANDLER_ALERT_CAUSE_26
+    4'b 0001, // index[150] ALERT_HANDLER_ALERT_CAUSE_27
+    4'b 0001, // index[151] ALERT_HANDLER_ALERT_CAUSE_28
+    4'b 0001, // index[152] ALERT_HANDLER_ALERT_CAUSE_29
+    4'b 0001, // index[153] ALERT_HANDLER_ALERT_CAUSE_30
+    4'b 0001, // index[154] ALERT_HANDLER_ALERT_CAUSE_31
+    4'b 0001, // index[155] ALERT_HANDLER_ALERT_CAUSE_32
+    4'b 0001, // index[156] ALERT_HANDLER_ALERT_CAUSE_33
+    4'b 0001, // index[157] ALERT_HANDLER_ALERT_CAUSE_34
+    4'b 0001, // index[158] ALERT_HANDLER_ALERT_CAUSE_35
+    4'b 0001, // index[159] ALERT_HANDLER_ALERT_CAUSE_36
+    4'b 0001, // index[160] ALERT_HANDLER_ALERT_CAUSE_37
+    4'b 0001, // index[161] ALERT_HANDLER_ALERT_CAUSE_38
+    4'b 0001, // index[162] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+    4'b 0001, // index[163] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+    4'b 0001, // index[164] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+    4'b 0001, // index[165] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+    4'b 0001, // index[166] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+    4'b 0001, // index[167] ALERT_HANDLER_LOC_ALERT_REGWEN_5
+    4'b 0001, // index[168] ALERT_HANDLER_LOC_ALERT_REGWEN_6
+    4'b 0001, // index[169] ALERT_HANDLER_LOC_ALERT_REGWEN_7
+    4'b 0001, // index[170] ALERT_HANDLER_LOC_ALERT_REGWEN_8
+    4'b 0001, // index[171] ALERT_HANDLER_LOC_ALERT_REGWEN_9
+    4'b 0001, // index[172] ALERT_HANDLER_LOC_ALERT_REGWEN_10
+    4'b 0001, // index[173] ALERT_HANDLER_LOC_ALERT_REGWEN_11
+    4'b 0001, // index[174] ALERT_HANDLER_LOC_ALERT_REGWEN_12
+    4'b 0001, // index[175] ALERT_HANDLER_LOC_ALERT_REGWEN_13
+    4'b 0001, // index[176] ALERT_HANDLER_LOC_ALERT_REGWEN_14
+    4'b 0001, // index[177] ALERT_HANDLER_LOC_ALERT_REGWEN_15
+    4'b 0001, // index[178] ALERT_HANDLER_LOC_ALERT_REGWEN_16
+    4'b 0001, // index[179] ALERT_HANDLER_LOC_ALERT_REGWEN_17
+    4'b 0001, // index[180] ALERT_HANDLER_LOC_ALERT_REGWEN_18
+    4'b 0001, // index[181] ALERT_HANDLER_LOC_ALERT_REGWEN_19
+    4'b 0001, // index[182] ALERT_HANDLER_LOC_ALERT_REGWEN_20
+    4'b 0001, // index[183] ALERT_HANDLER_LOC_ALERT_REGWEN_21
+    4'b 0001, // index[184] ALERT_HANDLER_LOC_ALERT_REGWEN_22
+    4'b 0001, // index[185] ALERT_HANDLER_LOC_ALERT_REGWEN_23
+    4'b 0001, // index[186] ALERT_HANDLER_LOC_ALERT_REGWEN_24
+    4'b 0001, // index[187] ALERT_HANDLER_LOC_ALERT_REGWEN_25
+    4'b 0001, // index[188] ALERT_HANDLER_LOC_ALERT_REGWEN_26
+    4'b 0001, // index[189] ALERT_HANDLER_LOC_ALERT_REGWEN_27
+    4'b 0001, // index[190] ALERT_HANDLER_LOC_ALERT_REGWEN_28
+    4'b 0001, // index[191] ALERT_HANDLER_LOC_ALERT_REGWEN_29
+    4'b 0001, // index[192] ALERT_HANDLER_LOC_ALERT_REGWEN_30
+    4'b 0001, // index[193] ALERT_HANDLER_LOC_ALERT_REGWEN_31
+    4'b 0001, // index[194] ALERT_HANDLER_LOC_ALERT_REGWEN_32
+    4'b 0001, // index[195] ALERT_HANDLER_LOC_ALERT_REGWEN_33
+    4'b 0001, // index[196] ALERT_HANDLER_LOC_ALERT_REGWEN_34
+    4'b 0001, // index[197] ALERT_HANDLER_LOC_ALERT_REGWEN_35
+    4'b 0001, // index[198] ALERT_HANDLER_LOC_ALERT_REGWEN_36
+    4'b 0001, // index[199] ALERT_HANDLER_LOC_ALERT_REGWEN_37
+    4'b 0001, // index[200] ALERT_HANDLER_LOC_ALERT_REGWEN_38
+    4'b 0001, // index[201] ALERT_HANDLER_LOC_ALERT_EN_0
+    4'b 0001, // index[202] ALERT_HANDLER_LOC_ALERT_EN_1
+    4'b 0001, // index[203] ALERT_HANDLER_LOC_ALERT_EN_2
+    4'b 0001, // index[204] ALERT_HANDLER_LOC_ALERT_EN_3
+    4'b 0001, // index[205] ALERT_HANDLER_LOC_ALERT_CLASS_0
+    4'b 0001, // index[206] ALERT_HANDLER_LOC_ALERT_CLASS_1
+    4'b 0001, // index[207] ALERT_HANDLER_LOC_ALERT_CLASS_2
+    4'b 0001, // index[208] ALERT_HANDLER_LOC_ALERT_CLASS_3
+    4'b 0001, // index[209] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+    4'b 0001, // index[210] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+    4'b 0001, // index[211] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+    4'b 0001, // index[212] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+    4'b 0001, // index[213] ALERT_HANDLER_CLASSA_REGWEN
+    4'b 0011, // index[214] ALERT_HANDLER_CLASSA_CTRL
+    4'b 0001, // index[215] ALERT_HANDLER_CLASSA_CLR_REGWEN
+    4'b 0001, // index[216] ALERT_HANDLER_CLASSA_CLR
+    4'b 0011, // index[217] ALERT_HANDLER_CLASSA_ACCUM_CNT
+    4'b 0011, // index[218] ALERT_HANDLER_CLASSA_ACCUM_THRESH
+    4'b 1111, // index[219] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
+    4'b 1111, // index[220] ALERT_HANDLER_CLASSA_PHASE0_CYC
+    4'b 1111, // index[221] ALERT_HANDLER_CLASSA_PHASE1_CYC
+    4'b 1111, // index[222] ALERT_HANDLER_CLASSA_PHASE2_CYC
+    4'b 1111, // index[223] ALERT_HANDLER_CLASSA_PHASE3_CYC
+    4'b 1111, // index[224] ALERT_HANDLER_CLASSA_ESC_CNT
+    4'b 0001, // index[225] ALERT_HANDLER_CLASSA_STATE
+    4'b 0001, // index[226] ALERT_HANDLER_CLASSB_REGWEN
+    4'b 0011, // index[227] ALERT_HANDLER_CLASSB_CTRL
+    4'b 0001, // index[228] ALERT_HANDLER_CLASSB_CLR_REGWEN
+    4'b 0001, // index[229] ALERT_HANDLER_CLASSB_CLR
+    4'b 0011, // index[230] ALERT_HANDLER_CLASSB_ACCUM_CNT
+    4'b 0011, // index[231] ALERT_HANDLER_CLASSB_ACCUM_THRESH
+    4'b 1111, // index[232] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
+    4'b 1111, // index[233] ALERT_HANDLER_CLASSB_PHASE0_CYC
+    4'b 1111, // index[234] ALERT_HANDLER_CLASSB_PHASE1_CYC
+    4'b 1111, // index[235] ALERT_HANDLER_CLASSB_PHASE2_CYC
+    4'b 1111, // index[236] ALERT_HANDLER_CLASSB_PHASE3_CYC
+    4'b 1111, // index[237] ALERT_HANDLER_CLASSB_ESC_CNT
+    4'b 0001, // index[238] ALERT_HANDLER_CLASSB_STATE
+    4'b 0001, // index[239] ALERT_HANDLER_CLASSC_REGWEN
+    4'b 0011, // index[240] ALERT_HANDLER_CLASSC_CTRL
+    4'b 0001, // index[241] ALERT_HANDLER_CLASSC_CLR_REGWEN
+    4'b 0001, // index[242] ALERT_HANDLER_CLASSC_CLR
+    4'b 0011, // index[243] ALERT_HANDLER_CLASSC_ACCUM_CNT
+    4'b 0011, // index[244] ALERT_HANDLER_CLASSC_ACCUM_THRESH
+    4'b 1111, // index[245] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
+    4'b 1111, // index[246] ALERT_HANDLER_CLASSC_PHASE0_CYC
+    4'b 1111, // index[247] ALERT_HANDLER_CLASSC_PHASE1_CYC
+    4'b 1111, // index[248] ALERT_HANDLER_CLASSC_PHASE2_CYC
+    4'b 1111, // index[249] ALERT_HANDLER_CLASSC_PHASE3_CYC
+    4'b 1111, // index[250] ALERT_HANDLER_CLASSC_ESC_CNT
+    4'b 0001, // index[251] ALERT_HANDLER_CLASSC_STATE
+    4'b 0001, // index[252] ALERT_HANDLER_CLASSD_REGWEN
+    4'b 0011, // index[253] ALERT_HANDLER_CLASSD_CTRL
+    4'b 0001, // index[254] ALERT_HANDLER_CLASSD_CLR_REGWEN
+    4'b 0001, // index[255] ALERT_HANDLER_CLASSD_CLR
+    4'b 0011, // index[256] ALERT_HANDLER_CLASSD_ACCUM_CNT
+    4'b 0011, // index[257] ALERT_HANDLER_CLASSD_ACCUM_THRESH
+    4'b 1111, // index[258] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
+    4'b 1111, // index[259] ALERT_HANDLER_CLASSD_PHASE0_CYC
+    4'b 1111, // index[260] ALERT_HANDLER_CLASSD_PHASE1_CYC
+    4'b 1111, // index[261] ALERT_HANDLER_CLASSD_PHASE2_CYC
+    4'b 1111, // index[262] ALERT_HANDLER_CLASSD_PHASE3_CYC
+    4'b 1111, // index[263] ALERT_HANDLER_CLASSD_ESC_CNT
+    4'b 0001  // index[264] ALERT_HANDLER_CLASSD_STATE
   };
 
 endpackage

diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index 7d30360..74af3f5 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv

@@ -25,7 +25,7 @@
 
   import alert_handler_reg_pkg::* ;
 
-  localparam int AW = 10;
+  localparam int AW = 11;
   localparam int DW = 32;
   localparam int DBW = DW/8;                    // Byte Width
 
@@ -256,6 +256,12 @@
   logic alert_regwen_36_qs;
   logic alert_regwen_36_wd;
   logic alert_regwen_36_we;
+  logic alert_regwen_37_qs;
+  logic alert_regwen_37_wd;
+  logic alert_regwen_37_we;
+  logic alert_regwen_38_qs;
+  logic alert_regwen_38_wd;
+  logic alert_regwen_38_we;
   logic alert_en_0_qs;
   logic alert_en_0_wd;
   logic alert_en_0_we;
@@ -367,6 +373,12 @@
   logic alert_en_36_qs;
   logic alert_en_36_wd;
   logic alert_en_36_we;
+  logic alert_en_37_qs;
+  logic alert_en_37_wd;
+  logic alert_en_37_we;
+  logic alert_en_38_qs;
+  logic alert_en_38_wd;
+  logic alert_en_38_we;
   logic [1:0] alert_class_0_qs;
   logic [1:0] alert_class_0_wd;
   logic alert_class_0_we;
@@ -478,6 +490,12 @@
   logic [1:0] alert_class_36_qs;
   logic [1:0] alert_class_36_wd;
   logic alert_class_36_we;
+  logic [1:0] alert_class_37_qs;
+  logic [1:0] alert_class_37_wd;
+  logic alert_class_37_we;
+  logic [1:0] alert_class_38_qs;
+  logic [1:0] alert_class_38_wd;
+  logic alert_class_38_we;
   logic alert_cause_0_qs;
   logic alert_cause_0_wd;
   logic alert_cause_0_we;
@@ -589,6 +607,12 @@
   logic alert_cause_36_qs;
   logic alert_cause_36_wd;
   logic alert_cause_36_we;
+  logic alert_cause_37_qs;
+  logic alert_cause_37_wd;
+  logic alert_cause_37_we;
+  logic alert_cause_38_qs;
+  logic alert_cause_38_wd;
+  logic alert_cause_38_we;
   logic loc_alert_regwen_0_qs;
   logic loc_alert_regwen_0_wd;
   logic loc_alert_regwen_0_we;
@@ -700,6 +724,12 @@
   logic loc_alert_regwen_36_qs;
   logic loc_alert_regwen_36_wd;
   logic loc_alert_regwen_36_we;
+  logic loc_alert_regwen_37_qs;
+  logic loc_alert_regwen_37_wd;
+  logic loc_alert_regwen_37_we;
+  logic loc_alert_regwen_38_qs;
+  logic loc_alert_regwen_38_wd;
+  logic loc_alert_regwen_38_we;
   logic loc_alert_en_0_qs;
   logic loc_alert_en_0_wd;
   logic loc_alert_en_0_we;
@@ -2341,6 +2371,60 @@
     .qs     (alert_regwen_36_qs)
   );
 
+  // Subregister 37 of Multireg alert_regwen
+  // R[alert_regwen_37]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_alert_regwen_37 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (alert_regwen_37_we),
+    .wd     (alert_regwen_37_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_regwen[37].q ),
+
+    // to register interface (read)
+    .qs     (alert_regwen_37_qs)
+  );
+
+  // Subregister 38 of Multireg alert_regwen
+  // R[alert_regwen_38]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_alert_regwen_38 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (alert_regwen_38_we),
+    .wd     (alert_regwen_38_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_regwen[38].q ),
+
+    // to register interface (read)
+    .qs     (alert_regwen_38_qs)
+  );
+
 
 
   // Subregister 0 of Multireg alert_en
@@ -3342,6 +3426,60 @@
     .qs     (alert_en_36_qs)
   );
 
+  // Subregister 37 of Multireg alert_en
+  // R[alert_en_37]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_alert_en_37 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (alert_en_37_we & alert_regwen_37_qs),
+    .wd     (alert_en_37_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_en[37].q ),
+
+    // to register interface (read)
+    .qs     (alert_en_37_qs)
+  );
+
+  // Subregister 38 of Multireg alert_en
+  // R[alert_en_38]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_alert_en_38 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (alert_en_38_we & alert_regwen_38_qs),
+    .wd     (alert_en_38_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_en[38].q ),
+
+    // to register interface (read)
+    .qs     (alert_en_38_qs)
+  );
+
 
 
   // Subregister 0 of Multireg alert_class
@@ -4343,6 +4481,60 @@
     .qs     (alert_class_36_qs)
   );
 
+  // Subregister 37 of Multireg alert_class
+  // R[alert_class_37]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_alert_class_37 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (alert_class_37_we & alert_regwen_37_qs),
+    .wd     (alert_class_37_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_class[37].q ),
+
+    // to register interface (read)
+    .qs     (alert_class_37_qs)
+  );
+
+  // Subregister 38 of Multireg alert_class
+  // R[alert_class_38]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_alert_class_38 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (alert_class_38_we & alert_regwen_38_qs),
+    .wd     (alert_class_38_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_class[38].q ),
+
+    // to register interface (read)
+    .qs     (alert_class_38_qs)
+  );
+
 
 
   // Subregister 0 of Multireg alert_cause
@@ -5344,6 +5536,60 @@
     .qs     (alert_cause_36_qs)
   );
 
+  // Subregister 37 of Multireg alert_cause
+  // R[alert_cause_37]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_alert_cause_37 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (alert_cause_37_we),
+    .wd     (alert_cause_37_wd),
+
+    // from internal hardware
+    .de     (hw2reg.alert_cause[37].de),
+    .d      (hw2reg.alert_cause[37].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_cause[37].q ),
+
+    // to register interface (read)
+    .qs     (alert_cause_37_qs)
+  );
+
+  // Subregister 38 of Multireg alert_cause
+  // R[alert_cause_38]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_alert_cause_38 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (alert_cause_38_we),
+    .wd     (alert_cause_38_wd),
+
+    // from internal hardware
+    .de     (hw2reg.alert_cause[38].de),
+    .d      (hw2reg.alert_cause[38].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_cause[38].q ),
+
+    // to register interface (read)
+    .qs     (alert_cause_38_qs)
+  );
+
 
 
   // Subregister 0 of Multireg loc_alert_regwen
@@ -6345,6 +6591,60 @@
     .qs     (loc_alert_regwen_36_qs)
   );
 
+  // Subregister 37 of Multireg loc_alert_regwen
+  // R[loc_alert_regwen_37]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_loc_alert_regwen_37 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (loc_alert_regwen_37_we),
+    .wd     (loc_alert_regwen_37_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (loc_alert_regwen_37_qs)
+  );
+
+  // Subregister 38 of Multireg loc_alert_regwen
+  // R[loc_alert_regwen_38]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_loc_alert_regwen_38 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (loc_alert_regwen_38_we),
+    .wd     (loc_alert_regwen_38_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (loc_alert_regwen_38_qs)
+  );
+
 
 
   // Subregister 0 of Multireg loc_alert_en
@@ -8886,7 +9186,7 @@
 
 
 
-  logic [254:0] addr_hit;
+  logic [264:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[  0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
@@ -8932,218 +9232,228 @@
     addr_hit[ 40] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_34_OFFSET);
     addr_hit[ 41] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_35_OFFSET);
     addr_hit[ 42] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_36_OFFSET);
-    addr_hit[ 43] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
-    addr_hit[ 44] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
-    addr_hit[ 45] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
-    addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
-    addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
-    addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
-    addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
-    addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
-    addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
-    addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
-    addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
-    addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
-    addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
-    addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
-    addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
-    addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
-    addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
-    addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
-    addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
-    addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
-    addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
-    addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
-    addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
-    addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
-    addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
-    addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
-    addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
-    addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
-    addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
-    addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
-    addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
-    addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
-    addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
-    addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
-    addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
-    addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
-    addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
-    addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
-    addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
-    addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
-    addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
-    addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
-    addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
-    addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
-    addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
-    addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
-    addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
-    addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
-    addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
-    addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
-    addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
-    addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
-    addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
-    addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
-    addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
-    addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
-    addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
-    addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
-    addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
-    addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
-    addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
-    addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
-    addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
-    addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
-    addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
-    addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
-    addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
-    addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
-    addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
-    addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
-    addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
-    addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
-    addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
-    addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
-    addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
-    addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
-    addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
-    addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
-    addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
-    addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
-    addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
-    addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
-    addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
-    addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
-    addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
-    addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
-    addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
-    addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
-    addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
-    addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
-    addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
-    addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
-    addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
-    addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
-    addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
-    addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
-    addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
-    addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
-    addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
-    addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
-    addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
-    addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
-    addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
-    addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
-    addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
-    addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
-    addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
-    addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
-    addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
-    addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
-    addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
-    addr_hit[154] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
-    addr_hit[155] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
-    addr_hit[156] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
-    addr_hit[157] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
-    addr_hit[158] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
-    addr_hit[159] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
-    addr_hit[160] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
-    addr_hit[161] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_7_OFFSET);
-    addr_hit[162] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_8_OFFSET);
-    addr_hit[163] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_9_OFFSET);
-    addr_hit[164] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_10_OFFSET);
-    addr_hit[165] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_11_OFFSET);
-    addr_hit[166] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_12_OFFSET);
-    addr_hit[167] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_13_OFFSET);
-    addr_hit[168] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_14_OFFSET);
-    addr_hit[169] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_15_OFFSET);
-    addr_hit[170] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_16_OFFSET);
-    addr_hit[171] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_17_OFFSET);
-    addr_hit[172] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_18_OFFSET);
-    addr_hit[173] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_19_OFFSET);
-    addr_hit[174] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_20_OFFSET);
-    addr_hit[175] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_21_OFFSET);
-    addr_hit[176] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_22_OFFSET);
-    addr_hit[177] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_23_OFFSET);
-    addr_hit[178] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_24_OFFSET);
-    addr_hit[179] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_25_OFFSET);
-    addr_hit[180] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_26_OFFSET);
-    addr_hit[181] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_27_OFFSET);
-    addr_hit[182] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_28_OFFSET);
-    addr_hit[183] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_29_OFFSET);
-    addr_hit[184] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_30_OFFSET);
-    addr_hit[185] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_31_OFFSET);
-    addr_hit[186] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_32_OFFSET);
-    addr_hit[187] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_33_OFFSET);
-    addr_hit[188] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_34_OFFSET);
-    addr_hit[189] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_35_OFFSET);
-    addr_hit[190] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_36_OFFSET);
-    addr_hit[191] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
-    addr_hit[192] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
-    addr_hit[193] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
-    addr_hit[194] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
-    addr_hit[195] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
-    addr_hit[196] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
-    addr_hit[197] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
-    addr_hit[198] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
-    addr_hit[199] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
-    addr_hit[200] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
-    addr_hit[201] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
-    addr_hit[202] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
-    addr_hit[203] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
-    addr_hit[204] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
-    addr_hit[205] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
-    addr_hit[206] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
-    addr_hit[207] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
-    addr_hit[208] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
-    addr_hit[209] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
-    addr_hit[210] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
-    addr_hit[211] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
-    addr_hit[212] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
-    addr_hit[213] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
-    addr_hit[214] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
-    addr_hit[215] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
-    addr_hit[216] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
-    addr_hit[217] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
-    addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
-    addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
-    addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
-    addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
-    addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
-    addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
-    addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
-    addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
-    addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
-    addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
-    addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
-    addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
-    addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
-    addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
-    addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
-    addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
-    addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
-    addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
-    addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
-    addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
-    addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
-    addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
-    addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
-    addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
-    addr_hit[242] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
-    addr_hit[243] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
-    addr_hit[244] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
-    addr_hit[245] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
-    addr_hit[246] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
-    addr_hit[247] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
-    addr_hit[248] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
-    addr_hit[249] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
-    addr_hit[250] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
-    addr_hit[251] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
-    addr_hit[252] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
-    addr_hit[253] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
-    addr_hit[254] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+    addr_hit[ 43] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_37_OFFSET);
+    addr_hit[ 44] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_38_OFFSET);
+    addr_hit[ 45] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
+    addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
+    addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
+    addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
+    addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
+    addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
+    addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
+    addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
+    addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
+    addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
+    addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
+    addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
+    addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
+    addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
+    addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
+    addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
+    addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
+    addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
+    addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
+    addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
+    addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
+    addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
+    addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
+    addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
+    addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
+    addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
+    addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
+    addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
+    addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
+    addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
+    addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
+    addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
+    addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
+    addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
+    addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
+    addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
+    addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
+    addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET);
+    addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET);
+    addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
+    addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
+    addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
+    addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
+    addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
+    addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
+    addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
+    addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
+    addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
+    addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
+    addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
+    addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
+    addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
+    addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
+    addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
+    addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
+    addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
+    addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
+    addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
+    addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
+    addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
+    addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
+    addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
+    addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
+    addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
+    addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
+    addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
+    addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
+    addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
+    addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
+    addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
+    addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
+    addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
+    addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
+    addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
+    addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
+    addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
+    addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET);
+    addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET);
+    addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+    addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+    addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+    addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+    addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+    addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+    addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+    addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+    addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+    addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+    addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+    addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+    addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+    addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+    addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+    addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+    addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+    addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+    addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+    addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+    addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+    addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+    addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+    addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+    addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+    addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+    addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+    addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+    addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+    addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+    addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+    addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+    addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+    addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+    addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+    addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+    addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+    addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+    addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+    addr_hit[162] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+    addr_hit[163] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+    addr_hit[164] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+    addr_hit[165] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+    addr_hit[166] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+    addr_hit[167] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
+    addr_hit[168] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
+    addr_hit[169] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_7_OFFSET);
+    addr_hit[170] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_8_OFFSET);
+    addr_hit[171] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_9_OFFSET);
+    addr_hit[172] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_10_OFFSET);
+    addr_hit[173] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_11_OFFSET);
+    addr_hit[174] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_12_OFFSET);
+    addr_hit[175] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_13_OFFSET);
+    addr_hit[176] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_14_OFFSET);
+    addr_hit[177] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_15_OFFSET);
+    addr_hit[178] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_16_OFFSET);
+    addr_hit[179] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_17_OFFSET);
+    addr_hit[180] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_18_OFFSET);
+    addr_hit[181] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_19_OFFSET);
+    addr_hit[182] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_20_OFFSET);
+    addr_hit[183] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_21_OFFSET);
+    addr_hit[184] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_22_OFFSET);
+    addr_hit[185] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_23_OFFSET);
+    addr_hit[186] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_24_OFFSET);
+    addr_hit[187] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_25_OFFSET);
+    addr_hit[188] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_26_OFFSET);
+    addr_hit[189] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_27_OFFSET);
+    addr_hit[190] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_28_OFFSET);
+    addr_hit[191] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_29_OFFSET);
+    addr_hit[192] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_30_OFFSET);
+    addr_hit[193] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_31_OFFSET);
+    addr_hit[194] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_32_OFFSET);
+    addr_hit[195] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_33_OFFSET);
+    addr_hit[196] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_34_OFFSET);
+    addr_hit[197] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_35_OFFSET);
+    addr_hit[198] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_36_OFFSET);
+    addr_hit[199] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_37_OFFSET);
+    addr_hit[200] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_38_OFFSET);
+    addr_hit[201] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
+    addr_hit[202] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
+    addr_hit[203] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
+    addr_hit[204] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
+    addr_hit[205] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
+    addr_hit[206] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
+    addr_hit[207] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
+    addr_hit[208] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
+    addr_hit[209] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+    addr_hit[210] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+    addr_hit[211] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+    addr_hit[212] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+    addr_hit[213] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+    addr_hit[214] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
+    addr_hit[215] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+    addr_hit[216] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
+    addr_hit[217] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+    addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
+    addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
+    addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
+    addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
+    addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
+    addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
+    addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+    addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+    addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+    addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
+    addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+    addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
+    addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+    addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
+    addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
+    addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
+    addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
+    addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
+    addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
+    addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+    addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+    addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+    addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
+    addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+    addr_hit[242] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
+    addr_hit[243] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+    addr_hit[244] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
+    addr_hit[245] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
+    addr_hit[246] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
+    addr_hit[247] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
+    addr_hit[248] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
+    addr_hit[249] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
+    addr_hit[250] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+    addr_hit[251] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+    addr_hit[252] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+    addr_hit[253] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
+    addr_hit[254] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+    addr_hit[255] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
+    addr_hit[256] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+    addr_hit[257] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
+    addr_hit[258] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
+    addr_hit[259] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
+    addr_hit[260] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
+    addr_hit[261] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
+    addr_hit[262] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
+    addr_hit[263] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+    addr_hit[264] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -9405,7 +9715,17 @@
                (addr_hit[251] & (|(ALERT_HANDLER_PERMIT[251] & ~reg_be))) |
                (addr_hit[252] & (|(ALERT_HANDLER_PERMIT[252] & ~reg_be))) |
                (addr_hit[253] & (|(ALERT_HANDLER_PERMIT[253] & ~reg_be))) |
-               (addr_hit[254] & (|(ALERT_HANDLER_PERMIT[254] & ~reg_be)))));
+               (addr_hit[254] & (|(ALERT_HANDLER_PERMIT[254] & ~reg_be))) |
+               (addr_hit[255] & (|(ALERT_HANDLER_PERMIT[255] & ~reg_be))) |
+               (addr_hit[256] & (|(ALERT_HANDLER_PERMIT[256] & ~reg_be))) |
+               (addr_hit[257] & (|(ALERT_HANDLER_PERMIT[257] & ~reg_be))) |
+               (addr_hit[258] & (|(ALERT_HANDLER_PERMIT[258] & ~reg_be))) |
+               (addr_hit[259] & (|(ALERT_HANDLER_PERMIT[259] & ~reg_be))) |
+               (addr_hit[260] & (|(ALERT_HANDLER_PERMIT[260] & ~reg_be))) |
+               (addr_hit[261] & (|(ALERT_HANDLER_PERMIT[261] & ~reg_be))) |
+               (addr_hit[262] & (|(ALERT_HANDLER_PERMIT[262] & ~reg_be))) |
+               (addr_hit[263] & (|(ALERT_HANDLER_PERMIT[263] & ~reg_be))) |
+               (addr_hit[264] & (|(ALERT_HANDLER_PERMIT[264] & ~reg_be)))));
   end
 
   assign intr_state_classa_we = addr_hit[0] & reg_we & !reg_error;
@@ -9564,737 +9884,767 @@
   assign alert_regwen_36_we = addr_hit[42] & reg_we & !reg_error;
   assign alert_regwen_36_wd = reg_wdata[0];
 
-  assign alert_en_0_we = addr_hit[43] & reg_we & !reg_error;
+  assign alert_regwen_37_we = addr_hit[43] & reg_we & !reg_error;
+  assign alert_regwen_37_wd = reg_wdata[0];
+
+  assign alert_regwen_38_we = addr_hit[44] & reg_we & !reg_error;
+  assign alert_regwen_38_wd = reg_wdata[0];
+
+  assign alert_en_0_we = addr_hit[45] & reg_we & !reg_error;
   assign alert_en_0_wd = reg_wdata[0];
 
-  assign alert_en_1_we = addr_hit[44] & reg_we & !reg_error;
+  assign alert_en_1_we = addr_hit[46] & reg_we & !reg_error;
   assign alert_en_1_wd = reg_wdata[0];
 
-  assign alert_en_2_we = addr_hit[45] & reg_we & !reg_error;
+  assign alert_en_2_we = addr_hit[47] & reg_we & !reg_error;
   assign alert_en_2_wd = reg_wdata[0];
 
-  assign alert_en_3_we = addr_hit[46] & reg_we & !reg_error;
+  assign alert_en_3_we = addr_hit[48] & reg_we & !reg_error;
   assign alert_en_3_wd = reg_wdata[0];
 
-  assign alert_en_4_we = addr_hit[47] & reg_we & !reg_error;
+  assign alert_en_4_we = addr_hit[49] & reg_we & !reg_error;
   assign alert_en_4_wd = reg_wdata[0];
 
-  assign alert_en_5_we = addr_hit[48] & reg_we & !reg_error;
+  assign alert_en_5_we = addr_hit[50] & reg_we & !reg_error;
   assign alert_en_5_wd = reg_wdata[0];
 
-  assign alert_en_6_we = addr_hit[49] & reg_we & !reg_error;
+  assign alert_en_6_we = addr_hit[51] & reg_we & !reg_error;
   assign alert_en_6_wd = reg_wdata[0];
 
-  assign alert_en_7_we = addr_hit[50] & reg_we & !reg_error;
+  assign alert_en_7_we = addr_hit[52] & reg_we & !reg_error;
   assign alert_en_7_wd = reg_wdata[0];
 
-  assign alert_en_8_we = addr_hit[51] & reg_we & !reg_error;
+  assign alert_en_8_we = addr_hit[53] & reg_we & !reg_error;
   assign alert_en_8_wd = reg_wdata[0];
 
-  assign alert_en_9_we = addr_hit[52] & reg_we & !reg_error;
+  assign alert_en_9_we = addr_hit[54] & reg_we & !reg_error;
   assign alert_en_9_wd = reg_wdata[0];
 
-  assign alert_en_10_we = addr_hit[53] & reg_we & !reg_error;
+  assign alert_en_10_we = addr_hit[55] & reg_we & !reg_error;
   assign alert_en_10_wd = reg_wdata[0];
 
-  assign alert_en_11_we = addr_hit[54] & reg_we & !reg_error;
+  assign alert_en_11_we = addr_hit[56] & reg_we & !reg_error;
   assign alert_en_11_wd = reg_wdata[0];
 
-  assign alert_en_12_we = addr_hit[55] & reg_we & !reg_error;
+  assign alert_en_12_we = addr_hit[57] & reg_we & !reg_error;
   assign alert_en_12_wd = reg_wdata[0];
 
-  assign alert_en_13_we = addr_hit[56] & reg_we & !reg_error;
+  assign alert_en_13_we = addr_hit[58] & reg_we & !reg_error;
   assign alert_en_13_wd = reg_wdata[0];
 
-  assign alert_en_14_we = addr_hit[57] & reg_we & !reg_error;
+  assign alert_en_14_we = addr_hit[59] & reg_we & !reg_error;
   assign alert_en_14_wd = reg_wdata[0];
 
-  assign alert_en_15_we = addr_hit[58] & reg_we & !reg_error;
+  assign alert_en_15_we = addr_hit[60] & reg_we & !reg_error;
   assign alert_en_15_wd = reg_wdata[0];
 
-  assign alert_en_16_we = addr_hit[59] & reg_we & !reg_error;
+  assign alert_en_16_we = addr_hit[61] & reg_we & !reg_error;
   assign alert_en_16_wd = reg_wdata[0];
 
-  assign alert_en_17_we = addr_hit[60] & reg_we & !reg_error;
+  assign alert_en_17_we = addr_hit[62] & reg_we & !reg_error;
   assign alert_en_17_wd = reg_wdata[0];
 
-  assign alert_en_18_we = addr_hit[61] & reg_we & !reg_error;
+  assign alert_en_18_we = addr_hit[63] & reg_we & !reg_error;
   assign alert_en_18_wd = reg_wdata[0];
 
-  assign alert_en_19_we = addr_hit[62] & reg_we & !reg_error;
+  assign alert_en_19_we = addr_hit[64] & reg_we & !reg_error;
   assign alert_en_19_wd = reg_wdata[0];
 
-  assign alert_en_20_we = addr_hit[63] & reg_we & !reg_error;
+  assign alert_en_20_we = addr_hit[65] & reg_we & !reg_error;
   assign alert_en_20_wd = reg_wdata[0];
 
-  assign alert_en_21_we = addr_hit[64] & reg_we & !reg_error;
+  assign alert_en_21_we = addr_hit[66] & reg_we & !reg_error;
   assign alert_en_21_wd = reg_wdata[0];
 
-  assign alert_en_22_we = addr_hit[65] & reg_we & !reg_error;
+  assign alert_en_22_we = addr_hit[67] & reg_we & !reg_error;
   assign alert_en_22_wd = reg_wdata[0];
 
-  assign alert_en_23_we = addr_hit[66] & reg_we & !reg_error;
+  assign alert_en_23_we = addr_hit[68] & reg_we & !reg_error;
   assign alert_en_23_wd = reg_wdata[0];
 
-  assign alert_en_24_we = addr_hit[67] & reg_we & !reg_error;
+  assign alert_en_24_we = addr_hit[69] & reg_we & !reg_error;
   assign alert_en_24_wd = reg_wdata[0];
 
-  assign alert_en_25_we = addr_hit[68] & reg_we & !reg_error;
+  assign alert_en_25_we = addr_hit[70] & reg_we & !reg_error;
   assign alert_en_25_wd = reg_wdata[0];
 
-  assign alert_en_26_we = addr_hit[69] & reg_we & !reg_error;
+  assign alert_en_26_we = addr_hit[71] & reg_we & !reg_error;
   assign alert_en_26_wd = reg_wdata[0];
 
-  assign alert_en_27_we = addr_hit[70] & reg_we & !reg_error;
+  assign alert_en_27_we = addr_hit[72] & reg_we & !reg_error;
   assign alert_en_27_wd = reg_wdata[0];
 
-  assign alert_en_28_we = addr_hit[71] & reg_we & !reg_error;
+  assign alert_en_28_we = addr_hit[73] & reg_we & !reg_error;
   assign alert_en_28_wd = reg_wdata[0];
 
-  assign alert_en_29_we = addr_hit[72] & reg_we & !reg_error;
+  assign alert_en_29_we = addr_hit[74] & reg_we & !reg_error;
   assign alert_en_29_wd = reg_wdata[0];
 
-  assign alert_en_30_we = addr_hit[73] & reg_we & !reg_error;
+  assign alert_en_30_we = addr_hit[75] & reg_we & !reg_error;
   assign alert_en_30_wd = reg_wdata[0];
 
-  assign alert_en_31_we = addr_hit[74] & reg_we & !reg_error;
+  assign alert_en_31_we = addr_hit[76] & reg_we & !reg_error;
   assign alert_en_31_wd = reg_wdata[0];
 
-  assign alert_en_32_we = addr_hit[75] & reg_we & !reg_error;
+  assign alert_en_32_we = addr_hit[77] & reg_we & !reg_error;
   assign alert_en_32_wd = reg_wdata[0];
 
-  assign alert_en_33_we = addr_hit[76] & reg_we & !reg_error;
+  assign alert_en_33_we = addr_hit[78] & reg_we & !reg_error;
   assign alert_en_33_wd = reg_wdata[0];
 
-  assign alert_en_34_we = addr_hit[77] & reg_we & !reg_error;
+  assign alert_en_34_we = addr_hit[79] & reg_we & !reg_error;
   assign alert_en_34_wd = reg_wdata[0];
 
-  assign alert_en_35_we = addr_hit[78] & reg_we & !reg_error;
+  assign alert_en_35_we = addr_hit[80] & reg_we & !reg_error;
   assign alert_en_35_wd = reg_wdata[0];
 
-  assign alert_en_36_we = addr_hit[79] & reg_we & !reg_error;
+  assign alert_en_36_we = addr_hit[81] & reg_we & !reg_error;
   assign alert_en_36_wd = reg_wdata[0];
 
-  assign alert_class_0_we = addr_hit[80] & reg_we & !reg_error;
+  assign alert_en_37_we = addr_hit[82] & reg_we & !reg_error;
+  assign alert_en_37_wd = reg_wdata[0];
+
+  assign alert_en_38_we = addr_hit[83] & reg_we & !reg_error;
+  assign alert_en_38_wd = reg_wdata[0];
+
+  assign alert_class_0_we = addr_hit[84] & reg_we & !reg_error;
   assign alert_class_0_wd = reg_wdata[1:0];
 
-  assign alert_class_1_we = addr_hit[81] & reg_we & !reg_error;
+  assign alert_class_1_we = addr_hit[85] & reg_we & !reg_error;
   assign alert_class_1_wd = reg_wdata[1:0];
 
-  assign alert_class_2_we = addr_hit[82] & reg_we & !reg_error;
+  assign alert_class_2_we = addr_hit[86] & reg_we & !reg_error;
   assign alert_class_2_wd = reg_wdata[1:0];
 
-  assign alert_class_3_we = addr_hit[83] & reg_we & !reg_error;
+  assign alert_class_3_we = addr_hit[87] & reg_we & !reg_error;
   assign alert_class_3_wd = reg_wdata[1:0];
 
-  assign alert_class_4_we = addr_hit[84] & reg_we & !reg_error;
+  assign alert_class_4_we = addr_hit[88] & reg_we & !reg_error;
   assign alert_class_4_wd = reg_wdata[1:0];
 
-  assign alert_class_5_we = addr_hit[85] & reg_we & !reg_error;
+  assign alert_class_5_we = addr_hit[89] & reg_we & !reg_error;
   assign alert_class_5_wd = reg_wdata[1:0];
 
-  assign alert_class_6_we = addr_hit[86] & reg_we & !reg_error;
+  assign alert_class_6_we = addr_hit[90] & reg_we & !reg_error;
   assign alert_class_6_wd = reg_wdata[1:0];
 
-  assign alert_class_7_we = addr_hit[87] & reg_we & !reg_error;
+  assign alert_class_7_we = addr_hit[91] & reg_we & !reg_error;
   assign alert_class_7_wd = reg_wdata[1:0];
 
-  assign alert_class_8_we = addr_hit[88] & reg_we & !reg_error;
+  assign alert_class_8_we = addr_hit[92] & reg_we & !reg_error;
   assign alert_class_8_wd = reg_wdata[1:0];
 
-  assign alert_class_9_we = addr_hit[89] & reg_we & !reg_error;
+  assign alert_class_9_we = addr_hit[93] & reg_we & !reg_error;
   assign alert_class_9_wd = reg_wdata[1:0];
 
-  assign alert_class_10_we = addr_hit[90] & reg_we & !reg_error;
+  assign alert_class_10_we = addr_hit[94] & reg_we & !reg_error;
   assign alert_class_10_wd = reg_wdata[1:0];
 
-  assign alert_class_11_we = addr_hit[91] & reg_we & !reg_error;
+  assign alert_class_11_we = addr_hit[95] & reg_we & !reg_error;
   assign alert_class_11_wd = reg_wdata[1:0];
 
-  assign alert_class_12_we = addr_hit[92] & reg_we & !reg_error;
+  assign alert_class_12_we = addr_hit[96] & reg_we & !reg_error;
   assign alert_class_12_wd = reg_wdata[1:0];
 
-  assign alert_class_13_we = addr_hit[93] & reg_we & !reg_error;
+  assign alert_class_13_we = addr_hit[97] & reg_we & !reg_error;
   assign alert_class_13_wd = reg_wdata[1:0];
 
-  assign alert_class_14_we = addr_hit[94] & reg_we & !reg_error;
+  assign alert_class_14_we = addr_hit[98] & reg_we & !reg_error;
   assign alert_class_14_wd = reg_wdata[1:0];
 
-  assign alert_class_15_we = addr_hit[95] & reg_we & !reg_error;
+  assign alert_class_15_we = addr_hit[99] & reg_we & !reg_error;
   assign alert_class_15_wd = reg_wdata[1:0];
 
-  assign alert_class_16_we = addr_hit[96] & reg_we & !reg_error;
+  assign alert_class_16_we = addr_hit[100] & reg_we & !reg_error;
   assign alert_class_16_wd = reg_wdata[1:0];
 
-  assign alert_class_17_we = addr_hit[97] & reg_we & !reg_error;
+  assign alert_class_17_we = addr_hit[101] & reg_we & !reg_error;
   assign alert_class_17_wd = reg_wdata[1:0];
 
-  assign alert_class_18_we = addr_hit[98] & reg_we & !reg_error;
+  assign alert_class_18_we = addr_hit[102] & reg_we & !reg_error;
   assign alert_class_18_wd = reg_wdata[1:0];
 
-  assign alert_class_19_we = addr_hit[99] & reg_we & !reg_error;
+  assign alert_class_19_we = addr_hit[103] & reg_we & !reg_error;
   assign alert_class_19_wd = reg_wdata[1:0];
 
-  assign alert_class_20_we = addr_hit[100] & reg_we & !reg_error;
+  assign alert_class_20_we = addr_hit[104] & reg_we & !reg_error;
   assign alert_class_20_wd = reg_wdata[1:0];
 
-  assign alert_class_21_we = addr_hit[101] & reg_we & !reg_error;
+  assign alert_class_21_we = addr_hit[105] & reg_we & !reg_error;
   assign alert_class_21_wd = reg_wdata[1:0];
 
-  assign alert_class_22_we = addr_hit[102] & reg_we & !reg_error;
+  assign alert_class_22_we = addr_hit[106] & reg_we & !reg_error;
   assign alert_class_22_wd = reg_wdata[1:0];
 
-  assign alert_class_23_we = addr_hit[103] & reg_we & !reg_error;
+  assign alert_class_23_we = addr_hit[107] & reg_we & !reg_error;
   assign alert_class_23_wd = reg_wdata[1:0];
 
-  assign alert_class_24_we = addr_hit[104] & reg_we & !reg_error;
+  assign alert_class_24_we = addr_hit[108] & reg_we & !reg_error;
   assign alert_class_24_wd = reg_wdata[1:0];
 
-  assign alert_class_25_we = addr_hit[105] & reg_we & !reg_error;
+  assign alert_class_25_we = addr_hit[109] & reg_we & !reg_error;
   assign alert_class_25_wd = reg_wdata[1:0];
 
-  assign alert_class_26_we = addr_hit[106] & reg_we & !reg_error;
+  assign alert_class_26_we = addr_hit[110] & reg_we & !reg_error;
   assign alert_class_26_wd = reg_wdata[1:0];
 
-  assign alert_class_27_we = addr_hit[107] & reg_we & !reg_error;
+  assign alert_class_27_we = addr_hit[111] & reg_we & !reg_error;
   assign alert_class_27_wd = reg_wdata[1:0];
 
-  assign alert_class_28_we = addr_hit[108] & reg_we & !reg_error;
+  assign alert_class_28_we = addr_hit[112] & reg_we & !reg_error;
   assign alert_class_28_wd = reg_wdata[1:0];
 
-  assign alert_class_29_we = addr_hit[109] & reg_we & !reg_error;
+  assign alert_class_29_we = addr_hit[113] & reg_we & !reg_error;
   assign alert_class_29_wd = reg_wdata[1:0];
 
-  assign alert_class_30_we = addr_hit[110] & reg_we & !reg_error;
+  assign alert_class_30_we = addr_hit[114] & reg_we & !reg_error;
   assign alert_class_30_wd = reg_wdata[1:0];
 
-  assign alert_class_31_we = addr_hit[111] & reg_we & !reg_error;
+  assign alert_class_31_we = addr_hit[115] & reg_we & !reg_error;
   assign alert_class_31_wd = reg_wdata[1:0];
 
-  assign alert_class_32_we = addr_hit[112] & reg_we & !reg_error;
+  assign alert_class_32_we = addr_hit[116] & reg_we & !reg_error;
   assign alert_class_32_wd = reg_wdata[1:0];
 
-  assign alert_class_33_we = addr_hit[113] & reg_we & !reg_error;
+  assign alert_class_33_we = addr_hit[117] & reg_we & !reg_error;
   assign alert_class_33_wd = reg_wdata[1:0];
 
-  assign alert_class_34_we = addr_hit[114] & reg_we & !reg_error;
+  assign alert_class_34_we = addr_hit[118] & reg_we & !reg_error;
   assign alert_class_34_wd = reg_wdata[1:0];
 
-  assign alert_class_35_we = addr_hit[115] & reg_we & !reg_error;
+  assign alert_class_35_we = addr_hit[119] & reg_we & !reg_error;
   assign alert_class_35_wd = reg_wdata[1:0];
 
-  assign alert_class_36_we = addr_hit[116] & reg_we & !reg_error;
+  assign alert_class_36_we = addr_hit[120] & reg_we & !reg_error;
   assign alert_class_36_wd = reg_wdata[1:0];
 
-  assign alert_cause_0_we = addr_hit[117] & reg_we & !reg_error;
+  assign alert_class_37_we = addr_hit[121] & reg_we & !reg_error;
+  assign alert_class_37_wd = reg_wdata[1:0];
+
+  assign alert_class_38_we = addr_hit[122] & reg_we & !reg_error;
+  assign alert_class_38_wd = reg_wdata[1:0];
+
+  assign alert_cause_0_we = addr_hit[123] & reg_we & !reg_error;
   assign alert_cause_0_wd = reg_wdata[0];
 
-  assign alert_cause_1_we = addr_hit[118] & reg_we & !reg_error;
+  assign alert_cause_1_we = addr_hit[124] & reg_we & !reg_error;
   assign alert_cause_1_wd = reg_wdata[0];
 
-  assign alert_cause_2_we = addr_hit[119] & reg_we & !reg_error;
+  assign alert_cause_2_we = addr_hit[125] & reg_we & !reg_error;
   assign alert_cause_2_wd = reg_wdata[0];
 
-  assign alert_cause_3_we = addr_hit[120] & reg_we & !reg_error;
+  assign alert_cause_3_we = addr_hit[126] & reg_we & !reg_error;
   assign alert_cause_3_wd = reg_wdata[0];
 
-  assign alert_cause_4_we = addr_hit[121] & reg_we & !reg_error;
+  assign alert_cause_4_we = addr_hit[127] & reg_we & !reg_error;
   assign alert_cause_4_wd = reg_wdata[0];
 
-  assign alert_cause_5_we = addr_hit[122] & reg_we & !reg_error;
+  assign alert_cause_5_we = addr_hit[128] & reg_we & !reg_error;
   assign alert_cause_5_wd = reg_wdata[0];
 
-  assign alert_cause_6_we = addr_hit[123] & reg_we & !reg_error;
+  assign alert_cause_6_we = addr_hit[129] & reg_we & !reg_error;
   assign alert_cause_6_wd = reg_wdata[0];
 
-  assign alert_cause_7_we = addr_hit[124] & reg_we & !reg_error;
+  assign alert_cause_7_we = addr_hit[130] & reg_we & !reg_error;
   assign alert_cause_7_wd = reg_wdata[0];
 
-  assign alert_cause_8_we = addr_hit[125] & reg_we & !reg_error;
+  assign alert_cause_8_we = addr_hit[131] & reg_we & !reg_error;
   assign alert_cause_8_wd = reg_wdata[0];
 
-  assign alert_cause_9_we = addr_hit[126] & reg_we & !reg_error;
+  assign alert_cause_9_we = addr_hit[132] & reg_we & !reg_error;
   assign alert_cause_9_wd = reg_wdata[0];
 
-  assign alert_cause_10_we = addr_hit[127] & reg_we & !reg_error;
+  assign alert_cause_10_we = addr_hit[133] & reg_we & !reg_error;
   assign alert_cause_10_wd = reg_wdata[0];
 
-  assign alert_cause_11_we = addr_hit[128] & reg_we & !reg_error;
+  assign alert_cause_11_we = addr_hit[134] & reg_we & !reg_error;
   assign alert_cause_11_wd = reg_wdata[0];
 
-  assign alert_cause_12_we = addr_hit[129] & reg_we & !reg_error;
+  assign alert_cause_12_we = addr_hit[135] & reg_we & !reg_error;
   assign alert_cause_12_wd = reg_wdata[0];
 
-  assign alert_cause_13_we = addr_hit[130] & reg_we & !reg_error;
+  assign alert_cause_13_we = addr_hit[136] & reg_we & !reg_error;
   assign alert_cause_13_wd = reg_wdata[0];
 
-  assign alert_cause_14_we = addr_hit[131] & reg_we & !reg_error;
+  assign alert_cause_14_we = addr_hit[137] & reg_we & !reg_error;
   assign alert_cause_14_wd = reg_wdata[0];
 
-  assign alert_cause_15_we = addr_hit[132] & reg_we & !reg_error;
+  assign alert_cause_15_we = addr_hit[138] & reg_we & !reg_error;
   assign alert_cause_15_wd = reg_wdata[0];
 
-  assign alert_cause_16_we = addr_hit[133] & reg_we & !reg_error;
+  assign alert_cause_16_we = addr_hit[139] & reg_we & !reg_error;
   assign alert_cause_16_wd = reg_wdata[0];
 
-  assign alert_cause_17_we = addr_hit[134] & reg_we & !reg_error;
+  assign alert_cause_17_we = addr_hit[140] & reg_we & !reg_error;
   assign alert_cause_17_wd = reg_wdata[0];
 
-  assign alert_cause_18_we = addr_hit[135] & reg_we & !reg_error;
+  assign alert_cause_18_we = addr_hit[141] & reg_we & !reg_error;
   assign alert_cause_18_wd = reg_wdata[0];
 
-  assign alert_cause_19_we = addr_hit[136] & reg_we & !reg_error;
+  assign alert_cause_19_we = addr_hit[142] & reg_we & !reg_error;
   assign alert_cause_19_wd = reg_wdata[0];
 
-  assign alert_cause_20_we = addr_hit[137] & reg_we & !reg_error;
+  assign alert_cause_20_we = addr_hit[143] & reg_we & !reg_error;
   assign alert_cause_20_wd = reg_wdata[0];
 
-  assign alert_cause_21_we = addr_hit[138] & reg_we & !reg_error;
+  assign alert_cause_21_we = addr_hit[144] & reg_we & !reg_error;
   assign alert_cause_21_wd = reg_wdata[0];
 
-  assign alert_cause_22_we = addr_hit[139] & reg_we & !reg_error;
+  assign alert_cause_22_we = addr_hit[145] & reg_we & !reg_error;
   assign alert_cause_22_wd = reg_wdata[0];
 
-  assign alert_cause_23_we = addr_hit[140] & reg_we & !reg_error;
+  assign alert_cause_23_we = addr_hit[146] & reg_we & !reg_error;
   assign alert_cause_23_wd = reg_wdata[0];
 
-  assign alert_cause_24_we = addr_hit[141] & reg_we & !reg_error;
+  assign alert_cause_24_we = addr_hit[147] & reg_we & !reg_error;
   assign alert_cause_24_wd = reg_wdata[0];
 
-  assign alert_cause_25_we = addr_hit[142] & reg_we & !reg_error;
+  assign alert_cause_25_we = addr_hit[148] & reg_we & !reg_error;
   assign alert_cause_25_wd = reg_wdata[0];
 
-  assign alert_cause_26_we = addr_hit[143] & reg_we & !reg_error;
+  assign alert_cause_26_we = addr_hit[149] & reg_we & !reg_error;
   assign alert_cause_26_wd = reg_wdata[0];
 
-  assign alert_cause_27_we = addr_hit[144] & reg_we & !reg_error;
+  assign alert_cause_27_we = addr_hit[150] & reg_we & !reg_error;
   assign alert_cause_27_wd = reg_wdata[0];
 
-  assign alert_cause_28_we = addr_hit[145] & reg_we & !reg_error;
+  assign alert_cause_28_we = addr_hit[151] & reg_we & !reg_error;
   assign alert_cause_28_wd = reg_wdata[0];
 
-  assign alert_cause_29_we = addr_hit[146] & reg_we & !reg_error;
+  assign alert_cause_29_we = addr_hit[152] & reg_we & !reg_error;
   assign alert_cause_29_wd = reg_wdata[0];
 
-  assign alert_cause_30_we = addr_hit[147] & reg_we & !reg_error;
+  assign alert_cause_30_we = addr_hit[153] & reg_we & !reg_error;
   assign alert_cause_30_wd = reg_wdata[0];
 
-  assign alert_cause_31_we = addr_hit[148] & reg_we & !reg_error;
+  assign alert_cause_31_we = addr_hit[154] & reg_we & !reg_error;
   assign alert_cause_31_wd = reg_wdata[0];
 
-  assign alert_cause_32_we = addr_hit[149] & reg_we & !reg_error;
+  assign alert_cause_32_we = addr_hit[155] & reg_we & !reg_error;
   assign alert_cause_32_wd = reg_wdata[0];
 
-  assign alert_cause_33_we = addr_hit[150] & reg_we & !reg_error;
+  assign alert_cause_33_we = addr_hit[156] & reg_we & !reg_error;
   assign alert_cause_33_wd = reg_wdata[0];
 
-  assign alert_cause_34_we = addr_hit[151] & reg_we & !reg_error;
+  assign alert_cause_34_we = addr_hit[157] & reg_we & !reg_error;
   assign alert_cause_34_wd = reg_wdata[0];
 
-  assign alert_cause_35_we = addr_hit[152] & reg_we & !reg_error;
+  assign alert_cause_35_we = addr_hit[158] & reg_we & !reg_error;
   assign alert_cause_35_wd = reg_wdata[0];
 
-  assign alert_cause_36_we = addr_hit[153] & reg_we & !reg_error;
+  assign alert_cause_36_we = addr_hit[159] & reg_we & !reg_error;
   assign alert_cause_36_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_0_we = addr_hit[154] & reg_we & !reg_error;
+  assign alert_cause_37_we = addr_hit[160] & reg_we & !reg_error;
+  assign alert_cause_37_wd = reg_wdata[0];
+
+  assign alert_cause_38_we = addr_hit[161] & reg_we & !reg_error;
+  assign alert_cause_38_wd = reg_wdata[0];
+
+  assign loc_alert_regwen_0_we = addr_hit[162] & reg_we & !reg_error;
   assign loc_alert_regwen_0_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_1_we = addr_hit[155] & reg_we & !reg_error;
+  assign loc_alert_regwen_1_we = addr_hit[163] & reg_we & !reg_error;
   assign loc_alert_regwen_1_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_2_we = addr_hit[156] & reg_we & !reg_error;
+  assign loc_alert_regwen_2_we = addr_hit[164] & reg_we & !reg_error;
   assign loc_alert_regwen_2_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_3_we = addr_hit[157] & reg_we & !reg_error;
+  assign loc_alert_regwen_3_we = addr_hit[165] & reg_we & !reg_error;
   assign loc_alert_regwen_3_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_4_we = addr_hit[158] & reg_we & !reg_error;
+  assign loc_alert_regwen_4_we = addr_hit[166] & reg_we & !reg_error;
   assign loc_alert_regwen_4_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_5_we = addr_hit[159] & reg_we & !reg_error;
+  assign loc_alert_regwen_5_we = addr_hit[167] & reg_we & !reg_error;
   assign loc_alert_regwen_5_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_6_we = addr_hit[160] & reg_we & !reg_error;
+  assign loc_alert_regwen_6_we = addr_hit[168] & reg_we & !reg_error;
   assign loc_alert_regwen_6_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_7_we = addr_hit[161] & reg_we & !reg_error;
+  assign loc_alert_regwen_7_we = addr_hit[169] & reg_we & !reg_error;
   assign loc_alert_regwen_7_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_8_we = addr_hit[162] & reg_we & !reg_error;
+  assign loc_alert_regwen_8_we = addr_hit[170] & reg_we & !reg_error;
   assign loc_alert_regwen_8_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_9_we = addr_hit[163] & reg_we & !reg_error;
+  assign loc_alert_regwen_9_we = addr_hit[171] & reg_we & !reg_error;
   assign loc_alert_regwen_9_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_10_we = addr_hit[164] & reg_we & !reg_error;
+  assign loc_alert_regwen_10_we = addr_hit[172] & reg_we & !reg_error;
   assign loc_alert_regwen_10_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_11_we = addr_hit[165] & reg_we & !reg_error;
+  assign loc_alert_regwen_11_we = addr_hit[173] & reg_we & !reg_error;
   assign loc_alert_regwen_11_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_12_we = addr_hit[166] & reg_we & !reg_error;
+  assign loc_alert_regwen_12_we = addr_hit[174] & reg_we & !reg_error;
   assign loc_alert_regwen_12_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_13_we = addr_hit[167] & reg_we & !reg_error;
+  assign loc_alert_regwen_13_we = addr_hit[175] & reg_we & !reg_error;
   assign loc_alert_regwen_13_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_14_we = addr_hit[168] & reg_we & !reg_error;
+  assign loc_alert_regwen_14_we = addr_hit[176] & reg_we & !reg_error;
   assign loc_alert_regwen_14_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_15_we = addr_hit[169] & reg_we & !reg_error;
+  assign loc_alert_regwen_15_we = addr_hit[177] & reg_we & !reg_error;
   assign loc_alert_regwen_15_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_16_we = addr_hit[170] & reg_we & !reg_error;
+  assign loc_alert_regwen_16_we = addr_hit[178] & reg_we & !reg_error;
   assign loc_alert_regwen_16_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_17_we = addr_hit[171] & reg_we & !reg_error;
+  assign loc_alert_regwen_17_we = addr_hit[179] & reg_we & !reg_error;
   assign loc_alert_regwen_17_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_18_we = addr_hit[172] & reg_we & !reg_error;
+  assign loc_alert_regwen_18_we = addr_hit[180] & reg_we & !reg_error;
   assign loc_alert_regwen_18_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_19_we = addr_hit[173] & reg_we & !reg_error;
+  assign loc_alert_regwen_19_we = addr_hit[181] & reg_we & !reg_error;
   assign loc_alert_regwen_19_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_20_we = addr_hit[174] & reg_we & !reg_error;
+  assign loc_alert_regwen_20_we = addr_hit[182] & reg_we & !reg_error;
   assign loc_alert_regwen_20_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_21_we = addr_hit[175] & reg_we & !reg_error;
+  assign loc_alert_regwen_21_we = addr_hit[183] & reg_we & !reg_error;
   assign loc_alert_regwen_21_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_22_we = addr_hit[176] & reg_we & !reg_error;
+  assign loc_alert_regwen_22_we = addr_hit[184] & reg_we & !reg_error;
   assign loc_alert_regwen_22_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_23_we = addr_hit[177] & reg_we & !reg_error;
+  assign loc_alert_regwen_23_we = addr_hit[185] & reg_we & !reg_error;
   assign loc_alert_regwen_23_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_24_we = addr_hit[178] & reg_we & !reg_error;
+  assign loc_alert_regwen_24_we = addr_hit[186] & reg_we & !reg_error;
   assign loc_alert_regwen_24_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_25_we = addr_hit[179] & reg_we & !reg_error;
+  assign loc_alert_regwen_25_we = addr_hit[187] & reg_we & !reg_error;
   assign loc_alert_regwen_25_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_26_we = addr_hit[180] & reg_we & !reg_error;
+  assign loc_alert_regwen_26_we = addr_hit[188] & reg_we & !reg_error;
   assign loc_alert_regwen_26_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_27_we = addr_hit[181] & reg_we & !reg_error;
+  assign loc_alert_regwen_27_we = addr_hit[189] & reg_we & !reg_error;
   assign loc_alert_regwen_27_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_28_we = addr_hit[182] & reg_we & !reg_error;
+  assign loc_alert_regwen_28_we = addr_hit[190] & reg_we & !reg_error;
   assign loc_alert_regwen_28_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_29_we = addr_hit[183] & reg_we & !reg_error;
+  assign loc_alert_regwen_29_we = addr_hit[191] & reg_we & !reg_error;
   assign loc_alert_regwen_29_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_30_we = addr_hit[184] & reg_we & !reg_error;
+  assign loc_alert_regwen_30_we = addr_hit[192] & reg_we & !reg_error;
   assign loc_alert_regwen_30_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_31_we = addr_hit[185] & reg_we & !reg_error;
+  assign loc_alert_regwen_31_we = addr_hit[193] & reg_we & !reg_error;
   assign loc_alert_regwen_31_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_32_we = addr_hit[186] & reg_we & !reg_error;
+  assign loc_alert_regwen_32_we = addr_hit[194] & reg_we & !reg_error;
   assign loc_alert_regwen_32_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_33_we = addr_hit[187] & reg_we & !reg_error;
+  assign loc_alert_regwen_33_we = addr_hit[195] & reg_we & !reg_error;
   assign loc_alert_regwen_33_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_34_we = addr_hit[188] & reg_we & !reg_error;
+  assign loc_alert_regwen_34_we = addr_hit[196] & reg_we & !reg_error;
   assign loc_alert_regwen_34_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_35_we = addr_hit[189] & reg_we & !reg_error;
+  assign loc_alert_regwen_35_we = addr_hit[197] & reg_we & !reg_error;
   assign loc_alert_regwen_35_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_36_we = addr_hit[190] & reg_we & !reg_error;
+  assign loc_alert_regwen_36_we = addr_hit[198] & reg_we & !reg_error;
   assign loc_alert_regwen_36_wd = reg_wdata[0];
 
-  assign loc_alert_en_0_we = addr_hit[191] & reg_we & !reg_error;
+  assign loc_alert_regwen_37_we = addr_hit[199] & reg_we & !reg_error;
+  assign loc_alert_regwen_37_wd = reg_wdata[0];
+
+  assign loc_alert_regwen_38_we = addr_hit[200] & reg_we & !reg_error;
+  assign loc_alert_regwen_38_wd = reg_wdata[0];
+
+  assign loc_alert_en_0_we = addr_hit[201] & reg_we & !reg_error;
   assign loc_alert_en_0_wd = reg_wdata[0];
 
-  assign loc_alert_en_1_we = addr_hit[192] & reg_we & !reg_error;
+  assign loc_alert_en_1_we = addr_hit[202] & reg_we & !reg_error;
   assign loc_alert_en_1_wd = reg_wdata[0];
 
-  assign loc_alert_en_2_we = addr_hit[193] & reg_we & !reg_error;
+  assign loc_alert_en_2_we = addr_hit[203] & reg_we & !reg_error;
   assign loc_alert_en_2_wd = reg_wdata[0];
 
-  assign loc_alert_en_3_we = addr_hit[194] & reg_we & !reg_error;
+  assign loc_alert_en_3_we = addr_hit[204] & reg_we & !reg_error;
   assign loc_alert_en_3_wd = reg_wdata[0];
 
-  assign loc_alert_class_0_we = addr_hit[195] & reg_we & !reg_error;
+  assign loc_alert_class_0_we = addr_hit[205] & reg_we & !reg_error;
   assign loc_alert_class_0_wd = reg_wdata[1:0];
 
-  assign loc_alert_class_1_we = addr_hit[196] & reg_we & !reg_error;
+  assign loc_alert_class_1_we = addr_hit[206] & reg_we & !reg_error;
   assign loc_alert_class_1_wd = reg_wdata[1:0];
 
-  assign loc_alert_class_2_we = addr_hit[197] & reg_we & !reg_error;
+  assign loc_alert_class_2_we = addr_hit[207] & reg_we & !reg_error;
   assign loc_alert_class_2_wd = reg_wdata[1:0];
 
-  assign loc_alert_class_3_we = addr_hit[198] & reg_we & !reg_error;
+  assign loc_alert_class_3_we = addr_hit[208] & reg_we & !reg_error;
   assign loc_alert_class_3_wd = reg_wdata[1:0];
 
-  assign loc_alert_cause_0_we = addr_hit[199] & reg_we & !reg_error;
+  assign loc_alert_cause_0_we = addr_hit[209] & reg_we & !reg_error;
   assign loc_alert_cause_0_wd = reg_wdata[0];
 
-  assign loc_alert_cause_1_we = addr_hit[200] & reg_we & !reg_error;
+  assign loc_alert_cause_1_we = addr_hit[210] & reg_we & !reg_error;
   assign loc_alert_cause_1_wd = reg_wdata[0];
 
-  assign loc_alert_cause_2_we = addr_hit[201] & reg_we & !reg_error;
+  assign loc_alert_cause_2_we = addr_hit[211] & reg_we & !reg_error;
   assign loc_alert_cause_2_wd = reg_wdata[0];
 
-  assign loc_alert_cause_3_we = addr_hit[202] & reg_we & !reg_error;
+  assign loc_alert_cause_3_we = addr_hit[212] & reg_we & !reg_error;
   assign loc_alert_cause_3_wd = reg_wdata[0];
 
-  assign classa_regwen_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_regwen_we = addr_hit[213] & reg_we & !reg_error;
   assign classa_regwen_wd = reg_wdata[0];
 
-  assign classa_ctrl_en_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_en_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_en_wd = reg_wdata[0];
 
-  assign classa_ctrl_lock_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_lock_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_lock_wd = reg_wdata[1];
 
-  assign classa_ctrl_en_e0_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_en_e0_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_en_e0_wd = reg_wdata[2];
 
-  assign classa_ctrl_en_e1_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_en_e1_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_en_e1_wd = reg_wdata[3];
 
-  assign classa_ctrl_en_e2_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_en_e2_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_en_e2_wd = reg_wdata[4];
 
-  assign classa_ctrl_en_e3_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_en_e3_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_en_e3_wd = reg_wdata[5];
 
-  assign classa_ctrl_map_e0_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_map_e0_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_map_e0_wd = reg_wdata[7:6];
 
-  assign classa_ctrl_map_e1_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_map_e1_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_map_e1_wd = reg_wdata[9:8];
 
-  assign classa_ctrl_map_e2_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_map_e2_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_map_e2_wd = reg_wdata[11:10];
 
-  assign classa_ctrl_map_e3_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_ctrl_map_e3_we = addr_hit[214] & reg_we & !reg_error;
   assign classa_ctrl_map_e3_wd = reg_wdata[13:12];
 
-  assign classa_clr_regwen_we = addr_hit[205] & reg_we & !reg_error;
+  assign classa_clr_regwen_we = addr_hit[215] & reg_we & !reg_error;
   assign classa_clr_regwen_wd = reg_wdata[0];
 
-  assign classa_clr_we = addr_hit[206] & reg_we & !reg_error;
+  assign classa_clr_we = addr_hit[216] & reg_we & !reg_error;
   assign classa_clr_wd = reg_wdata[0];
 
-  assign classa_accum_cnt_re = addr_hit[207] & reg_re & !reg_error;
+  assign classa_accum_cnt_re = addr_hit[217] & reg_re & !reg_error;
 
-  assign classa_accum_thresh_we = addr_hit[208] & reg_we & !reg_error;
+  assign classa_accum_thresh_we = addr_hit[218] & reg_we & !reg_error;
   assign classa_accum_thresh_wd = reg_wdata[15:0];
 
-  assign classa_timeout_cyc_we = addr_hit[209] & reg_we & !reg_error;
+  assign classa_timeout_cyc_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_timeout_cyc_wd = reg_wdata[31:0];
 
-  assign classa_phase0_cyc_we = addr_hit[210] & reg_we & !reg_error;
+  assign classa_phase0_cyc_we = addr_hit[220] & reg_we & !reg_error;
   assign classa_phase0_cyc_wd = reg_wdata[31:0];
 
-  assign classa_phase1_cyc_we = addr_hit[211] & reg_we & !reg_error;
+  assign classa_phase1_cyc_we = addr_hit[221] & reg_we & !reg_error;
   assign classa_phase1_cyc_wd = reg_wdata[31:0];
 
-  assign classa_phase2_cyc_we = addr_hit[212] & reg_we & !reg_error;
+  assign classa_phase2_cyc_we = addr_hit[222] & reg_we & !reg_error;
   assign classa_phase2_cyc_wd = reg_wdata[31:0];
 
-  assign classa_phase3_cyc_we = addr_hit[213] & reg_we & !reg_error;
+  assign classa_phase3_cyc_we = addr_hit[223] & reg_we & !reg_error;
   assign classa_phase3_cyc_wd = reg_wdata[31:0];
 
-  assign classa_esc_cnt_re = addr_hit[214] & reg_re & !reg_error;
+  assign classa_esc_cnt_re = addr_hit[224] & reg_re & !reg_error;
 
-  assign classa_state_re = addr_hit[215] & reg_re & !reg_error;
+  assign classa_state_re = addr_hit[225] & reg_re & !reg_error;
 
-  assign classb_regwen_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_regwen_we = addr_hit[226] & reg_we & !reg_error;
   assign classb_regwen_wd = reg_wdata[0];
 
-  assign classb_ctrl_en_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_en_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_en_wd = reg_wdata[0];
 
-  assign classb_ctrl_lock_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_lock_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_lock_wd = reg_wdata[1];
 
-  assign classb_ctrl_en_e0_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_en_e0_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_en_e0_wd = reg_wdata[2];
 
-  assign classb_ctrl_en_e1_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_en_e1_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_en_e1_wd = reg_wdata[3];
 
-  assign classb_ctrl_en_e2_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_en_e2_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_en_e2_wd = reg_wdata[4];
 
-  assign classb_ctrl_en_e3_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_en_e3_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_en_e3_wd = reg_wdata[5];
 
-  assign classb_ctrl_map_e0_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_map_e0_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_map_e0_wd = reg_wdata[7:6];
 
-  assign classb_ctrl_map_e1_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_map_e1_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_map_e1_wd = reg_wdata[9:8];
 
-  assign classb_ctrl_map_e2_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_map_e2_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_map_e2_wd = reg_wdata[11:10];
 
-  assign classb_ctrl_map_e3_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_ctrl_map_e3_we = addr_hit[227] & reg_we & !reg_error;
   assign classb_ctrl_map_e3_wd = reg_wdata[13:12];
 
-  assign classb_clr_regwen_we = addr_hit[218] & reg_we & !reg_error;
+  assign classb_clr_regwen_we = addr_hit[228] & reg_we & !reg_error;
   assign classb_clr_regwen_wd = reg_wdata[0];
 
-  assign classb_clr_we = addr_hit[219] & reg_we & !reg_error;
+  assign classb_clr_we = addr_hit[229] & reg_we & !reg_error;
   assign classb_clr_wd = reg_wdata[0];
 
-  assign classb_accum_cnt_re = addr_hit[220] & reg_re & !reg_error;
+  assign classb_accum_cnt_re = addr_hit[230] & reg_re & !reg_error;
 
-  assign classb_accum_thresh_we = addr_hit[221] & reg_we & !reg_error;
+  assign classb_accum_thresh_we = addr_hit[231] & reg_we & !reg_error;
   assign classb_accum_thresh_wd = reg_wdata[15:0];
 
-  assign classb_timeout_cyc_we = addr_hit[222] & reg_we & !reg_error;
+  assign classb_timeout_cyc_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_timeout_cyc_wd = reg_wdata[31:0];
 
-  assign classb_phase0_cyc_we = addr_hit[223] & reg_we & !reg_error;
+  assign classb_phase0_cyc_we = addr_hit[233] & reg_we & !reg_error;
   assign classb_phase0_cyc_wd = reg_wdata[31:0];
 
-  assign classb_phase1_cyc_we = addr_hit[224] & reg_we & !reg_error;
+  assign classb_phase1_cyc_we = addr_hit[234] & reg_we & !reg_error;
   assign classb_phase1_cyc_wd = reg_wdata[31:0];
 
-  assign classb_phase2_cyc_we = addr_hit[225] & reg_we & !reg_error;
+  assign classb_phase2_cyc_we = addr_hit[235] & reg_we & !reg_error;
   assign classb_phase2_cyc_wd = reg_wdata[31:0];
 
-  assign classb_phase3_cyc_we = addr_hit[226] & reg_we & !reg_error;
+  assign classb_phase3_cyc_we = addr_hit[236] & reg_we & !reg_error;
   assign classb_phase3_cyc_wd = reg_wdata[31:0];
 
-  assign classb_esc_cnt_re = addr_hit[227] & reg_re & !reg_error;
+  assign classb_esc_cnt_re = addr_hit[237] & reg_re & !reg_error;
 
-  assign classb_state_re = addr_hit[228] & reg_re & !reg_error;
+  assign classb_state_re = addr_hit[238] & reg_re & !reg_error;
 
-  assign classc_regwen_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_regwen_we = addr_hit[239] & reg_we & !reg_error;
   assign classc_regwen_wd = reg_wdata[0];
 
-  assign classc_ctrl_en_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_en_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_en_wd = reg_wdata[0];
 
-  assign classc_ctrl_lock_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_lock_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_lock_wd = reg_wdata[1];
 
-  assign classc_ctrl_en_e0_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_en_e0_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_en_e0_wd = reg_wdata[2];
 
-  assign classc_ctrl_en_e1_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_en_e1_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_en_e1_wd = reg_wdata[3];
 
-  assign classc_ctrl_en_e2_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_en_e2_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_en_e2_wd = reg_wdata[4];
 
-  assign classc_ctrl_en_e3_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_en_e3_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_en_e3_wd = reg_wdata[5];
 
-  assign classc_ctrl_map_e0_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_map_e0_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_map_e0_wd = reg_wdata[7:6];
 
-  assign classc_ctrl_map_e1_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_map_e1_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_map_e1_wd = reg_wdata[9:8];
 
-  assign classc_ctrl_map_e2_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_map_e2_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_map_e2_wd = reg_wdata[11:10];
 
-  assign classc_ctrl_map_e3_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_ctrl_map_e3_we = addr_hit[240] & reg_we & !reg_error;
   assign classc_ctrl_map_e3_wd = reg_wdata[13:12];
 
-  assign classc_clr_regwen_we = addr_hit[231] & reg_we & !reg_error;
+  assign classc_clr_regwen_we = addr_hit[241] & reg_we & !reg_error;
   assign classc_clr_regwen_wd = reg_wdata[0];
 
-  assign classc_clr_we = addr_hit[232] & reg_we & !reg_error;
+  assign classc_clr_we = addr_hit[242] & reg_we & !reg_error;
   assign classc_clr_wd = reg_wdata[0];
 
-  assign classc_accum_cnt_re = addr_hit[233] & reg_re & !reg_error;
+  assign classc_accum_cnt_re = addr_hit[243] & reg_re & !reg_error;
 
-  assign classc_accum_thresh_we = addr_hit[234] & reg_we & !reg_error;
+  assign classc_accum_thresh_we = addr_hit[244] & reg_we & !reg_error;
   assign classc_accum_thresh_wd = reg_wdata[15:0];
 
-  assign classc_timeout_cyc_we = addr_hit[235] & reg_we & !reg_error;
+  assign classc_timeout_cyc_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_timeout_cyc_wd = reg_wdata[31:0];
 
-  assign classc_phase0_cyc_we = addr_hit[236] & reg_we & !reg_error;
+  assign classc_phase0_cyc_we = addr_hit[246] & reg_we & !reg_error;
   assign classc_phase0_cyc_wd = reg_wdata[31:0];
 
-  assign classc_phase1_cyc_we = addr_hit[237] & reg_we & !reg_error;
+  assign classc_phase1_cyc_we = addr_hit[247] & reg_we & !reg_error;
   assign classc_phase1_cyc_wd = reg_wdata[31:0];
 
-  assign classc_phase2_cyc_we = addr_hit[238] & reg_we & !reg_error;
+  assign classc_phase2_cyc_we = addr_hit[248] & reg_we & !reg_error;
   assign classc_phase2_cyc_wd = reg_wdata[31:0];
 
-  assign classc_phase3_cyc_we = addr_hit[239] & reg_we & !reg_error;
+  assign classc_phase3_cyc_we = addr_hit[249] & reg_we & !reg_error;
   assign classc_phase3_cyc_wd = reg_wdata[31:0];
 
-  assign classc_esc_cnt_re = addr_hit[240] & reg_re & !reg_error;
+  assign classc_esc_cnt_re = addr_hit[250] & reg_re & !reg_error;
 
-  assign classc_state_re = addr_hit[241] & reg_re & !reg_error;
+  assign classc_state_re = addr_hit[251] & reg_re & !reg_error;
 
-  assign classd_regwen_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_regwen_we = addr_hit[252] & reg_we & !reg_error;
   assign classd_regwen_wd = reg_wdata[0];
 
-  assign classd_ctrl_en_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_en_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_en_wd = reg_wdata[0];
 
-  assign classd_ctrl_lock_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_lock_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_lock_wd = reg_wdata[1];
 
-  assign classd_ctrl_en_e0_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_en_e0_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_en_e0_wd = reg_wdata[2];
 
-  assign classd_ctrl_en_e1_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_en_e1_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_en_e1_wd = reg_wdata[3];
 
-  assign classd_ctrl_en_e2_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_en_e2_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_en_e2_wd = reg_wdata[4];
 
-  assign classd_ctrl_en_e3_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_en_e3_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_en_e3_wd = reg_wdata[5];
 
-  assign classd_ctrl_map_e0_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_map_e0_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_map_e0_wd = reg_wdata[7:6];
 
-  assign classd_ctrl_map_e1_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_map_e1_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_map_e1_wd = reg_wdata[9:8];
 
-  assign classd_ctrl_map_e2_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_map_e2_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_map_e2_wd = reg_wdata[11:10];
 
-  assign classd_ctrl_map_e3_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_ctrl_map_e3_we = addr_hit[253] & reg_we & !reg_error;
   assign classd_ctrl_map_e3_wd = reg_wdata[13:12];
 
-  assign classd_clr_regwen_we = addr_hit[244] & reg_we & !reg_error;
+  assign classd_clr_regwen_we = addr_hit[254] & reg_we & !reg_error;
   assign classd_clr_regwen_wd = reg_wdata[0];
 
-  assign classd_clr_we = addr_hit[245] & reg_we & !reg_error;
+  assign classd_clr_we = addr_hit[255] & reg_we & !reg_error;
   assign classd_clr_wd = reg_wdata[0];
 
-  assign classd_accum_cnt_re = addr_hit[246] & reg_re & !reg_error;
+  assign classd_accum_cnt_re = addr_hit[256] & reg_re & !reg_error;
 
-  assign classd_accum_thresh_we = addr_hit[247] & reg_we & !reg_error;
+  assign classd_accum_thresh_we = addr_hit[257] & reg_we & !reg_error;
   assign classd_accum_thresh_wd = reg_wdata[15:0];
 
-  assign classd_timeout_cyc_we = addr_hit[248] & reg_we & !reg_error;
+  assign classd_timeout_cyc_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_timeout_cyc_wd = reg_wdata[31:0];
 
-  assign classd_phase0_cyc_we = addr_hit[249] & reg_we & !reg_error;
+  assign classd_phase0_cyc_we = addr_hit[259] & reg_we & !reg_error;
   assign classd_phase0_cyc_wd = reg_wdata[31:0];
 
-  assign classd_phase1_cyc_we = addr_hit[250] & reg_we & !reg_error;
+  assign classd_phase1_cyc_we = addr_hit[260] & reg_we & !reg_error;
   assign classd_phase1_cyc_wd = reg_wdata[31:0];
 
-  assign classd_phase2_cyc_we = addr_hit[251] & reg_we & !reg_error;
+  assign classd_phase2_cyc_we = addr_hit[261] & reg_we & !reg_error;
   assign classd_phase2_cyc_wd = reg_wdata[31:0];
 
-  assign classd_phase3_cyc_we = addr_hit[252] & reg_we & !reg_error;
+  assign classd_phase3_cyc_we = addr_hit[262] & reg_we & !reg_error;
   assign classd_phase3_cyc_wd = reg_wdata[31:0];
 
-  assign classd_esc_cnt_re = addr_hit[253] & reg_re & !reg_error;
+  assign classd_esc_cnt_re = addr_hit[263] & reg_re & !reg_error;
 
-  assign classd_state_re = addr_hit[254] & reg_re & !reg_error;
+  assign classd_state_re = addr_hit[264] & reg_re & !reg_error;
 
   // Read data return
   always_comb begin
@@ -10482,650 +10832,690 @@
       end
 
       addr_hit[43]: begin
-        reg_rdata_next[0] = alert_en_0_qs;
+        reg_rdata_next[0] = alert_regwen_37_qs;
       end
 
       addr_hit[44]: begin
-        reg_rdata_next[0] = alert_en_1_qs;
+        reg_rdata_next[0] = alert_regwen_38_qs;
       end
 
       addr_hit[45]: begin
-        reg_rdata_next[0] = alert_en_2_qs;
+        reg_rdata_next[0] = alert_en_0_qs;
       end
 
       addr_hit[46]: begin
-        reg_rdata_next[0] = alert_en_3_qs;
+        reg_rdata_next[0] = alert_en_1_qs;
       end
 
       addr_hit[47]: begin
-        reg_rdata_next[0] = alert_en_4_qs;
+        reg_rdata_next[0] = alert_en_2_qs;
       end
 
       addr_hit[48]: begin
-        reg_rdata_next[0] = alert_en_5_qs;
+        reg_rdata_next[0] = alert_en_3_qs;
       end
 
       addr_hit[49]: begin
-        reg_rdata_next[0] = alert_en_6_qs;
+        reg_rdata_next[0] = alert_en_4_qs;
       end
 
       addr_hit[50]: begin
-        reg_rdata_next[0] = alert_en_7_qs;
+        reg_rdata_next[0] = alert_en_5_qs;
       end
 
       addr_hit[51]: begin
-        reg_rdata_next[0] = alert_en_8_qs;
+        reg_rdata_next[0] = alert_en_6_qs;
       end
 
       addr_hit[52]: begin
-        reg_rdata_next[0] = alert_en_9_qs;
+        reg_rdata_next[0] = alert_en_7_qs;
       end
 
       addr_hit[53]: begin
-        reg_rdata_next[0] = alert_en_10_qs;
+        reg_rdata_next[0] = alert_en_8_qs;
       end
 
       addr_hit[54]: begin
-        reg_rdata_next[0] = alert_en_11_qs;
+        reg_rdata_next[0] = alert_en_9_qs;
       end
 
       addr_hit[55]: begin
-        reg_rdata_next[0] = alert_en_12_qs;
+        reg_rdata_next[0] = alert_en_10_qs;
       end
 
       addr_hit[56]: begin
-        reg_rdata_next[0] = alert_en_13_qs;
+        reg_rdata_next[0] = alert_en_11_qs;
       end
 
       addr_hit[57]: begin
-        reg_rdata_next[0] = alert_en_14_qs;
+        reg_rdata_next[0] = alert_en_12_qs;
       end
 
       addr_hit[58]: begin
-        reg_rdata_next[0] = alert_en_15_qs;
+        reg_rdata_next[0] = alert_en_13_qs;
       end
 
       addr_hit[59]: begin
-        reg_rdata_next[0] = alert_en_16_qs;
+        reg_rdata_next[0] = alert_en_14_qs;
       end
 
       addr_hit[60]: begin
-        reg_rdata_next[0] = alert_en_17_qs;
+        reg_rdata_next[0] = alert_en_15_qs;
       end
 
       addr_hit[61]: begin
-        reg_rdata_next[0] = alert_en_18_qs;
+        reg_rdata_next[0] = alert_en_16_qs;
       end
 
       addr_hit[62]: begin
-        reg_rdata_next[0] = alert_en_19_qs;
+        reg_rdata_next[0] = alert_en_17_qs;
       end
 
       addr_hit[63]: begin
-        reg_rdata_next[0] = alert_en_20_qs;
+        reg_rdata_next[0] = alert_en_18_qs;
       end
 
       addr_hit[64]: begin
-        reg_rdata_next[0] = alert_en_21_qs;
+        reg_rdata_next[0] = alert_en_19_qs;
       end
 
       addr_hit[65]: begin
-        reg_rdata_next[0] = alert_en_22_qs;
+        reg_rdata_next[0] = alert_en_20_qs;
       end
 
       addr_hit[66]: begin
-        reg_rdata_next[0] = alert_en_23_qs;
+        reg_rdata_next[0] = alert_en_21_qs;
       end
 
       addr_hit[67]: begin
-        reg_rdata_next[0] = alert_en_24_qs;
+        reg_rdata_next[0] = alert_en_22_qs;
       end
 
       addr_hit[68]: begin
-        reg_rdata_next[0] = alert_en_25_qs;
+        reg_rdata_next[0] = alert_en_23_qs;
       end
 
       addr_hit[69]: begin
-        reg_rdata_next[0] = alert_en_26_qs;
+        reg_rdata_next[0] = alert_en_24_qs;
       end
 
       addr_hit[70]: begin
-        reg_rdata_next[0] = alert_en_27_qs;
+        reg_rdata_next[0] = alert_en_25_qs;
       end
 
       addr_hit[71]: begin
-        reg_rdata_next[0] = alert_en_28_qs;
+        reg_rdata_next[0] = alert_en_26_qs;
       end
 
       addr_hit[72]: begin
-        reg_rdata_next[0] = alert_en_29_qs;
+        reg_rdata_next[0] = alert_en_27_qs;
       end
 
       addr_hit[73]: begin
-        reg_rdata_next[0] = alert_en_30_qs;
+        reg_rdata_next[0] = alert_en_28_qs;
       end
 
       addr_hit[74]: begin
-        reg_rdata_next[0] = alert_en_31_qs;
+        reg_rdata_next[0] = alert_en_29_qs;
       end
 
       addr_hit[75]: begin
-        reg_rdata_next[0] = alert_en_32_qs;
+        reg_rdata_next[0] = alert_en_30_qs;
       end
 
       addr_hit[76]: begin
-        reg_rdata_next[0] = alert_en_33_qs;
+        reg_rdata_next[0] = alert_en_31_qs;
       end
 
       addr_hit[77]: begin
-        reg_rdata_next[0] = alert_en_34_qs;
+        reg_rdata_next[0] = alert_en_32_qs;
       end
 
       addr_hit[78]: begin
-        reg_rdata_next[0] = alert_en_35_qs;
+        reg_rdata_next[0] = alert_en_33_qs;
       end
 
       addr_hit[79]: begin
-        reg_rdata_next[0] = alert_en_36_qs;
+        reg_rdata_next[0] = alert_en_34_qs;
       end
 
       addr_hit[80]: begin
-        reg_rdata_next[1:0] = alert_class_0_qs;
+        reg_rdata_next[0] = alert_en_35_qs;
       end
 
       addr_hit[81]: begin
-        reg_rdata_next[1:0] = alert_class_1_qs;
+        reg_rdata_next[0] = alert_en_36_qs;
       end
 
       addr_hit[82]: begin
-        reg_rdata_next[1:0] = alert_class_2_qs;
+        reg_rdata_next[0] = alert_en_37_qs;
       end
 
       addr_hit[83]: begin
-        reg_rdata_next[1:0] = alert_class_3_qs;
+        reg_rdata_next[0] = alert_en_38_qs;
       end
 
       addr_hit[84]: begin
-        reg_rdata_next[1:0] = alert_class_4_qs;
+        reg_rdata_next[1:0] = alert_class_0_qs;
       end
 
       addr_hit[85]: begin
-        reg_rdata_next[1:0] = alert_class_5_qs;
+        reg_rdata_next[1:0] = alert_class_1_qs;
       end
 
       addr_hit[86]: begin
-        reg_rdata_next[1:0] = alert_class_6_qs;
+        reg_rdata_next[1:0] = alert_class_2_qs;
       end
 
       addr_hit[87]: begin
-        reg_rdata_next[1:0] = alert_class_7_qs;
+        reg_rdata_next[1:0] = alert_class_3_qs;
       end
 
       addr_hit[88]: begin
-        reg_rdata_next[1:0] = alert_class_8_qs;
+        reg_rdata_next[1:0] = alert_class_4_qs;
       end
 
       addr_hit[89]: begin
-        reg_rdata_next[1:0] = alert_class_9_qs;
+        reg_rdata_next[1:0] = alert_class_5_qs;
       end
 
       addr_hit[90]: begin
-        reg_rdata_next[1:0] = alert_class_10_qs;
+        reg_rdata_next[1:0] = alert_class_6_qs;
       end
 
       addr_hit[91]: begin
-        reg_rdata_next[1:0] = alert_class_11_qs;
+        reg_rdata_next[1:0] = alert_class_7_qs;
       end
 
       addr_hit[92]: begin
-        reg_rdata_next[1:0] = alert_class_12_qs;
+        reg_rdata_next[1:0] = alert_class_8_qs;
       end
 
       addr_hit[93]: begin
-        reg_rdata_next[1:0] = alert_class_13_qs;
+        reg_rdata_next[1:0] = alert_class_9_qs;
       end
 
       addr_hit[94]: begin
-        reg_rdata_next[1:0] = alert_class_14_qs;
+        reg_rdata_next[1:0] = alert_class_10_qs;
       end
 
       addr_hit[95]: begin
-        reg_rdata_next[1:0] = alert_class_15_qs;
+        reg_rdata_next[1:0] = alert_class_11_qs;
       end
 
       addr_hit[96]: begin
-        reg_rdata_next[1:0] = alert_class_16_qs;
+        reg_rdata_next[1:0] = alert_class_12_qs;
       end
 
       addr_hit[97]: begin
-        reg_rdata_next[1:0] = alert_class_17_qs;
+        reg_rdata_next[1:0] = alert_class_13_qs;
       end
 
       addr_hit[98]: begin
-        reg_rdata_next[1:0] = alert_class_18_qs;
+        reg_rdata_next[1:0] = alert_class_14_qs;
       end
 
       addr_hit[99]: begin
-        reg_rdata_next[1:0] = alert_class_19_qs;
+        reg_rdata_next[1:0] = alert_class_15_qs;
       end
 
       addr_hit[100]: begin
-        reg_rdata_next[1:0] = alert_class_20_qs;
+        reg_rdata_next[1:0] = alert_class_16_qs;
       end
 
       addr_hit[101]: begin
-        reg_rdata_next[1:0] = alert_class_21_qs;
+        reg_rdata_next[1:0] = alert_class_17_qs;
       end
 
       addr_hit[102]: begin
-        reg_rdata_next[1:0] = alert_class_22_qs;
+        reg_rdata_next[1:0] = alert_class_18_qs;
       end
 
       addr_hit[103]: begin
-        reg_rdata_next[1:0] = alert_class_23_qs;
+        reg_rdata_next[1:0] = alert_class_19_qs;
       end
 
       addr_hit[104]: begin
-        reg_rdata_next[1:0] = alert_class_24_qs;
+        reg_rdata_next[1:0] = alert_class_20_qs;
       end
 
       addr_hit[105]: begin
-        reg_rdata_next[1:0] = alert_class_25_qs;
+        reg_rdata_next[1:0] = alert_class_21_qs;
       end
 
       addr_hit[106]: begin
-        reg_rdata_next[1:0] = alert_class_26_qs;
+        reg_rdata_next[1:0] = alert_class_22_qs;
       end
 
       addr_hit[107]: begin
-        reg_rdata_next[1:0] = alert_class_27_qs;
+        reg_rdata_next[1:0] = alert_class_23_qs;
       end
 
       addr_hit[108]: begin
-        reg_rdata_next[1:0] = alert_class_28_qs;
+        reg_rdata_next[1:0] = alert_class_24_qs;
       end
 
       addr_hit[109]: begin
-        reg_rdata_next[1:0] = alert_class_29_qs;
+        reg_rdata_next[1:0] = alert_class_25_qs;
       end
 
       addr_hit[110]: begin
-        reg_rdata_next[1:0] = alert_class_30_qs;
+        reg_rdata_next[1:0] = alert_class_26_qs;
       end
 
       addr_hit[111]: begin
-        reg_rdata_next[1:0] = alert_class_31_qs;
+        reg_rdata_next[1:0] = alert_class_27_qs;
       end
 
       addr_hit[112]: begin
-        reg_rdata_next[1:0] = alert_class_32_qs;
+        reg_rdata_next[1:0] = alert_class_28_qs;
       end
 
       addr_hit[113]: begin
-        reg_rdata_next[1:0] = alert_class_33_qs;
+        reg_rdata_next[1:0] = alert_class_29_qs;
       end
 
       addr_hit[114]: begin
-        reg_rdata_next[1:0] = alert_class_34_qs;
+        reg_rdata_next[1:0] = alert_class_30_qs;
       end
 
       addr_hit[115]: begin
-        reg_rdata_next[1:0] = alert_class_35_qs;
+        reg_rdata_next[1:0] = alert_class_31_qs;
       end
 
       addr_hit[116]: begin
-        reg_rdata_next[1:0] = alert_class_36_qs;
+        reg_rdata_next[1:0] = alert_class_32_qs;
       end
 
       addr_hit[117]: begin
-        reg_rdata_next[0] = alert_cause_0_qs;
+        reg_rdata_next[1:0] = alert_class_33_qs;
       end
 
       addr_hit[118]: begin
-        reg_rdata_next[0] = alert_cause_1_qs;
+        reg_rdata_next[1:0] = alert_class_34_qs;
       end
 
       addr_hit[119]: begin
-        reg_rdata_next[0] = alert_cause_2_qs;
+        reg_rdata_next[1:0] = alert_class_35_qs;
       end
 
       addr_hit[120]: begin
-        reg_rdata_next[0] = alert_cause_3_qs;
+        reg_rdata_next[1:0] = alert_class_36_qs;
       end
 
       addr_hit[121]: begin
-        reg_rdata_next[0] = alert_cause_4_qs;
+        reg_rdata_next[1:0] = alert_class_37_qs;
       end
 
       addr_hit[122]: begin
-        reg_rdata_next[0] = alert_cause_5_qs;
+        reg_rdata_next[1:0] = alert_class_38_qs;
       end
 
       addr_hit[123]: begin
-        reg_rdata_next[0] = alert_cause_6_qs;
+        reg_rdata_next[0] = alert_cause_0_qs;
       end
 
       addr_hit[124]: begin
-        reg_rdata_next[0] = alert_cause_7_qs;
+        reg_rdata_next[0] = alert_cause_1_qs;
       end
 
       addr_hit[125]: begin
-        reg_rdata_next[0] = alert_cause_8_qs;
+        reg_rdata_next[0] = alert_cause_2_qs;
       end
 
       addr_hit[126]: begin
-        reg_rdata_next[0] = alert_cause_9_qs;
+        reg_rdata_next[0] = alert_cause_3_qs;
       end
 
       addr_hit[127]: begin
-        reg_rdata_next[0] = alert_cause_10_qs;
+        reg_rdata_next[0] = alert_cause_4_qs;
       end
 
       addr_hit[128]: begin
-        reg_rdata_next[0] = alert_cause_11_qs;
+        reg_rdata_next[0] = alert_cause_5_qs;
       end
 
       addr_hit[129]: begin
-        reg_rdata_next[0] = alert_cause_12_qs;
+        reg_rdata_next[0] = alert_cause_6_qs;
       end
 
       addr_hit[130]: begin
-        reg_rdata_next[0] = alert_cause_13_qs;
+        reg_rdata_next[0] = alert_cause_7_qs;
       end
 
       addr_hit[131]: begin
-        reg_rdata_next[0] = alert_cause_14_qs;
+        reg_rdata_next[0] = alert_cause_8_qs;
       end
 
       addr_hit[132]: begin
-        reg_rdata_next[0] = alert_cause_15_qs;
+        reg_rdata_next[0] = alert_cause_9_qs;
       end
 
       addr_hit[133]: begin
-        reg_rdata_next[0] = alert_cause_16_qs;
+        reg_rdata_next[0] = alert_cause_10_qs;
       end
 
       addr_hit[134]: begin
-        reg_rdata_next[0] = alert_cause_17_qs;
+        reg_rdata_next[0] = alert_cause_11_qs;
       end
 
       addr_hit[135]: begin
-        reg_rdata_next[0] = alert_cause_18_qs;
+        reg_rdata_next[0] = alert_cause_12_qs;
       end
 
       addr_hit[136]: begin
-        reg_rdata_next[0] = alert_cause_19_qs;
+        reg_rdata_next[0] = alert_cause_13_qs;
       end
 
       addr_hit[137]: begin
-        reg_rdata_next[0] = alert_cause_20_qs;
+        reg_rdata_next[0] = alert_cause_14_qs;
       end
 
       addr_hit[138]: begin
-        reg_rdata_next[0] = alert_cause_21_qs;
+        reg_rdata_next[0] = alert_cause_15_qs;
       end
 
       addr_hit[139]: begin
-        reg_rdata_next[0] = alert_cause_22_qs;
+        reg_rdata_next[0] = alert_cause_16_qs;
       end
 
       addr_hit[140]: begin
-        reg_rdata_next[0] = alert_cause_23_qs;
+        reg_rdata_next[0] = alert_cause_17_qs;
       end
 
       addr_hit[141]: begin
-        reg_rdata_next[0] = alert_cause_24_qs;
+        reg_rdata_next[0] = alert_cause_18_qs;
       end
 
       addr_hit[142]: begin
-        reg_rdata_next[0] = alert_cause_25_qs;
+        reg_rdata_next[0] = alert_cause_19_qs;
       end
 
       addr_hit[143]: begin
-        reg_rdata_next[0] = alert_cause_26_qs;
+        reg_rdata_next[0] = alert_cause_20_qs;
       end
 
       addr_hit[144]: begin
-        reg_rdata_next[0] = alert_cause_27_qs;
+        reg_rdata_next[0] = alert_cause_21_qs;
       end
 
       addr_hit[145]: begin
-        reg_rdata_next[0] = alert_cause_28_qs;
+        reg_rdata_next[0] = alert_cause_22_qs;
       end
 
       addr_hit[146]: begin
-        reg_rdata_next[0] = alert_cause_29_qs;
+        reg_rdata_next[0] = alert_cause_23_qs;
       end
 
       addr_hit[147]: begin
-        reg_rdata_next[0] = alert_cause_30_qs;
+        reg_rdata_next[0] = alert_cause_24_qs;
       end
 
       addr_hit[148]: begin
-        reg_rdata_next[0] = alert_cause_31_qs;
+        reg_rdata_next[0] = alert_cause_25_qs;
       end
 
       addr_hit[149]: begin
-        reg_rdata_next[0] = alert_cause_32_qs;
+        reg_rdata_next[0] = alert_cause_26_qs;
       end
 
       addr_hit[150]: begin
-        reg_rdata_next[0] = alert_cause_33_qs;
+        reg_rdata_next[0] = alert_cause_27_qs;
       end
 
       addr_hit[151]: begin
-        reg_rdata_next[0] = alert_cause_34_qs;
+        reg_rdata_next[0] = alert_cause_28_qs;
       end
 
       addr_hit[152]: begin
-        reg_rdata_next[0] = alert_cause_35_qs;
+        reg_rdata_next[0] = alert_cause_29_qs;
       end
 
       addr_hit[153]: begin
-        reg_rdata_next[0] = alert_cause_36_qs;
+        reg_rdata_next[0] = alert_cause_30_qs;
       end
 
       addr_hit[154]: begin
-        reg_rdata_next[0] = loc_alert_regwen_0_qs;
+        reg_rdata_next[0] = alert_cause_31_qs;
       end
 
       addr_hit[155]: begin
-        reg_rdata_next[0] = loc_alert_regwen_1_qs;
+        reg_rdata_next[0] = alert_cause_32_qs;
       end
 
       addr_hit[156]: begin
-        reg_rdata_next[0] = loc_alert_regwen_2_qs;
+        reg_rdata_next[0] = alert_cause_33_qs;
       end
 
       addr_hit[157]: begin
-        reg_rdata_next[0] = loc_alert_regwen_3_qs;
+        reg_rdata_next[0] = alert_cause_34_qs;
       end
 
       addr_hit[158]: begin
-        reg_rdata_next[0] = loc_alert_regwen_4_qs;
+        reg_rdata_next[0] = alert_cause_35_qs;
       end
 
       addr_hit[159]: begin
-        reg_rdata_next[0] = loc_alert_regwen_5_qs;
+        reg_rdata_next[0] = alert_cause_36_qs;
       end
 
       addr_hit[160]: begin
-        reg_rdata_next[0] = loc_alert_regwen_6_qs;
+        reg_rdata_next[0] = alert_cause_37_qs;
       end
 
       addr_hit[161]: begin
-        reg_rdata_next[0] = loc_alert_regwen_7_qs;
+        reg_rdata_next[0] = alert_cause_38_qs;
       end
 
       addr_hit[162]: begin
-        reg_rdata_next[0] = loc_alert_regwen_8_qs;
+        reg_rdata_next[0] = loc_alert_regwen_0_qs;
       end
 
       addr_hit[163]: begin
-        reg_rdata_next[0] = loc_alert_regwen_9_qs;
+        reg_rdata_next[0] = loc_alert_regwen_1_qs;
       end
 
       addr_hit[164]: begin
-        reg_rdata_next[0] = loc_alert_regwen_10_qs;
+        reg_rdata_next[0] = loc_alert_regwen_2_qs;
       end
 
       addr_hit[165]: begin
-        reg_rdata_next[0] = loc_alert_regwen_11_qs;
+        reg_rdata_next[0] = loc_alert_regwen_3_qs;
       end
 
       addr_hit[166]: begin
-        reg_rdata_next[0] = loc_alert_regwen_12_qs;
+        reg_rdata_next[0] = loc_alert_regwen_4_qs;
       end
 
       addr_hit[167]: begin
-        reg_rdata_next[0] = loc_alert_regwen_13_qs;
+        reg_rdata_next[0] = loc_alert_regwen_5_qs;
       end
 
       addr_hit[168]: begin
-        reg_rdata_next[0] = loc_alert_regwen_14_qs;
+        reg_rdata_next[0] = loc_alert_regwen_6_qs;
       end
 
       addr_hit[169]: begin
-        reg_rdata_next[0] = loc_alert_regwen_15_qs;
+        reg_rdata_next[0] = loc_alert_regwen_7_qs;
       end
 
       addr_hit[170]: begin
-        reg_rdata_next[0] = loc_alert_regwen_16_qs;
+        reg_rdata_next[0] = loc_alert_regwen_8_qs;
       end
 
       addr_hit[171]: begin
-        reg_rdata_next[0] = loc_alert_regwen_17_qs;
+        reg_rdata_next[0] = loc_alert_regwen_9_qs;
       end
 
       addr_hit[172]: begin
-        reg_rdata_next[0] = loc_alert_regwen_18_qs;
+        reg_rdata_next[0] = loc_alert_regwen_10_qs;
       end
 
       addr_hit[173]: begin
-        reg_rdata_next[0] = loc_alert_regwen_19_qs;
+        reg_rdata_next[0] = loc_alert_regwen_11_qs;
       end
 
       addr_hit[174]: begin
-        reg_rdata_next[0] = loc_alert_regwen_20_qs;
+        reg_rdata_next[0] = loc_alert_regwen_12_qs;
       end
 
       addr_hit[175]: begin
-        reg_rdata_next[0] = loc_alert_regwen_21_qs;
+        reg_rdata_next[0] = loc_alert_regwen_13_qs;
       end
 
       addr_hit[176]: begin
-        reg_rdata_next[0] = loc_alert_regwen_22_qs;
+        reg_rdata_next[0] = loc_alert_regwen_14_qs;
       end
 
       addr_hit[177]: begin
-        reg_rdata_next[0] = loc_alert_regwen_23_qs;
+        reg_rdata_next[0] = loc_alert_regwen_15_qs;
       end
 
       addr_hit[178]: begin
-        reg_rdata_next[0] = loc_alert_regwen_24_qs;
+        reg_rdata_next[0] = loc_alert_regwen_16_qs;
       end
 
       addr_hit[179]: begin
-        reg_rdata_next[0] = loc_alert_regwen_25_qs;
+        reg_rdata_next[0] = loc_alert_regwen_17_qs;
       end
 
       addr_hit[180]: begin
-        reg_rdata_next[0] = loc_alert_regwen_26_qs;
+        reg_rdata_next[0] = loc_alert_regwen_18_qs;
       end
 
       addr_hit[181]: begin
-        reg_rdata_next[0] = loc_alert_regwen_27_qs;
+        reg_rdata_next[0] = loc_alert_regwen_19_qs;
       end
 
       addr_hit[182]: begin
-        reg_rdata_next[0] = loc_alert_regwen_28_qs;
+        reg_rdata_next[0] = loc_alert_regwen_20_qs;
       end
 
       addr_hit[183]: begin
-        reg_rdata_next[0] = loc_alert_regwen_29_qs;
+        reg_rdata_next[0] = loc_alert_regwen_21_qs;
       end
 
       addr_hit[184]: begin
-        reg_rdata_next[0] = loc_alert_regwen_30_qs;
+        reg_rdata_next[0] = loc_alert_regwen_22_qs;
       end
 
       addr_hit[185]: begin
-        reg_rdata_next[0] = loc_alert_regwen_31_qs;
+        reg_rdata_next[0] = loc_alert_regwen_23_qs;
       end
 
       addr_hit[186]: begin
-        reg_rdata_next[0] = loc_alert_regwen_32_qs;
+        reg_rdata_next[0] = loc_alert_regwen_24_qs;
       end
 
       addr_hit[187]: begin
-        reg_rdata_next[0] = loc_alert_regwen_33_qs;
+        reg_rdata_next[0] = loc_alert_regwen_25_qs;
       end
 
       addr_hit[188]: begin
-        reg_rdata_next[0] = loc_alert_regwen_34_qs;
+        reg_rdata_next[0] = loc_alert_regwen_26_qs;
       end
 
       addr_hit[189]: begin
-        reg_rdata_next[0] = loc_alert_regwen_35_qs;
+        reg_rdata_next[0] = loc_alert_regwen_27_qs;
       end
 
       addr_hit[190]: begin
-        reg_rdata_next[0] = loc_alert_regwen_36_qs;
+        reg_rdata_next[0] = loc_alert_regwen_28_qs;
       end
 
       addr_hit[191]: begin
-        reg_rdata_next[0] = loc_alert_en_0_qs;
+        reg_rdata_next[0] = loc_alert_regwen_29_qs;
       end
 
       addr_hit[192]: begin
-        reg_rdata_next[0] = loc_alert_en_1_qs;
+        reg_rdata_next[0] = loc_alert_regwen_30_qs;
       end
 
       addr_hit[193]: begin
-        reg_rdata_next[0] = loc_alert_en_2_qs;
+        reg_rdata_next[0] = loc_alert_regwen_31_qs;
       end
 
       addr_hit[194]: begin
-        reg_rdata_next[0] = loc_alert_en_3_qs;
+        reg_rdata_next[0] = loc_alert_regwen_32_qs;
       end
 
       addr_hit[195]: begin
-        reg_rdata_next[1:0] = loc_alert_class_0_qs;
+        reg_rdata_next[0] = loc_alert_regwen_33_qs;
       end
 
       addr_hit[196]: begin
-        reg_rdata_next[1:0] = loc_alert_class_1_qs;
+        reg_rdata_next[0] = loc_alert_regwen_34_qs;
       end
 
       addr_hit[197]: begin
-        reg_rdata_next[1:0] = loc_alert_class_2_qs;
+        reg_rdata_next[0] = loc_alert_regwen_35_qs;
       end
 
       addr_hit[198]: begin
-        reg_rdata_next[1:0] = loc_alert_class_3_qs;
+        reg_rdata_next[0] = loc_alert_regwen_36_qs;
       end
 
       addr_hit[199]: begin
-        reg_rdata_next[0] = loc_alert_cause_0_qs;
+        reg_rdata_next[0] = loc_alert_regwen_37_qs;
       end
 
       addr_hit[200]: begin
-        reg_rdata_next[0] = loc_alert_cause_1_qs;
+        reg_rdata_next[0] = loc_alert_regwen_38_qs;
       end
 
       addr_hit[201]: begin
-        reg_rdata_next[0] = loc_alert_cause_2_qs;
+        reg_rdata_next[0] = loc_alert_en_0_qs;
       end
 
       addr_hit[202]: begin
-        reg_rdata_next[0] = loc_alert_cause_3_qs;
+        reg_rdata_next[0] = loc_alert_en_1_qs;
       end
 
       addr_hit[203]: begin
-        reg_rdata_next[0] = classa_regwen_qs;
+        reg_rdata_next[0] = loc_alert_en_2_qs;
       end
 
       addr_hit[204]: begin
+        reg_rdata_next[0] = loc_alert_en_3_qs;
+      end
+
+      addr_hit[205]: begin
+        reg_rdata_next[1:0] = loc_alert_class_0_qs;
+      end
+
+      addr_hit[206]: begin
+        reg_rdata_next[1:0] = loc_alert_class_1_qs;
+      end
+
+      addr_hit[207]: begin
+        reg_rdata_next[1:0] = loc_alert_class_2_qs;
+      end
+
+      addr_hit[208]: begin
+        reg_rdata_next[1:0] = loc_alert_class_3_qs;
+      end
+
+      addr_hit[209]: begin
+        reg_rdata_next[0] = loc_alert_cause_0_qs;
+      end
+
+      addr_hit[210]: begin
+        reg_rdata_next[0] = loc_alert_cause_1_qs;
+      end
+
+      addr_hit[211]: begin
+        reg_rdata_next[0] = loc_alert_cause_2_qs;
+      end
+
+      addr_hit[212]: begin
+        reg_rdata_next[0] = loc_alert_cause_3_qs;
+      end
+
+      addr_hit[213]: begin
+        reg_rdata_next[0] = classa_regwen_qs;
+      end
+
+      addr_hit[214]: begin
         reg_rdata_next[0] = classa_ctrl_en_qs;
         reg_rdata_next[1] = classa_ctrl_lock_qs;
         reg_rdata_next[2] = classa_ctrl_en_e0_qs;
@@ -11138,55 +11528,55 @@
         reg_rdata_next[13:12] = classa_ctrl_map_e3_qs;
       end
 
-      addr_hit[205]: begin
+      addr_hit[215]: begin
         reg_rdata_next[0] = classa_clr_regwen_qs;
       end
 
-      addr_hit[206]: begin
+      addr_hit[216]: begin
         reg_rdata_next[0] = '0;
       end
 
-      addr_hit[207]: begin
+      addr_hit[217]: begin
         reg_rdata_next[15:0] = classa_accum_cnt_qs;
       end
 
-      addr_hit[208]: begin
+      addr_hit[218]: begin
         reg_rdata_next[15:0] = classa_accum_thresh_qs;
       end
 
-      addr_hit[209]: begin
+      addr_hit[219]: begin
         reg_rdata_next[31:0] = classa_timeout_cyc_qs;
       end
 
-      addr_hit[210]: begin
+      addr_hit[220]: begin
         reg_rdata_next[31:0] = classa_phase0_cyc_qs;
       end
 
-      addr_hit[211]: begin
+      addr_hit[221]: begin
         reg_rdata_next[31:0] = classa_phase1_cyc_qs;
       end
 
-      addr_hit[212]: begin
+      addr_hit[222]: begin
         reg_rdata_next[31:0] = classa_phase2_cyc_qs;
       end
 
-      addr_hit[213]: begin
+      addr_hit[223]: begin
         reg_rdata_next[31:0] = classa_phase3_cyc_qs;
       end
 
-      addr_hit[214]: begin
+      addr_hit[224]: begin
         reg_rdata_next[31:0] = classa_esc_cnt_qs;
       end
 
-      addr_hit[215]: begin
+      addr_hit[225]: begin
         reg_rdata_next[2:0] = classa_state_qs;
       end
 
-      addr_hit[216]: begin
+      addr_hit[226]: begin
         reg_rdata_next[0] = classb_regwen_qs;
       end
 
-      addr_hit[217]: begin
+      addr_hit[227]: begin
         reg_rdata_next[0] = classb_ctrl_en_qs;
         reg_rdata_next[1] = classb_ctrl_lock_qs;
         reg_rdata_next[2] = classb_ctrl_en_e0_qs;
@@ -11199,55 +11589,55 @@
         reg_rdata_next[13:12] = classb_ctrl_map_e3_qs;
       end
 
-      addr_hit[218]: begin
+      addr_hit[228]: begin
         reg_rdata_next[0] = classb_clr_regwen_qs;
       end
 
-      addr_hit[219]: begin
+      addr_hit[229]: begin
         reg_rdata_next[0] = '0;
       end
 
-      addr_hit[220]: begin
+      addr_hit[230]: begin
         reg_rdata_next[15:0] = classb_accum_cnt_qs;
       end
 
-      addr_hit[221]: begin
+      addr_hit[231]: begin
         reg_rdata_next[15:0] = classb_accum_thresh_qs;
       end
 
-      addr_hit[222]: begin
+      addr_hit[232]: begin
         reg_rdata_next[31:0] = classb_timeout_cyc_qs;
       end
 
-      addr_hit[223]: begin
+      addr_hit[233]: begin
         reg_rdata_next[31:0] = classb_phase0_cyc_qs;
       end
 
-      addr_hit[224]: begin
+      addr_hit[234]: begin
         reg_rdata_next[31:0] = classb_phase1_cyc_qs;
       end
 
-      addr_hit[225]: begin
+      addr_hit[235]: begin
         reg_rdata_next[31:0] = classb_phase2_cyc_qs;
       end
 
-      addr_hit[226]: begin
+      addr_hit[236]: begin
         reg_rdata_next[31:0] = classb_phase3_cyc_qs;
       end
 
-      addr_hit[227]: begin
+      addr_hit[237]: begin
         reg_rdata_next[31:0] = classb_esc_cnt_qs;
       end
 
-      addr_hit[228]: begin
+      addr_hit[238]: begin
         reg_rdata_next[2:0] = classb_state_qs;
       end
 
-      addr_hit[229]: begin
+      addr_hit[239]: begin
         reg_rdata_next[0] = classc_regwen_qs;
       end
 
-      addr_hit[230]: begin
+      addr_hit[240]: begin
         reg_rdata_next[0] = classc_ctrl_en_qs;
         reg_rdata_next[1] = classc_ctrl_lock_qs;
         reg_rdata_next[2] = classc_ctrl_en_e0_qs;
@@ -11260,55 +11650,55 @@
         reg_rdata_next[13:12] = classc_ctrl_map_e3_qs;
       end
 
-      addr_hit[231]: begin
+      addr_hit[241]: begin
         reg_rdata_next[0] = classc_clr_regwen_qs;
       end
 
-      addr_hit[232]: begin
+      addr_hit[242]: begin
         reg_rdata_next[0] = '0;
       end
 
-      addr_hit[233]: begin
+      addr_hit[243]: begin
         reg_rdata_next[15:0] = classc_accum_cnt_qs;
       end
 
-      addr_hit[234]: begin
+      addr_hit[244]: begin
         reg_rdata_next[15:0] = classc_accum_thresh_qs;
       end
 
-      addr_hit[235]: begin
+      addr_hit[245]: begin
         reg_rdata_next[31:0] = classc_timeout_cyc_qs;
       end
 
-      addr_hit[236]: begin
+      addr_hit[246]: begin
         reg_rdata_next[31:0] = classc_phase0_cyc_qs;
       end
 
-      addr_hit[237]: begin
+      addr_hit[247]: begin
         reg_rdata_next[31:0] = classc_phase1_cyc_qs;
       end
 
-      addr_hit[238]: begin
+      addr_hit[248]: begin
         reg_rdata_next[31:0] = classc_phase2_cyc_qs;
       end
 
-      addr_hit[239]: begin
+      addr_hit[249]: begin
         reg_rdata_next[31:0] = classc_phase3_cyc_qs;
       end
 
-      addr_hit[240]: begin
+      addr_hit[250]: begin
         reg_rdata_next[31:0] = classc_esc_cnt_qs;
       end
 
-      addr_hit[241]: begin
+      addr_hit[251]: begin
         reg_rdata_next[2:0] = classc_state_qs;
       end
 
-      addr_hit[242]: begin
+      addr_hit[252]: begin
         reg_rdata_next[0] = classd_regwen_qs;
       end
 
-      addr_hit[243]: begin
+      addr_hit[253]: begin
         reg_rdata_next[0] = classd_ctrl_en_qs;
         reg_rdata_next[1] = classd_ctrl_lock_qs;
         reg_rdata_next[2] = classd_ctrl_en_e0_qs;
@@ -11321,47 +11711,47 @@
         reg_rdata_next[13:12] = classd_ctrl_map_e3_qs;
       end
 
-      addr_hit[244]: begin
+      addr_hit[254]: begin
         reg_rdata_next[0] = classd_clr_regwen_qs;
       end
 
-      addr_hit[245]: begin
+      addr_hit[255]: begin
         reg_rdata_next[0] = '0;
       end
 
-      addr_hit[246]: begin
+      addr_hit[256]: begin
         reg_rdata_next[15:0] = classd_accum_cnt_qs;
       end
 
-      addr_hit[247]: begin
+      addr_hit[257]: begin
         reg_rdata_next[15:0] = classd_accum_thresh_qs;
       end
 
-      addr_hit[248]: begin
+      addr_hit[258]: begin
         reg_rdata_next[31:0] = classd_timeout_cyc_qs;
       end
 
-      addr_hit[249]: begin
+      addr_hit[259]: begin
         reg_rdata_next[31:0] = classd_phase0_cyc_qs;
       end
 
-      addr_hit[250]: begin
+      addr_hit[260]: begin
         reg_rdata_next[31:0] = classd_phase1_cyc_qs;
       end
 
-      addr_hit[251]: begin
+      addr_hit[261]: begin
         reg_rdata_next[31:0] = classd_phase2_cyc_qs;
       end
 
-      addr_hit[252]: begin
+      addr_hit[262]: begin
         reg_rdata_next[31:0] = classd_phase3_cyc_qs;
       end
 
-      addr_hit[253]: begin
+      addr_hit[263]: begin
         reg_rdata_next[31:0] = classd_esc_cnt_qs;
       end
 
-      addr_hit[254]: begin
+      addr_hit[264]: begin
         reg_rdata_next[2:0] = classd_state_qs;
       end
 

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index b1dad90..d368df2 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

@@ -1230,7 +1230,9 @@
       .rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel])
   );
 
-  spi_host u_spi_host0 (
+  spi_host #(
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[0:0])
+  ) u_spi_host0 (
 
       // Input
       .cio_sd_i     (cio_spi_host0_sd_p2d),
@@ -1246,6 +1248,9 @@
       // Interrupt
       .intr_error_o     (intr_spi_host0_error),
       .intr_spi_event_o (intr_spi_host0_spi_event),
+      // [0]: fatal_fault
+      .alert_tx_o  ( alert_tx[0:0] ),
+      .alert_rx_i  ( alert_rx[0:0] ),
 
       // Inter-module signals
       .passthrough_i(spi_device_passthrough_req),
@@ -1261,7 +1266,9 @@
       .rst_core_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel])
   );
 
-  spi_host u_spi_host1 (
+  spi_host #(
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:1])
+  ) u_spi_host1 (
 
       // Input
       .cio_sd_i     (cio_spi_host1_sd_p2d),
@@ -1277,6 +1284,9 @@
       // Interrupt
       .intr_error_o     (intr_spi_host1_error),
       .intr_spi_event_o (intr_spi_host1_spi_event),
+      // [1]: fatal_fault
+      .alert_tx_o  ( alert_tx[1:1] ),
+      .alert_rx_i  ( alert_rx[1:1] ),
 
       // Inter-module signals
       .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
@@ -1517,7 +1527,7 @@
   );
 
   otp_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:0]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:2]),
     .MemInitFile(OtpCtrlMemInitFile),
     .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
     .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm)
@@ -1526,10 +1536,10 @@
       // Interrupt
       .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
       .intr_otp_error_o          (intr_otp_ctrl_otp_error),
-      // [0]: fatal_macro_error
-      // [1]: fatal_check_error
-      .alert_tx_o  ( alert_tx[1:0] ),
-      .alert_rx_i  ( alert_rx[1:0] ),
+      // [2]: fatal_macro_error
+      // [3]: fatal_check_error
+      .alert_tx_o  ( alert_tx[3:2] ),
+      .alert_rx_i  ( alert_rx[3:2] ),
 
       // Inter-module signals
       .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
@@ -1570,15 +1580,15 @@
   );
 
   lc_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:2]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[5:4]),
     .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
     .RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma),
     .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction)
   ) u_lc_ctrl (
-      // [2]: fatal_prog_error
-      // [3]: fatal_state_error
-      .alert_tx_o  ( alert_tx[3:2] ),
-      .alert_rx_i  ( alert_rx[3:2] ),
+      // [4]: fatal_prog_error
+      // [5]: fatal_state_error
+      .alert_tx_o  ( alert_tx[5:4] ),
+      .alert_rx_i  ( alert_rx[5:4] ),
 
       // Inter-module signals
       .jtag_i(pinmux_aon_lc_jtag_req),
@@ -1901,25 +1911,25 @@
   );
 
   sensor_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[14:4])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[16:6])
   ) u_sensor_ctrl_aon (
 
       // Output
       .cio_ast_debug_out_o    (cio_sensor_ctrl_aon_ast_debug_out_d2p),
       .cio_ast_debug_out_en_o (cio_sensor_ctrl_aon_ast_debug_out_en_d2p),
-      // [4]: recov_as
-      // [5]: recov_cg
-      // [6]: recov_gd
-      // [7]: recov_ts_hi
-      // [8]: recov_ts_lo
-      // [9]: recov_fla
-      // [10]: recov_otp
-      // [11]: recov_ot0
-      // [12]: recov_ot1
-      // [13]: recov_ot2
-      // [14]: recov_ot3
-      .alert_tx_o  ( alert_tx[14:4] ),
-      .alert_rx_i  ( alert_rx[14:4] ),
+      // [6]: recov_as
+      // [7]: recov_cg
+      // [8]: recov_gd
+      // [9]: recov_ts_hi
+      // [10]: recov_ts_lo
+      // [11]: recov_fla
+      // [12]: recov_otp
+      // [13]: recov_ot0
+      // [14]: recov_ot1
+      // [15]: recov_ot2
+      // [16]: recov_ot3
+      .alert_tx_o  ( alert_tx[16:6] ),
+      .alert_rx_i  ( alert_rx[16:6] ),
 
       // Inter-module signals
       .ast_alert_i(sensor_ctrl_ast_alert_req_i),
@@ -1936,16 +1946,16 @@
   );
 
   sram_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[16:15]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:17]),
     .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey),
     .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce),
     .RndCnstSramLfsrPerm(RndCnstSramCtrlRetAonSramLfsrPerm),
     .InstrExec(SramCtrlRetAonInstrExec)
   ) u_sram_ctrl_ret_aon (
-      // [15]: fatal_intg_error
-      // [16]: fatal_parity_error
-      .alert_tx_o  ( alert_tx[16:15] ),
-      .alert_rx_i  ( alert_rx[16:15] ),
+      // [17]: fatal_intg_error
+      // [18]: fatal_parity_error
+      .alert_tx_o  ( alert_tx[18:17] ),
+      .alert_rx_i  ( alert_rx[18:17] ),
 
       // Inter-module signals
       .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]),
@@ -1970,7 +1980,7 @@
   );
 
   flash_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:17]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:19]),
     .RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
     .RndCnstDataKey(RndCnstFlashCtrlDataKey),
     .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
@@ -1993,12 +2003,12 @@
       .intr_rd_lvl_o     (intr_flash_ctrl_rd_lvl),
       .intr_op_done_o    (intr_flash_ctrl_op_done),
       .intr_err_o        (intr_flash_ctrl_err),
-      // [17]: recov_err
-      // [18]: recov_mp_err
-      // [19]: recov_ecc_err
-      // [20]: fatal_intg_err
-      .alert_tx_o  ( alert_tx[20:17] ),
-      .alert_rx_i  ( alert_rx[20:17] ),
+      // [19]: recov_err
+      // [20]: recov_mp_err
+      // [21]: recov_ecc_err
+      // [22]: fatal_intg_err
+      .alert_tx_o  ( alert_tx[22:19] ),
+      .alert_rx_i  ( alert_rx[22:19] ),
 
       // Inter-module signals
       .flash_o(flash_ctrl_flash_req),
@@ -2044,7 +2054,7 @@
   );
 
   aes #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:21]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:23]),
     .AES192Enable(1'b1),
     .Masking(AesMasking),
     .SBoxImpl(AesSBoxImpl),
@@ -2057,10 +2067,10 @@
     .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
     .RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm)
   ) u_aes (
-      // [21]: recov_ctrl_update_err
-      // [22]: fatal_fault
-      .alert_tx_o  ( alert_tx[22:21] ),
-      .alert_rx_i  ( alert_rx[22:21] ),
+      // [23]: recov_ctrl_update_err
+      // [24]: fatal_fault
+      .alert_tx_o  ( alert_tx[24:23] ),
+      .alert_rx_i  ( alert_rx[24:23] ),
 
       // Inter-module signals
       .idle_o(clkmgr_aon_idle[0]),
@@ -2078,16 +2088,16 @@
   );
 
   hmac #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:23])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:25])
   ) u_hmac (
 
       // Interrupt
       .intr_hmac_done_o  (intr_hmac_hmac_done),
       .intr_fifo_empty_o (intr_hmac_fifo_empty),
       .intr_hmac_err_o   (intr_hmac_hmac_err),
-      // [23]: fatal_fault
-      .alert_tx_o  ( alert_tx[23:23] ),
-      .alert_rx_i  ( alert_rx[23:23] ),
+      // [25]: fatal_fault
+      .alert_tx_o  ( alert_tx[25:25] ),
+      .alert_rx_i  ( alert_rx[25:25] ),
 
       // Inter-module signals
       .idle_o(clkmgr_aon_idle[1]),
@@ -2100,7 +2110,7 @@
   );
 
   kmac #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:24]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:26]),
     .EnMasking(KmacEnMasking),
     .ReuseShare(KmacReuseShare)
   ) u_kmac (
@@ -2109,9 +2119,9 @@
       .intr_kmac_done_o  (intr_kmac_kmac_done),
       .intr_fifo_empty_o (intr_kmac_fifo_empty),
       .intr_kmac_err_o   (intr_kmac_kmac_err),
-      // [24]: fatal_fault
-      .alert_tx_o  ( alert_tx[24:24] ),
-      .alert_rx_i  ( alert_rx[24:24] ),
+      // [26]: fatal_fault
+      .alert_tx_o  ( alert_tx[26:26] ),
+      .alert_rx_i  ( alert_rx[26:26] ),
 
       // Inter-module signals
       .keymgr_key_i(keymgr_kmac_key),
@@ -2131,7 +2141,7 @@
   );
 
   keymgr #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:25]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:27]),
     .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
     .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
     .RndCnstRandPerm(RndCnstKeymgrRandPerm),
@@ -2149,10 +2159,10 @@
 
       // Interrupt
       .intr_op_done_o (intr_keymgr_op_done),
-      // [25]: fatal_fault_err
-      // [26]: recov_operation_err
-      .alert_tx_o  ( alert_tx[26:25] ),
-      .alert_rx_i  ( alert_rx[26:25] ),
+      // [27]: fatal_fault_err
+      // [28]: recov_operation_err
+      .alert_tx_o  ( alert_tx[28:27] ),
+      .alert_rx_i  ( alert_rx[28:27] ),
 
       // Inter-module signals
       .edn_o(edn0_edn_req[0]),
@@ -2179,7 +2189,7 @@
   );
 
   csrng #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:27]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29]),
     .SBoxImpl(CsrngSBoxImpl)
   ) u_csrng (
 
@@ -2188,9 +2198,9 @@
       .intr_cs_entropy_req_o  (intr_csrng_cs_entropy_req),
       .intr_cs_hw_inst_exc_o  (intr_csrng_cs_hw_inst_exc),
       .intr_cs_fatal_err_o    (intr_csrng_cs_fatal_err),
-      // [27]: fatal_alert
-      .alert_tx_o  ( alert_tx[27:27] ),
-      .alert_rx_i  ( alert_rx[27:27] ),
+      // [29]: fatal_alert
+      .alert_tx_o  ( alert_tx[29:29] ),
+      .alert_rx_i  ( alert_rx[29:29] ),
 
       // Inter-module signals
       .csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2210,7 +2220,7 @@
   );
 
   entropy_src #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:28]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:30]),
     .Stub(EntropySrcStub)
   ) u_entropy_src (
 
@@ -2219,10 +2229,10 @@
       .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
       .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
       .intr_es_fatal_err_o          (intr_entropy_src_es_fatal_err),
-      // [28]: recov_alert
-      // [29]: fatal_alert
-      .alert_tx_o  ( alert_tx[29:28] ),
-      .alert_rx_i  ( alert_rx[29:28] ),
+      // [30]: recov_alert
+      // [31]: fatal_alert
+      .alert_tx_o  ( alert_tx[31:30] ),
+      .alert_rx_i  ( alert_rx[31:30] ),
 
       // Inter-module signals
       .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2245,15 +2255,15 @@
   );
 
   edn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[32:32])
   ) u_edn0 (
 
       // Interrupt
       .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
       .intr_edn_fatal_err_o    (intr_edn0_edn_fatal_err),
-      // [30]: fatal_alert
-      .alert_tx_o  ( alert_tx[30:30] ),
-      .alert_rx_i  ( alert_rx[30:30] ),
+      // [32]: fatal_alert
+      .alert_tx_o  ( alert_tx[32:32] ),
+      .alert_rx_i  ( alert_rx[32:32] ),
 
       // Inter-module signals
       .csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2269,15 +2279,15 @@
   );
 
   edn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:33])
   ) u_edn1 (
 
       // Interrupt
       .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
       .intr_edn_fatal_err_o    (intr_edn1_edn_fatal_err),
-      // [31]: fatal_alert
-      .alert_tx_o  ( alert_tx[31:31] ),
-      .alert_rx_i  ( alert_rx[31:31] ),
+      // [33]: fatal_alert
+      .alert_tx_o  ( alert_tx[33:33] ),
+      .alert_rx_i  ( alert_rx[33:33] ),
 
       // Inter-module signals
       .csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2293,16 +2303,16 @@
   );
 
   sram_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:34]),
     .RndCnstSramKey(RndCnstSramCtrlMainSramKey),
     .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
     .RndCnstSramLfsrPerm(RndCnstSramCtrlMainSramLfsrPerm),
     .InstrExec(SramCtrlMainInstrExec)
   ) u_sram_ctrl_main (
-      // [32]: fatal_intg_error
-      // [33]: fatal_parity_error
-      .alert_tx_o  ( alert_tx[33:32] ),
-      .alert_rx_i  ( alert_rx[33:32] ),
+      // [34]: fatal_intg_error
+      // [35]: fatal_parity_error
+      .alert_tx_o  ( alert_tx[35:34] ),
+      .alert_rx_i  ( alert_rx[35:34] ),
 
       // Inter-module signals
       .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2327,7 +2337,7 @@
   );
 
   otbn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:34]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:36]),
     .Stub(OtbnStub),
     .RegFile(OtbnRegFile),
     .RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed),
@@ -2336,10 +2346,10 @@
 
       // Interrupt
       .intr_done_o (intr_otbn_done),
-      // [34]: fatal
-      // [35]: recov
-      .alert_tx_o  ( alert_tx[35:34] ),
-      .alert_rx_i  ( alert_rx[35:34] ),
+      // [36]: fatal
+      // [37]: recov
+      .alert_tx_o  ( alert_tx[37:36] ),
+      .alert_rx_i  ( alert_rx[37:36] ),
 
       // Inter-module signals
       .edn_rnd_o(edn1_edn_req[0]),
@@ -2359,15 +2369,15 @@
   );
 
   rom_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[36:36]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:38]),
     .BootRomInitFile(RomCtrlBootRomInitFile),
     .RndCnstScrNonce(RndCnstRomCtrlScrNonce),
     .RndCnstScrKey(RndCnstRomCtrlScrKey),
     .SkipCheck(RomCtrlSkipCheck)
   ) u_rom_ctrl (
-      // [36]: fatal
-      .alert_tx_o  ( alert_tx[36:36] ),
-      .alert_rx_i  ( alert_rx[36:36] ),
+      // [38]: fatal
+      .alert_tx_o  ( alert_tx[38:38] ),
+      .alert_rx_i  ( alert_rx[38:38] ),
 
       // Inter-module signals
       .rom_cfg_i(ast_rom_cfg),

diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index f8b49f3..49a6de6 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c

@@ -202,7 +202,9 @@
  * `top_earlgrey_alert_peripheral_t`.
  */
 const top_earlgrey_alert_peripheral_t
-    top_earlgrey_alert_for_peripheral[37] = {
+    top_earlgrey_alert_for_peripheral[39] = {
+  [kTopEarlgreyAlertIdSpiHost0FatalFault] = kTopEarlgreyAlertPeripheralSpiHost0,
+  [kTopEarlgreyAlertIdSpiHost1FatalFault] = kTopEarlgreyAlertPeripheralSpiHost1,
   [kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl,
   [kTopEarlgreyAlertIdOtpCtrlFatalCheckError] = kTopEarlgreyAlertPeripheralOtpCtrl,
   [kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl,

diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 31a7632..298d1a0 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h

@@ -1088,23 +1088,25 @@
  * alert.
  */
 typedef enum top_earlgrey_alert_peripheral {
-  kTopEarlgreyAlertPeripheralOtpCtrl = 0, /**< otp_ctrl */
-  kTopEarlgreyAlertPeripheralLcCtrl = 1, /**< lc_ctrl */
-  kTopEarlgreyAlertPeripheralSensorCtrlAon = 2, /**< sensor_ctrl_aon */
-  kTopEarlgreyAlertPeripheralSramCtrlRetAon = 3, /**< sram_ctrl_ret_aon */
-  kTopEarlgreyAlertPeripheralFlashCtrl = 4, /**< flash_ctrl */
-  kTopEarlgreyAlertPeripheralAes = 5, /**< aes */
-  kTopEarlgreyAlertPeripheralHmac = 6, /**< hmac */
-  kTopEarlgreyAlertPeripheralKmac = 7, /**< kmac */
-  kTopEarlgreyAlertPeripheralKeymgr = 8, /**< keymgr */
-  kTopEarlgreyAlertPeripheralCsrng = 9, /**< csrng */
-  kTopEarlgreyAlertPeripheralEntropySrc = 10, /**< entropy_src */
-  kTopEarlgreyAlertPeripheralEdn0 = 11, /**< edn0 */
-  kTopEarlgreyAlertPeripheralEdn1 = 12, /**< edn1 */
-  kTopEarlgreyAlertPeripheralSramCtrlMain = 13, /**< sram_ctrl_main */
-  kTopEarlgreyAlertPeripheralOtbn = 14, /**< otbn */
-  kTopEarlgreyAlertPeripheralRomCtrl = 15, /**< rom_ctrl */
-  kTopEarlgreyAlertPeripheralLast = 15, /**< \internal Final Alert peripheral */
+  kTopEarlgreyAlertPeripheralSpiHost0 = 0, /**< spi_host0 */
+  kTopEarlgreyAlertPeripheralSpiHost1 = 1, /**< spi_host1 */
+  kTopEarlgreyAlertPeripheralOtpCtrl = 2, /**< otp_ctrl */
+  kTopEarlgreyAlertPeripheralLcCtrl = 3, /**< lc_ctrl */
+  kTopEarlgreyAlertPeripheralSensorCtrlAon = 4, /**< sensor_ctrl_aon */
+  kTopEarlgreyAlertPeripheralSramCtrlRetAon = 5, /**< sram_ctrl_ret_aon */
+  kTopEarlgreyAlertPeripheralFlashCtrl = 6, /**< flash_ctrl */
+  kTopEarlgreyAlertPeripheralAes = 7, /**< aes */
+  kTopEarlgreyAlertPeripheralHmac = 8, /**< hmac */
+  kTopEarlgreyAlertPeripheralKmac = 9, /**< kmac */
+  kTopEarlgreyAlertPeripheralKeymgr = 10, /**< keymgr */
+  kTopEarlgreyAlertPeripheralCsrng = 11, /**< csrng */
+  kTopEarlgreyAlertPeripheralEntropySrc = 12, /**< entropy_src */
+  kTopEarlgreyAlertPeripheralEdn0 = 13, /**< edn0 */
+  kTopEarlgreyAlertPeripheralEdn1 = 14, /**< edn1 */
+  kTopEarlgreyAlertPeripheralSramCtrlMain = 15, /**< sram_ctrl_main */
+  kTopEarlgreyAlertPeripheralOtbn = 16, /**< otbn */
+  kTopEarlgreyAlertPeripheralRomCtrl = 17, /**< rom_ctrl */
+  kTopEarlgreyAlertPeripheralLast = 17, /**< \internal Final Alert peripheral */
 } top_earlgrey_alert_peripheral_t;
 
 /**
@@ -1114,44 +1116,46 @@
  * the same peripheral are guaranteed to be consecutive.
  */
 typedef enum top_earlgrey_alert_id {
-  kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 0, /**< otp_ctrl_fatal_macro_error */
-  kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 1, /**< otp_ctrl_fatal_check_error */
-  kTopEarlgreyAlertIdLcCtrlFatalProgError = 2, /**< lc_ctrl_fatal_prog_error */
-  kTopEarlgreyAlertIdLcCtrlFatalStateError = 3, /**< lc_ctrl_fatal_state_error */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 4, /**< sensor_ctrl_aon_recov_as */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 5, /**< sensor_ctrl_aon_recov_cg */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 6, /**< sensor_ctrl_aon_recov_gd */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 7, /**< sensor_ctrl_aon_recov_ts_hi */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 8, /**< sensor_ctrl_aon_recov_ts_lo */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 9, /**< sensor_ctrl_aon_recov_fla */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 10, /**< sensor_ctrl_aon_recov_otp */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 11, /**< sensor_ctrl_aon_recov_ot0 */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 12, /**< sensor_ctrl_aon_recov_ot1 */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 13, /**< sensor_ctrl_aon_recov_ot2 */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 14, /**< sensor_ctrl_aon_recov_ot3 */
-  kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 15, /**< sram_ctrl_ret_aon_fatal_intg_error */
-  kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 16, /**< sram_ctrl_ret_aon_fatal_parity_error */
-  kTopEarlgreyAlertIdFlashCtrlRecovErr = 17, /**< flash_ctrl_recov_err */
-  kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 18, /**< flash_ctrl_recov_mp_err */
-  kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 19, /**< flash_ctrl_recov_ecc_err */
-  kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 20, /**< flash_ctrl_fatal_intg_err */
-  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 21, /**< aes_recov_ctrl_update_err */
-  kTopEarlgreyAlertIdAesFatalFault = 22, /**< aes_fatal_fault */
-  kTopEarlgreyAlertIdHmacFatalFault = 23, /**< hmac_fatal_fault */
-  kTopEarlgreyAlertIdKmacFatalFault = 24, /**< kmac_fatal_fault */
-  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 25, /**< keymgr_fatal_fault_err */
-  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 26, /**< keymgr_recov_operation_err */
-  kTopEarlgreyAlertIdCsrngFatalAlert = 27, /**< csrng_fatal_alert */
-  kTopEarlgreyAlertIdEntropySrcRecovAlert = 28, /**< entropy_src_recov_alert */
-  kTopEarlgreyAlertIdEntropySrcFatalAlert = 29, /**< entropy_src_fatal_alert */
-  kTopEarlgreyAlertIdEdn0FatalAlert = 30, /**< edn0_fatal_alert */
-  kTopEarlgreyAlertIdEdn1FatalAlert = 31, /**< edn1_fatal_alert */
-  kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 32, /**< sram_ctrl_main_fatal_intg_error */
-  kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 33, /**< sram_ctrl_main_fatal_parity_error */
-  kTopEarlgreyAlertIdOtbnFatal = 34, /**< otbn_fatal */
-  kTopEarlgreyAlertIdOtbnRecov = 35, /**< otbn_recov */
-  kTopEarlgreyAlertIdRomCtrlFatal = 36, /**< rom_ctrl_fatal */
-  kTopEarlgreyAlertIdLast = 36, /**< \internal The Last Valid Alert ID. */
+  kTopEarlgreyAlertIdSpiHost0FatalFault = 0, /**< spi_host0_fatal_fault */
+  kTopEarlgreyAlertIdSpiHost1FatalFault = 1, /**< spi_host1_fatal_fault */
+  kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 2, /**< otp_ctrl_fatal_macro_error */
+  kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 3, /**< otp_ctrl_fatal_check_error */
+  kTopEarlgreyAlertIdLcCtrlFatalProgError = 4, /**< lc_ctrl_fatal_prog_error */
+  kTopEarlgreyAlertIdLcCtrlFatalStateError = 5, /**< lc_ctrl_fatal_state_error */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 6, /**< sensor_ctrl_aon_recov_as */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 7, /**< sensor_ctrl_aon_recov_cg */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 8, /**< sensor_ctrl_aon_recov_gd */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 9, /**< sensor_ctrl_aon_recov_ts_hi */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 10, /**< sensor_ctrl_aon_recov_ts_lo */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 11, /**< sensor_ctrl_aon_recov_fla */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 12, /**< sensor_ctrl_aon_recov_otp */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 13, /**< sensor_ctrl_aon_recov_ot0 */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 14, /**< sensor_ctrl_aon_recov_ot1 */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 15, /**< sensor_ctrl_aon_recov_ot2 */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 16, /**< sensor_ctrl_aon_recov_ot3 */
+  kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 17, /**< sram_ctrl_ret_aon_fatal_intg_error */
+  kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 18, /**< sram_ctrl_ret_aon_fatal_parity_error */
+  kTopEarlgreyAlertIdFlashCtrlRecovErr = 19, /**< flash_ctrl_recov_err */
+  kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 20, /**< flash_ctrl_recov_mp_err */
+  kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 21, /**< flash_ctrl_recov_ecc_err */
+  kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 22, /**< flash_ctrl_fatal_intg_err */
+  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 23, /**< aes_recov_ctrl_update_err */
+  kTopEarlgreyAlertIdAesFatalFault = 24, /**< aes_fatal_fault */
+  kTopEarlgreyAlertIdHmacFatalFault = 25, /**< hmac_fatal_fault */
+  kTopEarlgreyAlertIdKmacFatalFault = 26, /**< kmac_fatal_fault */
+  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 27, /**< keymgr_fatal_fault_err */
+  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 28, /**< keymgr_recov_operation_err */
+  kTopEarlgreyAlertIdCsrngFatalAlert = 29, /**< csrng_fatal_alert */
+  kTopEarlgreyAlertIdEntropySrcRecovAlert = 30, /**< entropy_src_recov_alert */
+  kTopEarlgreyAlertIdEntropySrcFatalAlert = 31, /**< entropy_src_fatal_alert */
+  kTopEarlgreyAlertIdEdn0FatalAlert = 32, /**< edn0_fatal_alert */
+  kTopEarlgreyAlertIdEdn1FatalAlert = 33, /**< edn1_fatal_alert */
+  kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 34, /**< sram_ctrl_main_fatal_intg_error */
+  kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 35, /**< sram_ctrl_main_fatal_parity_error */
+  kTopEarlgreyAlertIdOtbnFatal = 36, /**< otbn_fatal */
+  kTopEarlgreyAlertIdOtbnRecov = 37, /**< otbn_recov */
+  kTopEarlgreyAlertIdRomCtrlFatal = 38, /**< rom_ctrl_fatal */
+  kTopEarlgreyAlertIdLast = 38, /**< \internal The Last Valid Alert ID. */
 } top_earlgrey_alert_id_t;
 
 /**
@@ -1161,7 +1165,7 @@
  * `top_earlgrey_alert_peripheral_t`.
  */
 extern const top_earlgrey_alert_peripheral_t
-    top_earlgrey_alert_for_peripheral[37];
+    top_earlgrey_alert_for_peripheral[39];
 
 #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
commit	bd21d5a2994b71fb16c70ce283a0c67e03d3e354	[log] [tgz]
author	Michael Schaffner <msf@opentitan.org>	Mon Jun 07 16:38:34 2021 -0700
committer	Michael Schaffner <msf@google.com>	Tue Jun 08 12:50:59 2021 -0700
tree	ed399daa836b009c9af7acc3623d389be6881814
parent	8a6bedc600ccb8f690724f6a71b96c0fce166a9b [diff]