[lc_ctrl] Increase number of test states from 4 to 8
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv
index 39a42c4..83de6c6 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv
@@ -102,89 +102,77 @@
// Manufacturing State Transition Matrix //
///////////////////////////////////////////
+ // Helper macro to assemble the token index matrix below.
+ // From TEST_UNLOCKED(N)
+ // -> SCRAP, RMA
+ // -> PROD, PROD_END, DEV
+ // -> TEST_UNLOCKED(N+1)-7
+ // -> TEST_LOCKED(N)-6
+ // -> TEST_UNLOCKED0-(N), RAW
+ `define TEST_UNLOCKED(idx) \
+ {2{ZeroTokenIdx}}, \
+ {3{TestExitTokenIdx}}, \
+ {(7-idx){InvalidTokenIdx, \
+ ZeroTokenIdx}}, \
+ {(2*idx+2){InvalidTokenIdx}}
+
+ // Helper macro to assemble the token index matrix below.
+ // From TEST_LOCKED(N)
+ // -> SCRAP
+ // -> RMA
+ // -> PROD, PROD_END, DEV
+ // -> TEST_UNLOCKED(N+1)-7
+ // -> TEST_LOCKED(N)-6
+ // -> TEST_UNLOCKED0-(N), RAW
+ `define TEST_LOCKED(idx) \
+ ZeroTokenIdx, \
+ InvalidTokenIdx, \
+ {3{TestExitTokenIdx}}, \
+ {(7-idx){TestUnlockTokenIdx, \
+ InvalidTokenIdx}}, \
+ {(2*idx+2){InvalidTokenIdx}}
+
// The token index matrix below encodes 1) which transition edges are valid and 2) which token
// to use for a given transition edge. Note that unconditional but otherwise valid transitions
// are assigned the ZeroTokenIdx, whereas invalid transitions are assigned an InvalidTokenIdx.
parameter token_idx_e [NumLcStates-1:0][NumLcStates-1:0] TransTokenIdxMatrix = {
// SCRAP
- {13{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA, SCRAP
+ {21{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END, RMA, SCRAP
// RMA
ZeroTokenIdx, // -> SCRAP
- {12{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA
+ {20{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END, RMA
// PROD_END
ZeroTokenIdx, // -> SCRAP
- {12{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA
+ {20{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END, RMA
// PROD
ZeroTokenIdx, // -> SCRAP
RmaTokenIdx, // -> RMA
- {11{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END
+ {19{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END
// DEV
ZeroTokenIdx, // -> SCRAP
RmaTokenIdx, // -> RMA
- {11{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END
- // TEST_UNLOCKED3
- {2{ZeroTokenIdx}}, // -> SCRAP, RMA
- {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
- {8{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, RAW
- // TEST_LOCKED2
- ZeroTokenIdx, // -> SCRAP
- InvalidTokenIdx, // -> RMA
- {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
- TestUnlockTokenIdx, // -> TEST_UNLOCKED3
- {7{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-2, RAW
- // TEST_UNLOCKED2
- {2{ZeroTokenIdx}}, // -> SCRAP, RMA
- {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
- InvalidTokenIdx, // -> TEST_UNLOCKED3
- ZeroTokenIdx, // -> TEST_LOCKED2
- {6{InvalidTokenIdx}}, // -> TEST_LOCKED0-1, TEST_UNLOCKED0-2, RAW
- // TEST_LOCKED1
- ZeroTokenIdx, // -> SCRAP
- InvalidTokenIdx, // -> RMA
- {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
- TestUnlockTokenIdx, // -> TEST_UNLOCKED3
- InvalidTokenIdx , // -> TEST_LOCKED2
- TestUnlockTokenIdx, // -> TEST_UNLOCKED2
- {5{InvalidTokenIdx}}, // -> TEST_LOCKED0-1, TEST_UNLOCKED0-1, RAW
- // TEST_UNLOCKED1
- {2{ZeroTokenIdx}}, // -> SCRAP, RMA
- {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
- InvalidTokenIdx, // -> TEST_UNLOCKED3
- ZeroTokenIdx, // -> TEST_LOCKED2
- InvalidTokenIdx, // -> TEST_UNLOCKED2
- ZeroTokenIdx, // -> TEST_LOCKED1
- {4{InvalidTokenIdx}}, // -> TEST_LOCKED0, TEST_UNLOCKED0-1, RAW
- // TEST_LOCKED0
- ZeroTokenIdx, // -> SCRAP
- InvalidTokenIdx, // -> RMA
- {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
- TestUnlockTokenIdx, // -> TEST_UNLOCKED3
- InvalidTokenIdx, // -> TEST_LOCKED2
- TestUnlockTokenIdx, // -> TEST_UNLOCKED2
- InvalidTokenIdx, // -> TEST_LOCKED1
- TestUnlockTokenIdx, // -> TEST_UNLOCKED1
- {3{InvalidTokenIdx}}, // -> TEST_LOCKED0, TEST_UNLOCKED0, RAW
- // TEST_UNLOCKED0
- {2{ZeroTokenIdx}}, // -> SCRAP, RMA
- {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
- InvalidTokenIdx, // -> TEST_UNLOCKED3
- ZeroTokenIdx, // -> TEST_LOCKED2
- InvalidTokenIdx, // -> TEST_UNLOCKED2
- ZeroTokenIdx, // -> TEST_LOCKED1
- InvalidTokenIdx, // -> TEST_UNLOCKED1
- ZeroTokenIdx, // -> TEST_LOCKED0
- {2{InvalidTokenIdx}}, // -> TEST_UNLOCKED0, RAW
+ {19{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END
+ // TEST_UNLOCKED0-7, TEST_LOCKED0-6
+ `TEST_UNLOCKED(7),
+ `TEST_LOCKED(6),
+ `TEST_UNLOCKED(6),
+ `TEST_LOCKED(5),
+ `TEST_UNLOCKED(5),
+ `TEST_LOCKED(4),
+ `TEST_UNLOCKED(4),
+ `TEST_LOCKED(3),
+ `TEST_UNLOCKED(3),
+ `TEST_LOCKED(2),
+ `TEST_UNLOCKED(2),
+ `TEST_LOCKED(1),
+ `TEST_UNLOCKED(1),
+ `TEST_LOCKED(0),
+ `TEST_UNLOCKED(0),
// RAW
ZeroTokenIdx, // -> SCRAP
{4{InvalidTokenIdx}}, // -> RMA, PROD, PROD_END, DEV
- RawUnlockTokenIdx, // -> TEST_UNLOCKED3
- InvalidTokenIdx, // -> TEST_LOCKED2
- RawUnlockTokenIdx, // -> TEST_UNLOCKED2
- InvalidTokenIdx, // -> TEST_LOCKED1
- RawUnlockTokenIdx, // -> TEST_UNLOCKED1
- InvalidTokenIdx, // -> TEST_LOCKED0
- RawUnlockTokenIdx, // -> TEST_UNLOCKED0
- InvalidTokenIdx // -> RAW
+ {8{RawUnlockTokenIdx, // -> TEST_UNLOCKED0-7
+ InvalidTokenIdx}} // -> RAW, TEST_LOCKED0-6
};
endpackage : lc_ctrl_pkg
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
index fcbedfc..d3e1536 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
@@ -8,7 +8,7 @@
// Param list
parameter int NumTokenWords = 4;
- parameter int CsrLcStateWidth = 4;
+ parameter int CsrLcStateWidth = 5;
parameter int CsrLcCountWidth = 5;
parameter int CsrLcIdStateWidth = 2;
parameter int CsrOtpTestCtrlWidth = 8;
@@ -53,7 +53,7 @@
} lc_ctrl_reg2hw_transition_token_mreg_t;
typedef struct packed {
- logic [3:0] q;
+ logic [4:0] q;
logic qe;
} lc_ctrl_reg2hw_transition_target_reg_t;
@@ -114,7 +114,7 @@
} lc_ctrl_hw2reg_transition_token_mreg_t;
typedef struct packed {
- logic [3:0] d;
+ logic [4:0] d;
} lc_ctrl_hw2reg_transition_target_reg_t;
typedef struct packed {
@@ -127,7 +127,7 @@
} lc_ctrl_hw2reg_otp_test_ctrl_reg_t;
typedef struct packed {
- logic [3:0] d;
+ logic [4:0] d;
} lc_ctrl_hw2reg_lc_state_reg_t;
typedef struct packed {
@@ -144,23 +144,23 @@
// Register -> HW type
typedef struct packed {
- lc_ctrl_reg2hw_alert_test_reg_t alert_test; // [164:159]
- lc_ctrl_reg2hw_claim_transition_if_reg_t claim_transition_if; // [158:150]
- lc_ctrl_reg2hw_transition_cmd_reg_t transition_cmd; // [149:148]
- lc_ctrl_reg2hw_transition_token_mreg_t [3:0] transition_token; // [147:16]
- lc_ctrl_reg2hw_transition_target_reg_t transition_target; // [15:11]
+ lc_ctrl_reg2hw_alert_test_reg_t alert_test; // [165:160]
+ lc_ctrl_reg2hw_claim_transition_if_reg_t claim_transition_if; // [159:151]
+ lc_ctrl_reg2hw_transition_cmd_reg_t transition_cmd; // [150:149]
+ lc_ctrl_reg2hw_transition_token_mreg_t [3:0] transition_token; // [148:17]
+ lc_ctrl_reg2hw_transition_target_reg_t transition_target; // [16:11]
lc_ctrl_reg2hw_otp_test_ctrl_reg_t otp_test_ctrl; // [10:0]
} lc_ctrl_reg2hw_t;
// HW -> register type
typedef struct packed {
- lc_ctrl_hw2reg_status_reg_t status; // [426:417]
- lc_ctrl_hw2reg_claim_transition_if_reg_t claim_transition_if; // [416:409]
- lc_ctrl_hw2reg_transition_regwen_reg_t transition_regwen; // [408:408]
- lc_ctrl_hw2reg_transition_token_mreg_t [3:0] transition_token; // [407:280]
- lc_ctrl_hw2reg_transition_target_reg_t transition_target; // [279:276]
- lc_ctrl_hw2reg_otp_test_ctrl_reg_t otp_test_ctrl; // [275:267]
- lc_ctrl_hw2reg_lc_state_reg_t lc_state; // [266:263]
+ lc_ctrl_hw2reg_status_reg_t status; // [428:419]
+ lc_ctrl_hw2reg_claim_transition_if_reg_t claim_transition_if; // [418:411]
+ lc_ctrl_hw2reg_transition_regwen_reg_t transition_regwen; // [410:410]
+ lc_ctrl_hw2reg_transition_token_mreg_t [3:0] transition_token; // [409:282]
+ lc_ctrl_hw2reg_transition_target_reg_t transition_target; // [281:277]
+ lc_ctrl_hw2reg_otp_test_ctrl_reg_t otp_test_ctrl; // [276:268]
+ lc_ctrl_hw2reg_lc_state_reg_t lc_state; // [267:263]
lc_ctrl_hw2reg_lc_transition_cnt_reg_t lc_transition_cnt; // [262:258]
lc_ctrl_hw2reg_lc_id_state_reg_t lc_id_state; // [257:256]
lc_ctrl_hw2reg_device_id_mreg_t [7:0] device_id; // [255:0]
@@ -204,9 +204,9 @@
parameter logic [31:0] LC_CTRL_TRANSITION_TOKEN_1_RESVAL = 32'h 0;
parameter logic [31:0] LC_CTRL_TRANSITION_TOKEN_2_RESVAL = 32'h 0;
parameter logic [31:0] LC_CTRL_TRANSITION_TOKEN_3_RESVAL = 32'h 0;
- parameter logic [3:0] LC_CTRL_TRANSITION_TARGET_RESVAL = 4'h 0;
+ parameter logic [4:0] LC_CTRL_TRANSITION_TARGET_RESVAL = 5'h 0;
parameter logic [16:0] LC_CTRL_OTP_TEST_CTRL_RESVAL = 17'h 0;
- parameter logic [3:0] LC_CTRL_LC_STATE_RESVAL = 4'h 0;
+ parameter logic [4:0] LC_CTRL_LC_STATE_RESVAL = 5'h 0;
parameter logic [4:0] LC_CTRL_LC_TRANSITION_CNT_RESVAL = 5'h 0;
parameter logic [1:0] LC_CTRL_LC_ID_STATE_RESVAL = 2'h 0;
parameter logic [31:0] LC_CTRL_DEVICE_ID_0_RESVAL = 32'h 0;
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv
index 0bac7bf..b594b3f 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv
@@ -145,8 +145,8 @@
logic [31:0] transition_token_3_wd;
logic transition_target_re;
logic transition_target_we;
- logic [3:0] transition_target_qs;
- logic [3:0] transition_target_wd;
+ logic [4:0] transition_target_qs;
+ logic [4:0] transition_target_wd;
logic otp_test_ctrl_re;
logic otp_test_ctrl_we;
logic [7:0] otp_test_ctrl_val_qs;
@@ -154,7 +154,7 @@
logic otp_test_ctrl_ext_clock_qs;
logic otp_test_ctrl_ext_clock_wd;
logic lc_state_re;
- logic [3:0] lc_state_qs;
+ logic [4:0] lc_state_qs;
logic lc_transition_cnt_re;
logic [4:0] lc_transition_cnt_qs;
logic lc_id_state_re;
@@ -493,7 +493,7 @@
// R[transition_target]: V(True)
prim_subreg_ext #(
- .DW (4)
+ .DW (5)
) u_transition_target (
.re (transition_target_re),
.we (transition_target_we & transition_regwen_qs),
@@ -541,7 +541,7 @@
// R[lc_state]: V(True)
prim_subreg_ext #(
- .DW (4)
+ .DW (5)
) u_lc_state (
.re (lc_state_re),
.we (1'b0),
@@ -808,7 +808,7 @@
assign transition_target_re = addr_hit[9] & reg_re & !reg_error;
assign transition_target_we = addr_hit[9] & reg_we & !reg_error;
- assign transition_target_wd = reg_wdata[3:0];
+ assign transition_target_wd = reg_wdata[4:0];
assign otp_test_ctrl_re = addr_hit[10] & reg_re & !reg_error;
assign otp_test_ctrl_we = addr_hit[10] & reg_we & !reg_error;
@@ -879,7 +879,7 @@
end
addr_hit[9]: begin
- reg_rdata_next[3:0] = transition_target_qs;
+ reg_rdata_next[4:0] = transition_target_qs;
end
addr_hit[10]: begin
@@ -888,7 +888,7 @@
end
addr_hit[11]: begin
- reg_rdata_next[3:0] = lc_state_qs;
+ reg_rdata_next[4:0] = lc_state_qs;
end
addr_hit[12]: begin
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_signal_decode.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl_signal_decode.sv
index f5080b1..a569db8 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_signal_decode.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_signal_decode.sv
@@ -91,7 +91,11 @@
LcStRaw,
LcStTestLocked0,
LcStTestLocked1,
- LcStTestLocked2: begin
+ LcStTestLocked2,
+ LcStTestLocked3,
+ LcStTestLocked4,
+ LcStTestLocked5,
+ LcStTestLocked6: begin
lc_test_or_rma = On;
end
///////////////////////////////////////////////////////////////////
@@ -100,7 +104,11 @@
LcStTestUnlocked0,
LcStTestUnlocked1,
LcStTestUnlocked2,
- LcStTestUnlocked3: begin
+ LcStTestUnlocked3,
+ LcStTestUnlocked4,
+ LcStTestUnlocked5,
+ LcStTestUnlocked6,
+ LcStTestUnlocked7: begin
lc_test_or_rma = On;
lc_dft_en = On;
lc_nvm_debug_en = On;
@@ -343,12 +351,20 @@
PostTransSt} &&
!(lc_state_i inside {LcStRaw,
LcStTestUnlocked0,
- LcStTestLocked0,
LcStTestUnlocked1,
- LcStTestLocked1,
LcStTestUnlocked2,
- LcStTestLocked2,
LcStTestUnlocked3,
+ LcStTestUnlocked4,
+ LcStTestUnlocked5,
+ LcStTestUnlocked6,
+ LcStTestUnlocked7,
+ LcStTestLocked0,
+ LcStTestLocked1,
+ LcStTestLocked2,
+ LcStTestLocked3,
+ LcStTestLocked4,
+ LcStTestLocked5,
+ LcStTestLocked6,
LcStDev,
LcStProd,
LcStProdEnd,
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_state_decode.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl_state_decode.sv
index d8f8d6f..250a02f 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_state_decode.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_state_decode.sv
@@ -63,6 +63,14 @@
LcStTestUnlocked2: dec_lc_state_o = DecLcStTestUnlocked2;
LcStTestLocked2: dec_lc_state_o = DecLcStTestLocked2;
LcStTestUnlocked3: dec_lc_state_o = DecLcStTestUnlocked3;
+ LcStTestLocked3: dec_lc_state_o = DecLcStTestLocked3;
+ LcStTestUnlocked4: dec_lc_state_o = DecLcStTestUnlocked4;
+ LcStTestLocked4: dec_lc_state_o = DecLcStTestLocked4;
+ LcStTestUnlocked5: dec_lc_state_o = DecLcStTestUnlocked5;
+ LcStTestLocked5: dec_lc_state_o = DecLcStTestLocked5;
+ LcStTestUnlocked6: dec_lc_state_o = DecLcStTestUnlocked6;
+ LcStTestLocked6: dec_lc_state_o = DecLcStTestLocked6;
+ LcStTestUnlocked7: dec_lc_state_o = DecLcStTestUnlocked7;
LcStDev: dec_lc_state_o = DecLcStDev;
LcStProd: dec_lc_state_o = DecLcStProd;
LcStProdEnd: dec_lc_state_o = DecLcStProdEnd;
@@ -89,6 +97,14 @@
LcCnt14: dec_lc_cnt_o = 5'd14;
LcCnt15: dec_lc_cnt_o = 5'd15;
LcCnt16: dec_lc_cnt_o = 5'd16;
+ LcCnt17: dec_lc_cnt_o = 5'd17;
+ LcCnt18: dec_lc_cnt_o = 5'd18;
+ LcCnt19: dec_lc_cnt_o = 5'd19;
+ LcCnt20: dec_lc_cnt_o = 5'd20;
+ LcCnt21: dec_lc_cnt_o = 5'd21;
+ LcCnt22: dec_lc_cnt_o = 5'd22;
+ LcCnt23: dec_lc_cnt_o = 5'd23;
+ LcCnt24: dec_lc_cnt_o = 5'd24;
default: state_invalid_error_o = 1'b1;
endcase // lc_cnt_i
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
index cc4177e..983ff5d 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
@@ -18,14 +18,14 @@
parameter int LcValueWidth = 16;
- parameter int NumLcStateValues = 12;
+ parameter int NumLcStateValues = 20;
parameter int LcStateWidth = NumLcStateValues * LcValueWidth;
- parameter int NumLcStates = 13;
+ parameter int NumLcStates = 21;
parameter int DecLcStateWidth = vbits(NumLcStates);
- parameter int NumLcCountValues = 16;
+ parameter int NumLcCountValues = 24;
parameter int LcCountWidth = NumLcCountValues * LcValueWidth;
- parameter int NumLcCountStates = 17;
+ parameter int NumLcCountStates = 25;
parameter int DecLcCountWidth = vbits(NumLcCountStates);
// This state is not stored in OTP, but inferred from the locked
@@ -48,7 +48,7 @@
// - Minimum Hamming weight: 8
// - Maximum Hamming weight: 16
// - Minimum Hamming distance from any other value: 6
- // - Maximum Hamming distance from any other value: 18
+ // - Maximum Hamming distance from any other value: 20
//
// Hamming distance histogram:
//
@@ -58,21 +58,21 @@
// 3: --
// 4: --
// 5: --
- // 6: |||| (6.95%)
+ // 6: ||| (5.85%)
// 7: --
- // 8: |||||||||| (16.36%)
+ // 8: ||||||||||| (17.40%)
// 9: --
- // 10: ||||||||||||||||||| (29.22%)
+ // 10: |||||||||||||||||||| (29.60%)
// 11: --
- // 12: |||||||||||||||||||| (29.81%)
+ // 12: ||||||||||||||||||| (29.21%)
// 13: --
- // 14: |||||||| (13.18%)
+ // 14: ||||||||| (13.51%)
// 15: --
- // 16: || (4.16%)
+ // 16: || (4.02%)
// 17: --
- // 18: (0.32%)
+ // 18: (0.37%)
// 19: --
- // 20: --
+ // 20: (0.05%)
// 21: --
// 22: --
//
@@ -117,55 +117,103 @@
parameter logic [15:0] A11 = 16'b1011000100000111; // ECC: 6'b011001
parameter logic [15:0] B11 = 16'b1111110110000111; // ECC: 6'b011111
+ parameter logic [15:0] A12 = 16'b0011100000010000; // ECC: 6'b111001
+ parameter logic [15:0] B12 = 16'b1111100100110000; // ECC: 6'b111111
+
+ parameter logic [15:0] A13 = 16'b0011000010101011; // ECC: 6'b100110
+ parameter logic [15:0] B13 = 16'b1011010011111011; // ECC: 6'b111110
+
+ parameter logic [15:0] A14 = 16'b0011110100100000; // ECC: 6'b011000
+ parameter logic [15:0] B14 = 16'b0011111101101011; // ECC: 6'b011100
+
+ parameter logic [15:0] A15 = 16'b1010101100010010; // ECC: 6'b111000
+ parameter logic [15:0] B15 = 16'b1111111110011010; // ECC: 6'b111010
+
+ parameter logic [15:0] A16 = 16'b0100011010010100; // ECC: 6'b110110
+ parameter logic [15:0] B16 = 16'b0101111110010111; // ECC: 6'b111110
+
+ parameter logic [15:0] A17 = 16'b1011111110000101; // ECC: 6'b000000
+ parameter logic [15:0] B17 = 16'b1011111111010111; // ECC: 6'b000111
+
+ parameter logic [15:0] A18 = 16'b1110010000010111; // ECC: 6'b010100
+ parameter logic [15:0] B18 = 16'b1111110010111111; // ECC: 6'b010110
+
+ parameter logic [15:0] A19 = 16'b0100100101011010; // ECC: 6'b001000
+ parameter logic [15:0] B19 = 16'b1110100111111111; // ECC: 6'b001101
+
// The C/D values are used for the encoded LC transition counter.
- parameter logic [15:0] C0 = 16'b0011100000010000; // ECC: 6'b111001
- parameter logic [15:0] D0 = 16'b1111100100110000; // ECC: 6'b111111
+ parameter logic [15:0] C0 = 16'b0000110000011011; // ECC: 6'b110110
+ parameter logic [15:0] D0 = 16'b0011111000011111; // ECC: 6'b111111
- parameter logic [15:0] C1 = 16'b0011000010101011; // ECC: 6'b100110
- parameter logic [15:0] D1 = 16'b1011010011111011; // ECC: 6'b111110
+ parameter logic [15:0] C1 = 16'b0111001100010100; // ECC: 6'b011001
+ parameter logic [15:0] D1 = 16'b1111101101110110; // ECC: 6'b111001
- parameter logic [15:0] C2 = 16'b0011110100100000; // ECC: 6'b011000
- parameter logic [15:0] D2 = 16'b0011111101101011; // ECC: 6'b011100
+ parameter logic [15:0] C2 = 16'b0001101110100010; // ECC: 6'b100011
+ parameter logic [15:0] D2 = 16'b0011111111100011; // ECC: 6'b110111
- parameter logic [15:0] C3 = 16'b1010101100010010; // ECC: 6'b111000
- parameter logic [15:0] D3 = 16'b1111111110011010; // ECC: 6'b111010
+ parameter logic [15:0] C3 = 16'b0000110101000010; // ECC: 6'b111101
+ parameter logic [15:0] D3 = 16'b1100110111010110; // ECC: 6'b111111
- parameter logic [15:0] C4 = 16'b0100011010010100; // ECC: 6'b110110
- parameter logic [15:0] D4 = 16'b0101111110010111; // ECC: 6'b111110
+ parameter logic [15:0] C4 = 16'b0001111111010001; // ECC: 6'b000010
+ parameter logic [15:0] D4 = 16'b0001111111111001; // ECC: 6'b101111
- parameter logic [15:0] C5 = 16'b1011111110000101; // ECC: 6'b000000
- parameter logic [15:0] D5 = 16'b1011111111010111; // ECC: 6'b000111
+ parameter logic [15:0] C5 = 16'b0010010000110000; // ECC: 6'b111111
+ parameter logic [15:0] D5 = 16'b0111011100110101; // ECC: 6'b111111
- parameter logic [15:0] C6 = 16'b1110010000010111; // ECC: 6'b010100
- parameter logic [15:0] D6 = 16'b1111110010111111; // ECC: 6'b010110
+ parameter logic [15:0] C6 = 16'b0010111010001111; // ECC: 6'b001000
+ parameter logic [15:0] D6 = 16'b1011111010111111; // ECC: 6'b101100
- parameter logic [15:0] C7 = 16'b0100100101011010; // ECC: 6'b001000
- parameter logic [15:0] D7 = 16'b1110100111111111; // ECC: 6'b001101
+ parameter logic [15:0] C7 = 16'b0100010000111101; // ECC: 6'b011010
+ parameter logic [15:0] D7 = 16'b0101110011111101; // ECC: 6'b111110
- parameter logic [15:0] C8 = 16'b0000110000011011; // ECC: 6'b110110
- parameter logic [15:0] D8 = 16'b0011111000011111; // ECC: 6'b111111
+ parameter logic [15:0] C8 = 16'b1110000000101100; // ECC: 6'b111001
+ parameter logic [15:0] D8 = 16'b1110010110111101; // ECC: 6'b111101
- parameter logic [15:0] C9 = 16'b0111001100010100; // ECC: 6'b011001
- parameter logic [15:0] D9 = 16'b1111101101110110; // ECC: 6'b111001
+ parameter logic [15:0] C9 = 16'b0010011100101110; // ECC: 6'b010001
+ parameter logic [15:0] D9 = 16'b1011011110101111; // ECC: 6'b111001
- parameter logic [15:0] C10 = 16'b0001101110100010; // ECC: 6'b100011
- parameter logic [15:0] D10 = 16'b0011111111100011; // ECC: 6'b110111
+ parameter logic [15:0] C10 = 16'b0010110011101110; // ECC: 6'b000100
+ parameter logic [15:0] D10 = 16'b1010111011111110; // ECC: 6'b110110
- parameter logic [15:0] C11 = 16'b0000110101000010; // ECC: 6'b111101
- parameter logic [15:0] D11 = 16'b1100110111010110; // ECC: 6'b111111
+ parameter logic [15:0] C11 = 16'b1100000100010011; // ECC: 6'b000011
+ parameter logic [15:0] D11 = 16'b1110000110011011; // ECC: 6'b111011
- parameter logic [15:0] C12 = 16'b0001111111010001; // ECC: 6'b000010
- parameter logic [15:0] D12 = 16'b0001111111111001; // ECC: 6'b101111
+ parameter logic [15:0] C12 = 16'b1000110110101101; // ECC: 6'b000010
+ parameter logic [15:0] D12 = 16'b1001111110111101; // ECC: 6'b010111
- parameter logic [15:0] C13 = 16'b0010010000110000; // ECC: 6'b111111
- parameter logic [15:0] D13 = 16'b0111011100110101; // ECC: 6'b111111
+ parameter logic [15:0] C13 = 16'b0000011111001011; // ECC: 6'b001010
+ parameter logic [15:0] D13 = 16'b1001111111001111; // ECC: 6'b111010
- parameter logic [15:0] C14 = 16'b0010111010001111; // ECC: 6'b001000
- parameter logic [15:0] D14 = 16'b1011111010111111; // ECC: 6'b101100
+ parameter logic [15:0] C14 = 16'b1101001001001010; // ECC: 6'b110100
+ parameter logic [15:0] D14 = 16'b1101001011101111; // ECC: 6'b110111
- parameter logic [15:0] C15 = 16'b0100010000111101; // ECC: 6'b011010
- parameter logic [15:0] D15 = 16'b0101110011111101; // ECC: 6'b111110
+ parameter logic [15:0] C15 = 16'b0001100011110101; // ECC: 6'b100010
+ parameter logic [15:0] D15 = 16'b0011110011110111; // ECC: 6'b111011
+
+ parameter logic [15:0] C16 = 16'b1000001110100011; // ECC: 6'b010110
+ parameter logic [15:0] D16 = 16'b1100111111101111; // ECC: 6'b010110
+
+ parameter logic [15:0] C17 = 16'b0100110101010001; // ECC: 6'b100110
+ parameter logic [15:0] D17 = 16'b1111110101010011; // ECC: 6'b110111
+
+ parameter logic [15:0] C18 = 16'b1010010000101010; // ECC: 6'b100001
+ parameter logic [15:0] D18 = 16'b1010011111101110; // ECC: 6'b100011
+
+ parameter logic [15:0] C19 = 16'b0001111001110000; // ECC: 6'b101010
+ parameter logic [15:0] D19 = 16'b0111111111110011; // ECC: 6'b101010
+
+ parameter logic [15:0] C20 = 16'b0010101001111110; // ECC: 6'b100000
+ parameter logic [15:0] D20 = 16'b0110101111111110; // ECC: 6'b110101
+
+ parameter logic [15:0] C21 = 16'b1001000011110000; // ECC: 6'b000011
+ parameter logic [15:0] D21 = 16'b1001001011111101; // ECC: 6'b001111
+
+ parameter logic [15:0] C22 = 16'b0101101010000001; // ECC: 6'b110110
+ parameter logic [15:0] D22 = 16'b1111101010010101; // ECC: 6'b111111
+
+ parameter logic [15:0] C23 = 16'b1101000100101110; // ECC: 6'b110000
+ parameter logic [15:0] D23 = 16'b1111100110101110; // ECC: 6'b111110
parameter logic [15:0] ZRO = 16'h0;
@@ -175,59 +223,83 @@
////////////////////////
typedef enum logic [LcStateWidth-1:0] {
- LcStRaw = {ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO},
- LcStTestUnlocked0 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, B0},
- LcStTestLocked0 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, B1, B0},
- LcStTestUnlocked1 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, B2, B1, B0},
- LcStTestLocked1 = {A11, A10, A9, A8, A7, A6, A5, A4, B3, B2, B1, B0},
- LcStTestUnlocked2 = {A11, A10, A9, A8, A7, A6, A5, B4, B3, B2, B1, B0},
- LcStTestLocked2 = {A11, A10, A9, A8, A7, A6, B5, B4, B3, B2, B1, B0},
- LcStTestUnlocked3 = {A11, A10, A9, A8, A7, B6, B5, B4, B3, B2, B1, B0},
- LcStDev = {A11, A10, A9, A8, B7, B6, B5, B4, B3, B2, B1, B0},
- LcStProd = {A11, A10, A9, B8, A7, B6, B5, B4, B3, B2, B1, B0},
- LcStProdEnd = {A11, A10, B9, A8, A7, B6, B5, B4, B3, B2, B1, B0},
- LcStRma = {B11, B10, A9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
- LcStScrap = {B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}
+ LcStRaw = {ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO},
+ LcStTestUnlocked0 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, B0},
+ LcStTestLocked0 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, B1, B0},
+ LcStTestUnlocked1 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, B2, B1, B0},
+ LcStTestLocked1 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, B3, B2, B1, B0},
+ LcStTestUnlocked2 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, B4, B3, B2, B1, B0},
+ LcStTestLocked2 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, B5, B4, B3, B2, B1, B0},
+ LcStTestUnlocked3 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStTestLocked3 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStTestUnlocked4 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStTestLocked4 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStTestUnlocked5 = {A19, A18, A17, A16, A15, A14, A13, A12, A11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStTestLocked5 = {A19, A18, A17, A16, A15, A14, A13, A12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStTestUnlocked6 = {A19, A18, A17, A16, A15, A14, A13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStTestLocked6 = {A19, A18, A17, A16, A15, A14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStTestUnlocked7 = {A19, A18, A17, A16, A15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStDev = {A19, A18, A17, A16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStProd = {A19, A18, A17, B16, A15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStProdEnd = {A19, A18, B17, A16, A15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStRma = {B19, B18, A17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStScrap = {B19, B18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}
} lc_state_e;
typedef enum logic [LcCountWidth-1:0] {
- LcCnt0 = {ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO},
- LcCnt1 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, D0},
- LcCnt2 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, D1, D0},
- LcCnt3 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, D2, D1, D0},
- LcCnt4 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, D3, D2, D1, D0},
- LcCnt5 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, D4, D3, D2, D1, D0},
- LcCnt6 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, D5, D4, D3, D2, D1, D0},
- LcCnt7 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, D6, D5, D4, D3, D2, D1, D0},
- LcCnt8 = {C15, C14, C13, C12, C11, C10, C9, C8, D7, D6, D5, D4, D3, D2, D1, D0},
- LcCnt9 = {C15, C14, C13, C12, C11, C10, C9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
- LcCnt10 = {C15, C14, C13, C12, C11, C10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
- LcCnt11 = {C15, C14, C13, C12, C11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
- LcCnt12 = {C15, C14, C13, C12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
- LcCnt13 = {C15, C14, C13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
- LcCnt14 = {C15, C14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
- LcCnt15 = {C15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
- LcCnt16 = {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}
+ LcCnt0 = {ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO, ZRO},
+ LcCnt1 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, D0},
+ LcCnt2 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, D1, D0},
+ LcCnt3 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, D2, D1, D0},
+ LcCnt4 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, D3, D2, D1, D0},
+ LcCnt5 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, D4, D3, D2, D1, D0},
+ LcCnt6 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, D5, D4, D3, D2, D1, D0},
+ LcCnt7 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt8 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt9 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt10 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt11 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, C11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt12 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt13 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt14 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt15 = {C23, C22, C21, C20, C19, C18, C17, C16, C15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt16 = {C23, C22, C21, C20, C19, C18, C17, C16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt17 = {C23, C22, C21, C20, C19, C18, C17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt18 = {C23, C22, C21, C20, C19, C18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt19 = {C23, C22, C21, C20, C19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt20 = {C23, C22, C21, C20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt21 = {C23, C22, C21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt22 = {C23, C22, D21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt23 = {C23, D22, D21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt24 = {D23, D22, D21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}
} lc_cnt_e;
// Decoded life cycle state, used to interface with CSRs and TAP.
typedef enum logic [DecLcStateWidth-1:0] {
- DecLcStRaw,
- DecLcStTestUnlocked0,
- DecLcStTestLocked0,
- DecLcStTestUnlocked1,
- DecLcStTestLocked1,
- DecLcStTestUnlocked2,
- DecLcStTestLocked2,
- DecLcStTestUnlocked3,
- DecLcStDev,
- DecLcStProd,
- DecLcStProdEnd,
- DecLcStRma,
- DecLcStScrap,
- DecLcStPostTrans,
- DecLcStEscalate,
- DecLcStInvalid
+ DecLcStRaw = 0,
+ DecLcStTestUnlocked0 = 1,
+ DecLcStTestLocked0 = 2,
+ DecLcStTestUnlocked1 = 3,
+ DecLcStTestLocked1 = 4,
+ DecLcStTestUnlocked2 = 5,
+ DecLcStTestLocked2 = 6,
+ DecLcStTestUnlocked3 = 7,
+ DecLcStTestLocked3 = 8,
+ DecLcStTestUnlocked4 = 9,
+ DecLcStTestLocked4 = 10,
+ DecLcStTestUnlocked5 = 11,
+ DecLcStTestLocked5 = 12,
+ DecLcStTestUnlocked6 = 13,
+ DecLcStTestLocked6 = 14,
+ DecLcStTestUnlocked7 = 15,
+ DecLcStDev = 16,
+ DecLcStProd = 17,
+ DecLcStProdEnd = 18,
+ DecLcStRma = 19,
+ DecLcStScrap = 20,
+ DecLcStPostTrans = 21,
+ DecLcStEscalate = 22,
+ DecLcStInvalid = 23
} dec_lc_state_e;
typedef enum logic [DecLcIdStateWidth-1:0] {
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv.tpl b/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv.tpl
index 439ead5..581928b 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv.tpl
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv.tpl
@@ -147,11 +147,11 @@
// Decoded life cycle state, used to interface with CSRs and TAP.
typedef enum logic [DecLcStateWidth-1:0] {
% for state in lc_st_enc.config['lc_state'].keys():
- DecLcSt${_to_pascal_case(state)},
+ DecLcSt${_to_pascal_case(state)} = ${loop.index},
% endfor
- DecLcStPostTrans,
- DecLcStEscalate,
- DecLcStInvalid
+ DecLcStPostTrans = ${len(lc_st_enc.config['lc_state']) + 0},
+ DecLcStEscalate = ${len(lc_st_enc.config['lc_state']) + 1},
+ DecLcStInvalid = ${len(lc_st_enc.config['lc_state']) + 2}
} dec_lc_state_e;
typedef enum logic [DecLcIdStateWidth-1:0] {
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_state_transition.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl_state_transition.sv
index ad480c4..bdbbbe2 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_state_transition.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_state_transition.sv
@@ -67,7 +67,15 @@
LcCnt13: next_lc_cnt_o = LcCnt14;
LcCnt14: next_lc_cnt_o = LcCnt15;
LcCnt15: next_lc_cnt_o = LcCnt16;
- LcCnt16: trans_cnt_oflw_error_o = 1'b1;
+ LcCnt16: next_lc_cnt_o = LcCnt17;
+ LcCnt17: next_lc_cnt_o = LcCnt18;
+ LcCnt18: next_lc_cnt_o = LcCnt19;
+ LcCnt19: next_lc_cnt_o = LcCnt20;
+ LcCnt20: next_lc_cnt_o = LcCnt21;
+ LcCnt21: next_lc_cnt_o = LcCnt22;
+ LcCnt22: next_lc_cnt_o = LcCnt23;
+ LcCnt23: next_lc_cnt_o = LcCnt24;
+ LcCnt24: trans_cnt_oflw_error_o = 1'b1;
default: trans_cnt_oflw_error_o = 1'b1;
endcase // lc_cnt_i
@@ -103,6 +111,14 @@
DecLcStTestUnlocked2: next_lc_state_o = LcStTestUnlocked2;
DecLcStTestLocked2: next_lc_state_o = LcStTestLocked2;
DecLcStTestUnlocked3: next_lc_state_o = LcStTestUnlocked3;
+ DecLcStTestLocked3: next_lc_state_o = LcStTestLocked3;
+ DecLcStTestUnlocked4: next_lc_state_o = LcStTestUnlocked4;
+ DecLcStTestLocked4: next_lc_state_o = LcStTestLocked4;
+ DecLcStTestUnlocked5: next_lc_state_o = LcStTestUnlocked5;
+ DecLcStTestLocked5: next_lc_state_o = LcStTestLocked5;
+ DecLcStTestUnlocked6: next_lc_state_o = LcStTestUnlocked6;
+ DecLcStTestLocked6: next_lc_state_o = LcStTestLocked6;
+ DecLcStTestUnlocked7: next_lc_state_o = LcStTestUnlocked7;
DecLcStDev: next_lc_state_o = LcStDev;
DecLcStProd: next_lc_state_o = LcStProd;
DecLcStProdEnd: next_lc_state_o = LcStProdEnd;
