[aes] Simplify clearing functionality
This commit simplifies the clearing functionality by reducing the number of
trigger bits from 4 to 2:
- One bit for clearing key, IV, and input data registers, and
- one bit for clearing output data registers.
This way, software can already trigger the clearing of the key, IV, and
input data registers while the last block operation is still running. After
the operation is finished, the output registers can be read in parallel to
the clearing operation. Having more, separate clearing triggers is not
useful but makes design verification a lot harder as it adds many
difficult corner cases.
This resolves lowRISC/OpenTitan#4653.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/ip/aes/data/aes.hjson b/hw/ip/aes/data/aes.hjson
index 127d01d..08ded2f 100644
--- a/hw/ip/aes/data/aes.hjson
+++ b/hw/ip/aes/data/aes.hjson
@@ -416,7 +416,7 @@
While executing any of the triggered operations, the AES unit will set the IDLE bit in the Status Register to zero.
The processor must check the Status Register before triggering further actions.
For example, writes to Initial Key and IV Registers are ignored while the AES unit is busy.
- Writes to the Input Data Registers are not ignored but the data will be cleared if a DATA_IN_CLEAR operation is pending.
+ Writes to the Input Data Registers are not ignored but the data will be cleared if a KEY_IV_DATA_IN_CLEAR operation is pending.
'''
swaccess: "wo",
hwaccess: "hrw",
@@ -437,39 +437,22 @@
tags: ["excl:CsrNonInitTests:CsrExclWriteCheck"]
}
{ bits: "1",
- name: "KEY_CLEAR",
+ name: "KEY_IV_DATA_IN_CLEAR",
resval: "1"
desc: '''
- Keep current values in Initial Key, internal Full Key and Decryption Key registers (0)
- or clear those registers with pseudo-random data (1).
+ Keep current values in Initial Key, internal Full Key and Decryption Key registers, IV registers and Input Data registers (0) or clear all those registers with pseudo-random data (1).
'''
tags: ["excl:CsrAllTests:CsrExclCheck"]
}
{ bits: "2",
- name: "IV_CLEAR",
+ name: "DATA_OUT_CLEAR",
resval: "1"
desc: '''
- Keep current values in IV registers (0) or clear those registers with pseudo-random data (1).
+ Keep current values in Output Data registers (0) or clear those registers with pseudo-random data (1).
'''
tags: ["excl:CsrAllTests:CsrExclCheck"]
}
{ bits: "3",
- name: "DATA_IN_CLEAR",
- resval: "1"
- desc: '''
- Keep current values in input registers (0) or clear those registers with pseudo-random data (1).
- '''
- tags: ["excl:CsrAllTests:CsrExclCheck"]
- }
- { bits: "4",
- name: "DATA_OUT_CLEAR",
- resval: "1"
- desc: '''
- Keep current values in output registers (0) or clear those registers with pseudo-random data (1).
- '''
- tags: ["excl:CsrAllTests:CsrExclCheck"]
- }
- { bits: "5",
name: "PRNG_RESEED",
resval: "1"
desc: '''
diff --git a/hw/ip/aes/doc/_index.md b/hw/ip/aes/doc/_index.md
index aaa4348..e531b32 100644
--- a/hw/ip/aes/doc/_index.md
+++ b/hw/ip/aes/doc/_index.md
@@ -447,7 +447,7 @@
After finishing operation, software must:
1. Disable the AES unit to no longer automatically start encryption/decryption by setting the MANUAL_OPERATION bit in {{< regref "CTRL_SHADOWED" >}} to `1`.
-1. Clear all key registers with pseudo-random data, IV registers as well as the Input Data and the Output Data registers by setting the KEY_CLEAR, IV_CLEAR, DATA_IN_CLEAR and DATA_OUT_CLEAR bits in {{< regref "TRIGGER" >}} to `1`.
+1. Clear all key registers, IV registers as well as the Input Data and the Output Data registers with pseudo-random data by setting the KEY_IV_DATA_IN_CLEAR and DATA_OUT_CLEAR bits in {{< regref "TRIGGER" >}} to `1`.
The code snippet below shows how to perform this task.
@@ -457,11 +457,9 @@
REG32(AES_CTRL_SHADOWED(0)) = aes_ctrl_val;
REG32(AES_CTRL_SHADOWED(0)) = aes_ctrl_val;
- // Clear all key register, Input Data and Output Data registers
+ // Clear all key, IV, Input Data and Output Data registers.
REG32(AES_TRIGGER(0)) =
- (0x1 << AES_TRIGGER_KEY_CLEAR) |
- (0x1 << AES_TRIGGER_IV_CLEAR) |
- (0x1 << AES_TRIGGER_DATA_IN_CLEAR) |
+ (0x1 << AES_TRIGGER_KEY_IV_DATA_IN_CLEAR) |
(0x1 << AES_TRIGGER_DATA_OUT_CLEAR);
```
diff --git a/hw/ip/aes/dv/env/aes_scoreboard.sv b/hw/ip/aes/dv/env/aes_scoreboard.sv
index fdb2c99..cdebfee 100644
--- a/hw/ip/aes/dv/env/aes_scoreboard.sv
+++ b/hw/ip/aes/dv/env/aes_scoreboard.sv
@@ -152,9 +152,11 @@
if (get_field_val(ral.trigger.start, item.a_data)) begin
ok_to_fwd = 1;
end
- // clear key
- if (get_field_val(ral.trigger.key_clear, item.a_data)) begin
+ // clear key, IV, data_in
+ if (get_field_val(ral.trigger.key_iv_data_in_clear, item.a_data)) begin
void'(input_item.key_clean(0, 1));
+ void'(input_item.iv_clean(0, 1));
+ input_item.clean_data_in();
// if in the middle of a message
// this is seen as the beginning of a new message
if (!input_item.start_item) begin
@@ -162,21 +164,7 @@
`uvm_info(`gfn, $sformatf("splitting message"), UVM_MEDIUM)
end
`uvm_info(`gfn, $sformatf("\n\t ----clearing KEY"), UVM_MEDIUM)
- end
- // clear IV
- if (get_field_val(ral.trigger.iv_clear, item.a_data)) begin
- void'(input_item.iv_clean(0, 1));
- // if in the middle of a message
- // this is seen as the beginning of a new message
- if (!input_item.start_item) begin
- input_item.start_item = 1;
- `uvm_info(`gfn, $sformatf("splitting message"), UVM_MEDIUM)
- end
`uvm_info(`gfn, $sformatf("\n\t ----| clearing IV"), UVM_MEDIUM)
- end
- // clear data_in
- if (get_field_val(ral.trigger.data_in_clear, item.a_data)) begin
- input_item.clean_data_in();
`uvm_info(`gfn, $sformatf("\n\t ----| clearing DATA_IN"), UVM_MEDIUM)
end
// clear data out
diff --git a/hw/ip/aes/dv/env/seq_lib/aes_base_vseq.sv b/hw/ip/aes/dv/env/seq_lib/aes_base_vseq.sv
index d360099..52eb525 100644
--- a/hw/ip/aes/dv/env/seq_lib/aes_base_vseq.sv
+++ b/hw/ip/aes/dv/env/seq_lib/aes_base_vseq.sv
@@ -71,9 +71,7 @@
`uvm_info(`gfn, $sformatf("%s",txt), UVM_MEDIUM)
ral.trigger.set(0);
- ral.trigger.key_clear.set(clr_vector.key);
- ral.trigger.iv_clear.set(clr_vector.iv);
- ral.trigger.data_in_clear.set(clr_vector.data_in);
+ ral.trigger.key_iv_data_in_clear.set(|clr_vector[2:0]);
ral.trigger.data_out_clear.set(clr_vector.data_out);
csr_update(ral.trigger);
endtask // clear_registers
diff --git a/hw/ip/aes/rtl/aes_control.sv b/hw/ip/aes/rtl/aes_control.sv
index 799f617..b946565 100644
--- a/hw/ip/aes/rtl/aes_control.sv
+++ b/hw/ip/aes/rtl/aes_control.sv
@@ -24,9 +24,7 @@
input aes_pkg::ciph_op_e cipher_op_i,
input logic manual_operation_i,
input logic start_i,
- input logic key_clear_i,
- input logic iv_clear_i,
- input logic data_in_clear_i,
+ input logic key_iv_data_in_clear_i,
input logic data_out_clear_i,
input logic prng_reseed_i,
input logic alert_fatal_i,
@@ -85,12 +83,8 @@
// Trigger register
output logic start_o,
output logic start_we_o,
- output logic key_clear_o,
- output logic key_clear_we_o,
- output logic iv_clear_o,
- output logic iv_clear_we_o,
- output logic data_in_clear_o,
- output logic data_in_clear_we_o,
+ output logic key_iv_data_in_clear_o,
+ output logic key_iv_data_in_clear_we_o,
output logic data_out_clear_o,
output logic data_out_clear_we_o,
output logic prng_reseed_o,
@@ -273,12 +267,10 @@
prng_reseed_req_o = 1'b0;
// Trigger register control
- start_we_o = 1'b0;
- key_clear_we_o = 1'b0;
- iv_clear_we_o = 1'b0;
- data_in_clear_we_o = 1'b0;
- data_out_clear_we_o = 1'b0;
- prng_reseed_we_o = 1'b0;
+ start_we_o = 1'b0;
+ key_iv_data_in_clear_we_o = 1'b0;
+ data_out_clear_we_o = 1'b0;
+ prng_reseed_we_o = 1'b0;
// Status register
idle_o = 1'b0;
@@ -305,8 +297,8 @@
unique case (aes_ctrl_cs)
IDLE: begin
- idle_o = (start || key_clear_i || iv_clear_i ||
- data_in_clear_i || data_out_clear_i || prng_reseed_i) ? 1'b0 : 1'b1;
+ idle_o = (start || key_iv_data_in_clear_i || data_out_clear_i ||
+ prng_reseed_i) ? 1'b0 : 1'b1;
idle_we_o = 1'b1;
if (idle_o) begin
@@ -331,7 +323,7 @@
prng_reseed_we_o = 1'b1;
end
- end else if (key_clear_i || data_out_clear_i || iv_clear_i || data_in_clear_i) begin
+ end else if (key_iv_data_in_clear_i || data_out_clear_i) begin
// To clear registers, we must first request fresh pseudo-random data.
aes_ctrl_ns = UPDATE_PRNG;
@@ -414,11 +406,11 @@
if (cipher_crypt_i) begin
aes_ctrl_ns = FINISH;
- end else if (key_clear_i || data_out_clear_i) begin
+ end else begin // (key_iv_data_in_clear_i || data_out_clear_i)
// To clear the output data registers, we re-use the muxing resources of the cipher
// core. To clear all key material, some key registers inside the cipher core need to
// be cleared.
- cipher_key_clear_o = key_clear_i;
+ cipher_key_clear_o = key_iv_data_in_clear_i;
cipher_data_out_clear_o = data_out_clear_i;
// We have work for the cipher core, perform handshake.
@@ -426,12 +418,8 @@
if (cipher_in_ready_i) begin
aes_ctrl_ns = CLEAR;
end
- end else begin // (iv_clear_i || data_in_clear_i)
- // To clear the IV or input data registers, no handshake with the cipher core is
- // needed.
- aes_ctrl_ns = CLEAR;
- end
- end
+ end // cipher_crypt_i
+ end // prng_data_ack_i
end
FINISH: begin
@@ -493,43 +481,43 @@
end
CLEAR: begin
- // The IV and input data registers can be cleared independently of the cipher core.
- if (iv_clear_i) begin
- iv_sel_o = IV_CLEAR;
- iv_we_o = 8'hFF;
- iv_clear_we_o = 1'b1;
- iv_clear = 1'b1;
- end
- if (data_in_clear_i) begin
+ // Initial Key, IV and input data registers can be cleared right away.
+ if (key_iv_data_in_clear_i) begin
+ // Initial Key
+ key_init_sel_o = KEY_INIT_CLEAR;
+ key_init_we_o = '{8'hFF, 8'hFF};
+ key_init_clear = 1'b1;
+
+ // IV
+ iv_sel_o = IV_CLEAR;
+ iv_we_o = 8'hFF;
+ iv_clear = 1'b1;
+
+ // Input data
data_in_we_o = 1'b1;
- data_in_clear_we_o = 1'b1;
data_in_prev_sel_o = DIP_CLEAR;
data_in_prev_we_o = 1'b1;
end
- // To clear the output data registers, we re-use the muxing resources of the cipher core.
- // To clear all key material, some key registers inside the cipher core need to be cleared.
- if (cipher_key_clear_i || cipher_data_out_clear_i) begin
+ // Perform handshake with cipher core.
+ cipher_out_ready_o = 1'b1;
+ if (cipher_out_valid_i) begin
- // Perform handshake.
- cipher_out_ready_o = 1'b1;
- if (cipher_out_valid_i) begin
-
- if (cipher_key_clear_i) begin
- key_init_sel_o = KEY_INIT_CLEAR;
- key_init_we_o = '{8'hFF, 8'hFF};
- key_clear_we_o = 1'b1;
- key_init_clear = 1'b1;
- end
-
- if (cipher_data_out_clear_i) begin
- data_out_we_o = 1'b1;
- data_out_clear_we_o = 1'b1;
- end
- aes_ctrl_ns = IDLE;
+ // Full Key and Decryption Key registers are cleared by the cipher core.
+ // key_iv_data_in_clear_i is acknowledged by the cipher core with cipher_key_clear_i.
+ if (cipher_key_clear_i) begin
+ // Clear the trigger bit.
+ key_iv_data_in_clear_we_o = 1'b1;
end
- end else begin
+ // To clear the output data registers, we re-use the muxing resources of the cipher core.
+ // data_out_clear_i is acknowledged by the cipher core with cipher_data_out_clear_i.
+ if (cipher_data_out_clear_i) begin
+ // Clear output data and the trigger bit.
+ data_out_we_o = 1'b1;
+ data_out_clear_we_o = 1'b1;
+ end
+
aes_ctrl_ns = IDLE;
end
end
@@ -661,12 +649,10 @@
end
// Trigger register, the control only ever clears these
- assign start_o = 1'b0;
- assign key_clear_o = 1'b0;
- assign iv_clear_o = 1'b0;
- assign data_in_clear_o = 1'b0;
- assign data_out_clear_o = 1'b0;
- assign prng_reseed_o = 1'b0;
+ assign start_o = 1'b0;
+ assign key_iv_data_in_clear_o = 1'b0;
+ assign data_out_clear_o = 1'b0;
+ assign prng_reseed_o = 1'b0;
// Selectors must be known/valid
`ASSERT(AesModeValid, !ctrl_err_storage_i |-> mode_i inside {
diff --git a/hw/ip/aes/rtl/aes_core.sv b/hw/ip/aes/rtl/aes_core.sv
index 9711eef..3f9443e 100644
--- a/hw/ip/aes/rtl/aes_core.sv
+++ b/hw/ip/aes/rtl/aes_core.sv
@@ -486,87 +486,81 @@
aes_control #(
.SecStartTriggerDelay ( SecStartTriggerDelay )
) u_aes_control (
- .clk_i ( clk_i ),
- .rst_ni ( rst_ni ),
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
- .ctrl_qe_i ( ctrl_qe ),
- .ctrl_we_o ( ctrl_we ),
- .ctrl_err_storage_i ( ctrl_err_storage ),
- .op_i ( aes_op_q ),
- .mode_i ( aes_mode_q ),
- .cipher_op_i ( cipher_op ),
- .manual_operation_i ( manual_operation_q ),
- .start_i ( reg2hw.trigger.start.q ),
- .key_clear_i ( reg2hw.trigger.key_clear.q ),
- .iv_clear_i ( reg2hw.trigger.iv_clear.q ),
- .data_in_clear_i ( reg2hw.trigger.data_in_clear.q ),
- .data_out_clear_i ( reg2hw.trigger.data_out_clear.q ),
- .prng_reseed_i ( reg2hw.trigger.prng_reseed.q ),
- .alert_fatal_i ( alert_fatal_o ),
- .alert_o ( ctrl_alert ),
+ .ctrl_qe_i ( ctrl_qe ),
+ .ctrl_we_o ( ctrl_we ),
+ .ctrl_err_storage_i ( ctrl_err_storage ),
+ .op_i ( aes_op_q ),
+ .mode_i ( aes_mode_q ),
+ .cipher_op_i ( cipher_op ),
+ .manual_operation_i ( manual_operation_q ),
+ .start_i ( reg2hw.trigger.start.q ),
+ .key_iv_data_in_clear_i ( reg2hw.trigger.key_iv_data_in_clear.q ),
+ .data_out_clear_i ( reg2hw.trigger.data_out_clear.q ),
+ .prng_reseed_i ( reg2hw.trigger.prng_reseed.q ),
+ .alert_fatal_i ( alert_fatal_o ),
+ .alert_o ( ctrl_alert ),
- .key_init_qe_i ( key_init_qe ),
- .iv_qe_i ( iv_qe ),
- .data_in_qe_i ( data_in_qe ),
- .data_out_re_i ( data_out_re ),
- .data_in_we_o ( data_in_we ),
- .data_out_we_o ( data_out_we ),
+ .key_init_qe_i ( key_init_qe ),
+ .iv_qe_i ( iv_qe ),
+ .data_in_qe_i ( data_in_qe ),
+ .data_out_re_i ( data_out_re ),
+ .data_in_we_o ( data_in_we ),
+ .data_out_we_o ( data_out_we ),
- .data_in_prev_sel_o ( data_in_prev_sel ),
- .data_in_prev_we_o ( data_in_prev_we ),
+ .data_in_prev_sel_o ( data_in_prev_sel ),
+ .data_in_prev_we_o ( data_in_prev_we ),
- .state_in_sel_o ( state_in_sel ),
- .add_state_in_sel_o ( add_state_in_sel ),
- .add_state_out_sel_o ( add_state_out_sel ),
+ .state_in_sel_o ( state_in_sel ),
+ .add_state_in_sel_o ( add_state_in_sel ),
+ .add_state_out_sel_o ( add_state_out_sel ),
- .ctr_incr_o ( ctr_incr ),
- .ctr_ready_i ( ctr_ready ),
- .ctr_we_i ( ctr_we ),
+ .ctr_incr_o ( ctr_incr ),
+ .ctr_ready_i ( ctr_ready ),
+ .ctr_we_i ( ctr_we ),
- .cipher_in_valid_o ( cipher_in_valid ),
- .cipher_in_ready_i ( cipher_in_ready ),
- .cipher_out_valid_i ( cipher_out_valid ),
- .cipher_out_ready_o ( cipher_out_ready ),
- .cipher_crypt_o ( cipher_crypt ),
- .cipher_crypt_i ( cipher_crypt_busy ),
- .cipher_dec_key_gen_o ( cipher_dec_key_gen ),
- .cipher_dec_key_gen_i ( cipher_dec_key_gen_busy ),
- .cipher_key_clear_o ( cipher_key_clear ),
- .cipher_key_clear_i ( cipher_key_clear_busy ),
- .cipher_data_out_clear_o ( cipher_data_out_clear ),
- .cipher_data_out_clear_i ( cipher_data_out_clear_busy ),
+ .cipher_in_valid_o ( cipher_in_valid ),
+ .cipher_in_ready_i ( cipher_in_ready ),
+ .cipher_out_valid_i ( cipher_out_valid ),
+ .cipher_out_ready_o ( cipher_out_ready ),
+ .cipher_crypt_o ( cipher_crypt ),
+ .cipher_crypt_i ( cipher_crypt_busy ),
+ .cipher_dec_key_gen_o ( cipher_dec_key_gen ),
+ .cipher_dec_key_gen_i ( cipher_dec_key_gen_busy ),
+ .cipher_key_clear_o ( cipher_key_clear ),
+ .cipher_key_clear_i ( cipher_key_clear_busy ),
+ .cipher_data_out_clear_o ( cipher_data_out_clear ),
+ .cipher_data_out_clear_i ( cipher_data_out_clear_busy ),
- .key_init_sel_o ( key_init_sel ),
- .key_init_we_o ( key_init_we ),
- .iv_sel_o ( iv_sel ),
- .iv_we_o ( iv_we ),
+ .key_init_sel_o ( key_init_sel ),
+ .key_init_we_o ( key_init_we ),
+ .iv_sel_o ( iv_sel ),
+ .iv_we_o ( iv_we ),
- .prng_data_req_o ( prd_clearing_upd_req ),
- .prng_data_ack_i ( prd_clearing_upd_ack ),
- .prng_reseed_req_o ( prd_clearing_rsd_req ),
- .prng_reseed_ack_i ( prd_clearing_rsd_ack ),
+ .prng_data_req_o ( prd_clearing_upd_req ),
+ .prng_data_ack_i ( prd_clearing_upd_ack ),
+ .prng_reseed_req_o ( prd_clearing_rsd_req ),
+ .prng_reseed_ack_i ( prd_clearing_rsd_ack ),
- .start_o ( hw2reg.trigger.start.d ),
- .start_we_o ( hw2reg.trigger.start.de ),
- .key_clear_o ( hw2reg.trigger.key_clear.d ),
- .key_clear_we_o ( hw2reg.trigger.key_clear.de ),
- .iv_clear_o ( hw2reg.trigger.iv_clear.d ),
- .iv_clear_we_o ( hw2reg.trigger.iv_clear.de ),
- .data_in_clear_o ( hw2reg.trigger.data_in_clear.d ),
- .data_in_clear_we_o ( hw2reg.trigger.data_in_clear.de ),
- .data_out_clear_o ( hw2reg.trigger.data_out_clear.d ),
- .data_out_clear_we_o ( hw2reg.trigger.data_out_clear.de ),
- .prng_reseed_o ( hw2reg.trigger.prng_reseed.d ),
- .prng_reseed_we_o ( hw2reg.trigger.prng_reseed.de ),
+ .start_o ( hw2reg.trigger.start.d ),
+ .start_we_o ( hw2reg.trigger.start.de ),
+ .key_iv_data_in_clear_o ( hw2reg.trigger.key_iv_data_in_clear.d ),
+ .key_iv_data_in_clear_we_o ( hw2reg.trigger.key_iv_data_in_clear.de ),
+ .data_out_clear_o ( hw2reg.trigger.data_out_clear.d ),
+ .data_out_clear_we_o ( hw2reg.trigger.data_out_clear.de ),
+ .prng_reseed_o ( hw2reg.trigger.prng_reseed.d ),
+ .prng_reseed_we_o ( hw2reg.trigger.prng_reseed.de ),
- .output_valid_o ( hw2reg.status.output_valid.d ),
- .output_valid_we_o ( hw2reg.status.output_valid.de ),
- .input_ready_o ( hw2reg.status.input_ready.d ),
- .input_ready_we_o ( hw2reg.status.input_ready.de ),
- .idle_o ( hw2reg.status.idle.d ),
- .idle_we_o ( hw2reg.status.idle.de ),
- .stall_o ( hw2reg.status.stall.d ),
- .stall_we_o ( hw2reg.status.stall.de )
+ .output_valid_o ( hw2reg.status.output_valid.d ),
+ .output_valid_we_o ( hw2reg.status.output_valid.de ),
+ .input_ready_o ( hw2reg.status.input_ready.d ),
+ .input_ready_we_o ( hw2reg.status.input_ready.de ),
+ .idle_o ( hw2reg.status.idle.d ),
+ .idle_we_o ( hw2reg.status.idle.de ),
+ .stall_o ( hw2reg.status.stall.d ),
+ .stall_we_o ( hw2reg.status.stall.de )
);
// Input data register clear
diff --git a/hw/ip/aes/rtl/aes_reg_pkg.sv b/hw/ip/aes/rtl/aes_reg_pkg.sv
index 35944e1..5b10a92 100644
--- a/hw/ip/aes/rtl/aes_reg_pkg.sv
+++ b/hw/ip/aes/rtl/aes_reg_pkg.sv
@@ -85,13 +85,7 @@
} start;
struct packed {
logic q;
- } key_clear;
- struct packed {
- logic q;
- } iv_clear;
- struct packed {
- logic q;
- } data_in_clear;
+ } key_iv_data_in_clear;
struct packed {
logic q;
} data_out_clear;
@@ -148,15 +142,7 @@
struct packed {
logic d;
logic de;
- } key_clear;
- struct packed {
- logic d;
- logic de;
- } iv_clear;
- struct packed {
- logic d;
- logic de;
- } data_in_clear;
+ } key_iv_data_in_clear;
struct packed {
logic d;
logic de;
@@ -199,27 +185,27 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- aes_reg2hw_alert_test_reg_t alert_test; // [950:947]
- aes_reg2hw_key_share0_mreg_t [7:0] key_share0; // [946:683]
- aes_reg2hw_key_share1_mreg_t [7:0] key_share1; // [682:419]
- aes_reg2hw_iv_mreg_t [3:0] iv; // [418:287]
- aes_reg2hw_data_in_mreg_t [3:0] data_in; // [286:155]
- aes_reg2hw_data_out_mreg_t [3:0] data_out; // [154:23]
- aes_reg2hw_ctrl_shadowed_reg_t ctrl_shadowed; // [22:6]
- aes_reg2hw_trigger_reg_t trigger; // [5:0]
+ aes_reg2hw_alert_test_reg_t alert_test; // [948:945]
+ aes_reg2hw_key_share0_mreg_t [7:0] key_share0; // [944:681]
+ aes_reg2hw_key_share1_mreg_t [7:0] key_share1; // [680:417]
+ aes_reg2hw_iv_mreg_t [3:0] iv; // [416:285]
+ aes_reg2hw_data_in_mreg_t [3:0] data_in; // [284:153]
+ aes_reg2hw_data_out_mreg_t [3:0] data_out; // [152:21]
+ aes_reg2hw_ctrl_shadowed_reg_t ctrl_shadowed; // [20:4]
+ aes_reg2hw_trigger_reg_t trigger; // [3:0]
} aes_reg2hw_t;
///////////////////////////////////////
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- aes_hw2reg_key_share0_mreg_t [7:0] key_share0; // [935:680]
- aes_hw2reg_key_share1_mreg_t [7:0] key_share1; // [679:424]
- aes_hw2reg_iv_mreg_t [3:0] iv; // [423:296]
- aes_hw2reg_data_in_mreg_t [3:0] data_in; // [295:164]
- aes_hw2reg_data_out_mreg_t [3:0] data_out; // [163:36]
- aes_hw2reg_ctrl_shadowed_reg_t ctrl_shadowed; // [35:24]
- aes_hw2reg_trigger_reg_t trigger; // [23:12]
+ aes_hw2reg_key_share0_mreg_t [7:0] key_share0; // [931:676]
+ aes_hw2reg_key_share1_mreg_t [7:0] key_share1; // [675:420]
+ aes_hw2reg_iv_mreg_t [3:0] iv; // [419:292]
+ aes_hw2reg_data_in_mreg_t [3:0] data_in; // [291:160]
+ aes_hw2reg_data_out_mreg_t [3:0] data_out; // [159:32]
+ aes_hw2reg_ctrl_shadowed_reg_t ctrl_shadowed; // [31:20]
+ aes_hw2reg_trigger_reg_t trigger; // [19:12]
aes_hw2reg_status_reg_t status; // [11:0]
} aes_hw2reg_t;
diff --git a/hw/ip/aes/rtl/aes_reg_top.sv b/hw/ip/aes/rtl/aes_reg_top.sv
index 7b7d6e5..a8b59e2 100644
--- a/hw/ip/aes/rtl/aes_reg_top.sv
+++ b/hw/ip/aes/rtl/aes_reg_top.sv
@@ -153,12 +153,8 @@
logic ctrl_shadowed_force_zero_masks_re;
logic trigger_start_wd;
logic trigger_start_we;
- logic trigger_key_clear_wd;
- logic trigger_key_clear_we;
- logic trigger_iv_clear_wd;
- logic trigger_iv_clear_we;
- logic trigger_data_in_clear_wd;
- logic trigger_data_in_clear_we;
+ logic trigger_key_iv_data_in_clear_wd;
+ logic trigger_key_iv_data_in_clear_we;
logic trigger_data_out_clear_wd;
logic trigger_data_out_clear_we;
logic trigger_prng_reseed_wd;
@@ -805,82 +801,32 @@
);
- // F[key_clear]: 1:1
+ // F[key_iv_data_in_clear]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("WO"),
.RESVAL (1'h1)
- ) u_trigger_key_clear (
+ ) u_trigger_key_iv_data_in_clear (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (trigger_key_clear_we),
- .wd (trigger_key_clear_wd),
+ .we (trigger_key_iv_data_in_clear_we),
+ .wd (trigger_key_iv_data_in_clear_wd),
// from internal hardware
- .de (hw2reg.trigger.key_clear.de),
- .d (hw2reg.trigger.key_clear.d ),
+ .de (hw2reg.trigger.key_iv_data_in_clear.de),
+ .d (hw2reg.trigger.key_iv_data_in_clear.d ),
// to internal hardware
.qe (),
- .q (reg2hw.trigger.key_clear.q ),
+ .q (reg2hw.trigger.key_iv_data_in_clear.q ),
.qs ()
);
- // F[iv_clear]: 2:2
- prim_subreg #(
- .DW (1),
- .SWACCESS("WO"),
- .RESVAL (1'h1)
- ) u_trigger_iv_clear (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (trigger_iv_clear_we),
- .wd (trigger_iv_clear_wd),
-
- // from internal hardware
- .de (hw2reg.trigger.iv_clear.de),
- .d (hw2reg.trigger.iv_clear.d ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.trigger.iv_clear.q ),
-
- .qs ()
- );
-
-
- // F[data_in_clear]: 3:3
- prim_subreg #(
- .DW (1),
- .SWACCESS("WO"),
- .RESVAL (1'h1)
- ) u_trigger_data_in_clear (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (trigger_data_in_clear_we),
- .wd (trigger_data_in_clear_wd),
-
- // from internal hardware
- .de (hw2reg.trigger.data_in_clear.de),
- .d (hw2reg.trigger.data_in_clear.d ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.trigger.data_in_clear.q ),
-
- .qs ()
- );
-
-
- // F[data_out_clear]: 4:4
+ // F[data_out_clear]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("WO"),
@@ -905,7 +851,7 @@
);
- // F[prng_reseed]: 5:5
+ // F[prng_reseed]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("WO"),
@@ -1269,20 +1215,14 @@
assign trigger_start_we = addr_hit[30] & reg_we & ~wr_err;
assign trigger_start_wd = reg_wdata[0];
- assign trigger_key_clear_we = addr_hit[30] & reg_we & ~wr_err;
- assign trigger_key_clear_wd = reg_wdata[1];
-
- assign trigger_iv_clear_we = addr_hit[30] & reg_we & ~wr_err;
- assign trigger_iv_clear_wd = reg_wdata[2];
-
- assign trigger_data_in_clear_we = addr_hit[30] & reg_we & ~wr_err;
- assign trigger_data_in_clear_wd = reg_wdata[3];
+ assign trigger_key_iv_data_in_clear_we = addr_hit[30] & reg_we & ~wr_err;
+ assign trigger_key_iv_data_in_clear_wd = reg_wdata[1];
assign trigger_data_out_clear_we = addr_hit[30] & reg_we & ~wr_err;
- assign trigger_data_out_clear_wd = reg_wdata[4];
+ assign trigger_data_out_clear_wd = reg_wdata[2];
assign trigger_prng_reseed_we = addr_hit[30] & reg_we & ~wr_err;
- assign trigger_prng_reseed_wd = reg_wdata[5];
+ assign trigger_prng_reseed_wd = reg_wdata[3];
@@ -1424,8 +1364,6 @@
reg_rdata_next[1] = '0;
reg_rdata_next[2] = '0;
reg_rdata_next[3] = '0;
- reg_rdata_next[4] = '0;
- reg_rdata_next[5] = '0;
end
addr_hit[31]: begin
diff --git a/sw/device/lib/aes.c b/sw/device/lib/aes.c
index 59c51e5..a594ab5 100644
--- a/sw/device/lib/aes.c
+++ b/sw/device/lib/aes.c
@@ -129,8 +129,7 @@
// Clear internal key and output registers
REG32(AES0_BASE_ADDR + AES_TRIGGER_REG_OFFSET) =
- (0x1u << AES_TRIGGER_KEY_CLEAR_BIT) | (0x1u << AES_TRIGGER_IV_CLEAR_BIT) |
- (0x1u << AES_TRIGGER_DATA_IN_CLEAR_BIT) |
+ (0x1u << AES_TRIGGER_KEY_IV_DATA_IN_CLEAR_BIT) |
(0x1u << AES_TRIGGER_DATA_OUT_CLEAR_BIT);
// Wait for output not valid, and input ready
