commit baf037e509029315e409845baf6d0c502345d91c
author Mark Branstad <mark.branstad@wdc.com> Tue Aug 24 15:22:31 2021 -0700
committer Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> Tue Aug 24 15:46:52 2021 -0700
tree 1f168a50a7d9b8359c96879936cdf5bd36692735
parent 3ef8b9c82b52d50a537d20c06bf2cbdb8ed97c04

[csrng/hjson] Change hw_exc_sts swaccess to rw0c

To fix CSR test fails, changing swaccess keyword to proper setting.

Signed-off-by: Mark Branstad <mark.branstad@wdc.com>

hw/ip/csrng/data/csrng.hjson

diff --git a/hw/ip/csrng/data/csrng.hjson b/hw/ip/csrng/data/csrng.hjson
index a200f72..52d9106 100644
--- a/hw/ip/csrng/data/csrng.hjson
+++ b/hw/ip/csrng/data/csrng.hjson
@@ -252,7 +252,7 @@
     {
       name: "HW_EXC_STS",
       desc: "Hardware instance exception status register",
-      swaccess: "rw",
+      swaccess: "rw0c",
       hwaccess: "hwo",
       fields: [
         { bits: "14:0",

hw/ip/csrng/rtl/csrng_reg_top.sv

diff --git a/hw/ip/csrng/rtl/csrng_reg_top.sv b/hw/ip/csrng/rtl/csrng_reg_top.sv
index 8757cea..8f3c240 100644
--- a/hw/ip/csrng/rtl/csrng_reg_top.sv
+++ b/hw/ip/csrng/rtl/csrng_reg_top.sv
@@ -741,7 +741,7 @@
 
   prim_subreg #(
     .DW      (15),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (15'h0)
   ) u_hw_exc_sts (
     .clk_i   (clk_i),