[pinmux] Add block level synth setup

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/ip/pinmux/pinmux.core

diff --git a/hw/ip/pinmux/pinmux.core b/hw/ip/pinmux/pinmux.core
index e32e3b8..3c5a364 100644
--- a/hw/ip/pinmux/pinmux.core
+++ b/hw/ip/pinmux/pinmux.core
@@ -34,4 +34,11 @@
         verilator_options:
           - "-Wall"
 
-
+  syn:
+    <<: *default_target
+    # TODO: set default to DC once
+    # this option is available
+    # olofk/edalize#89
+    default_tool: icarus
+    parameters:
+      - SYNTHESIS=true

hw/ip/pinmux/syn/constraints.sdc

diff --git a/hw/ip/pinmux/syn/constraints.sdc b/hw/ip/pinmux/syn/constraints.sdc
new file mode 100644
index 0000000..8c1275d
--- /dev/null
+++ b/hw/ip/pinmux/syn/constraints.sdc
@@ -0,0 +1,58 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Generic constraints file for simple testsynthesis flow
+
+# note that we do not fix hold timing in this flow
+set SETUP_CLOCK_UNCERTAINTY 0.5
+
+#####################
+# main clock        #
+#####################
+set MAIN_CLK_PIN clk_i
+set MAIN_RST_PIN rst_ni
+set AON_CLK_PIN clk_aon_i
+
+
+# set main clock to 125 MHz
+set MAIN_TCK  8.0
+set_ideal_network ${MAIN_CLK_PIN}
+set_ideal_network ${MAIN_RST_PIN}
+set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${MAIN_CLK_PIN}
+
+# other timing constraint in ns
+set IN_DEL    1.0
+set OUT_DEL   1.0
+set DELAY     ${MAIN_TCK}
+
+create_clock ${MAIN_CLK_PIN} -period ${MAIN_TCK}
+create_clock ${AON_CLK_PIN} -period ${MAIN_TCK}
+
+# in to out
+set_max_delay ${DELAY} -from [all_inputs] -to [all_outputs]
+# in to reg / reg to out
+set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] [get_ports -of_objects [get_clocks]]] -clock ${MAIN_CLK_PIN}
+set_output_delay ${OUT_DEL}  [all_outputs] -clock ${MAIN_CLK_PIN}
+
+set_clock_groups -name group1 -async                               \
+    -group [get_clocks ${MAIN_CLK_PIN}                           ] \
+    -group [get_clocks ${AON_CLK_PIN}                            ] \
+
+#####################
+# I/O drive/load    #
+#####################
+
+# attach load and drivers to IOs to get a more realistic estimate
+set_driving_cell  -no_design_rule -lib_cell ${DRIVING_CELL} -pin ${DRIVING_CELL_PIN} [all_inputs]
+set_load [load_of ${LOAD_CELL_LIB}/${LOAD_CELL}/${LOAD_CELL_PIN}] [all_outputs]
+
+# set a nonzero critical range to be able to spot the violating paths better
+# in the report
+set_critical_range 0.5 ${DUT}
+
+#####################
+# Size Only Cells   #
+#####################
+
+set_size_only -all_instances [get_cells -h *u_size_only*] true

hw/ip/pinmux/syn/pinmux_syn_cfg.hjson

diff --git a/hw/ip/pinmux/syn/pinmux_syn_cfg.hjson b/hw/ip/pinmux/syn/pinmux_syn_cfg.hjson
new file mode 100644
index 0000000..ca919a0
--- /dev/null
+++ b/hw/ip/pinmux/syn/pinmux_syn_cfg.hjson
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  // Top level dut name (sv module).
+  name: pinmux
+
+  // Fusesoc core file used for building the file list.
+  fusesoc_core: lowrisc:ip:pinmux:0.1
+
+  import_cfgs: [// Project wide common synthesis config file
+                "{proj_root}/hw/syn/tools/dvsim/common_syn_cfg.hjson"],
+
+  overrides: [
+    {
+      name: design_level
+      value: "top"
+    }
+  ]
+
+  // Timing constraints for this module
+  sdc_file: "{proj_root}/hw/ip/pinmux/syn/constraints.sdc"
+
+  // Technology specific timing constraints for this module
+  foundry_sdc_file: "{foundry_root}/top_earlgrey/syn/foundry.constraints.sdc"
+}