| commit | b9a1d3134a5095536e6f4c5159dc1bb0b56a6331 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Dec 16 10:51:07 2021 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Thu Dec 16 16:49:15 2021 +0000 |
| tree | b058fd06a08d9b9a0bd3556171edf8252e875a11 | |
| parent | 60d70aa09ca707846942c51f9f1a2b4c5c614625 [diff] |
[otbn] Some reformatting changes suggested by verible formatter
These seem to match our style guide and to improve the general layout.
There are some other changes that verible suggests at the moment that
look a bit more suspect and we might want to tweak it for. Those
changes are not included in this commit.
These come from running
find hw/ip/otbn/rtl -name '*.sv' | \
xargs util/verible-format.py --inplace -f
with the most recent version of Verible (v0.0-1784-g9f0278ee).
I've only included 10 files in the commit because reviewing this sort
of thing is a bit painful, so I thought it might be better to do it in
batches!
All of the changes are shuffling around whitespace. To see this, run
something like `git diff -w HEAD^..HEAD`. That should give us
confidence that the commit won't introduce any RTL bugs.
Other than little typos, most of the changes here are to do with
formatting port lists, both in the declarations of modules, and in
their instantiations. For better or for worse, we've agreed on a
format in our style guide; these changes tweak our code to match that.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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