commit b9894bf607066b4ae72b7da450d904a4accd55f0
author Steve Nelson <steve.nelson@wdc.com> Fri Apr 03 09:56:52 2020 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Fri Apr 03 13:46:30 2020 -0700
tree 529867197c12a35d5e3d9a1441b3711773745293
parent 84dac533bf92f781a4c178905c06a6358e5d7dbb

[dv:entropy_src] Changes from comments on PR 1862

Signed-off-by: Steve Nelson <steve.nelson@wdc.com>

hw/ip/entropy_src/data/entropy_src_testplan.hjson

diff --git a/hw/ip/entropy_src/data/entropy_src_testplan.hjson b/hw/ip/entropy_src/data/entropy_src_testplan.hjson
index d302675..e64f209 100644
--- a/hw/ip/entropy_src/data/entropy_src_testplan.hjson
+++ b/hw/ip/entropy_src/data/entropy_src_testplan.hjson
@@ -5,7 +5,6 @@
   name: "entropy_src"
   // TODO: remove the common testplans if not applicable
   import_testplans: ["hw/dv/tools/testplans/csr_testplan.hjson",
-                     "hw/dv/tools/testplans/mem_testplan.hjson",
                      "hw/dv/tools/testplans/intr_test_testplan.hjson",
                      "hw/dv/tools/testplans/tl_device_access_types_testplan.hjson"]
   entries: [

hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson

diff --git a/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson b/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson
index b3b15dd..2945782 100644
--- a/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson
+++ b/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson
@@ -12,7 +12,7 @@
   tb: tb
 
   // Simulator used to sign off this block
-  tool: vcs
+  tool: xcelium
 
   // Fusesoc core file used for building the file list.
   fusesoc_core: lowrisc:dv:entropy_src_sim:0.1

hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv

diff --git a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
index 6f1ca8a..fbbdad7 100644
--- a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
+++ b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
@@ -60,23 +60,23 @@
       // add individual case item for each csr
       "es_conf": begin
          if (write) begin
-           `uvm_info(`gfn, $sformatf("Write to ES_CONF register"), UVM_NONE)
+           `uvm_info(`gfn, $sformatf("Write to ES_CONF register"), UVM_DEBUG)
 	 end
          else begin
-           `uvm_info(`gfn, $sformatf("Read from ES_CONF register"), UVM_NONE)
+           `uvm_info(`gfn, $sformatf("Read from ES_CONF register"), UVM_DEBUG)
 	 end
       end
       "es_rev": begin
          if (!write) begin
-           `uvm_info(`gfn, $sformatf("Read from ES_REV register"), UVM_NONE)
+           `uvm_info(`gfn, $sformatf("Read from ES_REV register"), UVM_DEBUG)
 	 end
       end
       "intr_state": begin
          if (write) begin
-           `uvm_info(`gfn, $sformatf("Write to INTR_STATE register"), UVM_NONE)
+           `uvm_info(`gfn, $sformatf("Write to INTR_STATE register"), UVM_DEBUG)
 	 end
          else begin
-           `uvm_info(`gfn, $sformatf("Read from INTR_STATE register"), UVM_NONE)
+           `uvm_info(`gfn, $sformatf("Read from INTR_STATE register"), UVM_DEBUG)
 	 end
       end
       default: begin