commit b8f24c49177d388d43a1a5e438b7b6709b8095fe
author Pirmin Vogel <vogelpi@lowrisc.org> Fri Jan 21 21:47:47 2022 +0100
committer Pirmin Vogel <vogelpi@lowrisc.org> Mon Jan 24 22:00:04 2022 +0100
tree 9d41531aee612afda65fe608e2c08c8eb02b54a2
parent 65fe5bbda9f9959141b686c85943ee64a649e3f1

[top_englishbreakfast] Disconnect system bus access of debug module

This commit removes the rv_dm.sba port on the main interconnect to free
up some FPGA logic resources on the CW305.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>

hw/top_englishbreakfast/data/xbar_main.hjson

diff --git a/hw/top_englishbreakfast/data/xbar_main.hjson b/hw/top_englishbreakfast/data/xbar_main.hjson
index e56b970..35962ca 100644
--- a/hw/top_englishbreakfast/data/xbar_main.hjson
+++ b/hw/top_englishbreakfast/data/xbar_main.hjson
@@ -22,12 +22,6 @@
       reset: "rst_main_ni",
       pipeline: "false"
     },
-    { name:      "rv_dm.sba",
-      type:      "host",
-      clock:     "clk_main_i",
-      reset:     "rst_main_ni",
-      pipeline_byp: "false"
-    },
     { name:      "rv_dm.regs",
       type:      "device",
       clock:     "clk_main_i",
@@ -123,11 +117,5 @@
       "rv_plic", "sram_ctrl_main.ram", "sram_ctrl_main.regs",
       "rv_core_ibex.cfg"
     ],
-    rv_dm.sba: [
-      "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.regs", "sram_ctrl_main.ram",
-      "flash_ctrl.mem", "peri", "flash_ctrl.core", "flash_ctrl.prim", "aes",
-      "hmac", "rv_plic",
-      "sram_ctrl_main.regs", "rv_core_ibex.cfg"
-    ],
   },
 }