[otbn] Add instruction counter.
A 32-bit register is added to count instructions during the OTBN
procedure.
Signed-off-by: Vladimir Rozic <vrozic@lowrisc.org>
diff --git a/hw/ip/otbn/rtl/otbn_controller.sv b/hw/ip/otbn/rtl/otbn_controller.sv
index 29fc216..de7788c 100644
--- a/hw/ip/otbn/rtl/otbn_controller.sv
+++ b/hw/ip/otbn/rtl/otbn_controller.sv
@@ -121,7 +121,9 @@
output logic rnd_req_o,
output logic rnd_prefetch_req_o,
- input logic rnd_valid_i
+ input logic rnd_valid_i,
+
+ output logic [31:0] insn_cnt_o
);
otbn_state_e state_q, state_d, state_raw;
@@ -201,6 +203,9 @@
logic rf_a_indirect_err, rf_b_indirect_err, rf_d_indirect_err, rf_indirect_err;
+ logic insn_cnt_en;
+ logic [31:0] insn_cnt_d, insn_cnt_q;
+
// Stall a cycle on loads to allow load data writeback to happen the following cycle. Stall not
// required on stores as there is no response to deal with.
// TODO: Possibility of error response on store? Probably still don't need to stall in that case
@@ -345,6 +350,18 @@
end
end
+ assign insn_cnt_d = start_i ? 32'd0 : (insn_cnt_q + 32'd1);
+ assign insn_cnt_en = (insn_executing & ~stall & (insn_cnt_q != 32'hffffffff)) | start_i;
+ assign insn_cnt_o = insn_cnt_q;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ insn_cnt_q <= 32'd0;
+ end else if (insn_cnt_en) begin
+ insn_cnt_q <= insn_cnt_d;
+ end
+ end
+
otbn_loop_controller #(
.ImemAddrWidth(ImemAddrWidth)
) u_otbn_loop_controller (
