[keymgr] Convert configuration to shadow register
- split start from configuration since shadow registers do now support hrw
- this is part of keymgr d2s likely review items
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/keymgr/data/keymgr.hjson b/hw/ip/keymgr/data/keymgr.hjson
index c978b0f..f9626e0 100644
--- a/hw/ip/keymgr/data/keymgr.hjson
+++ b/hw/ip/keymgr/data/keymgr.hjson
@@ -240,23 +240,20 @@
key manager configuration enable.
When key manager operation is started (see CONTROL), registers protected by this EN are no longer
modifiable until the operation completes.
-
- TBD
- This should be enhanced to support multi-bit values in the future. Should be another script change.
'''
},
]
},
- { name: "CONTROL",
- desc: "Key manager operation controls",
- regwen: "CFG_REGWEN",
+ { name: "START",
+ desc: "Key manager operation start",
swaccess: "rw",
- hwaccess: "hro",
+ hwaccess: "hrw",
+ regwen: "CFG_REGWEN",
fields: [
{ bits: "0",
hwaccess: "hrw",
- name: "START",
+ name: "EN",
desc: "Start key manager operations",
resval: "0"
enum: [
@@ -269,8 +266,19 @@
]
tags: [// bit self clears, handle in directed test
"excl:CsrNonInitTests:CsrExclWrite"]
- },
+ }
+ ]
+ },
+ { name: "CONTROL_SHADOWED",
+ desc: "Key manager operation controls",
+ regwen: "CFG_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ update_err_alert: "recov_operation_err",
+ storage_err_alert: "fatal_fault_err",
+ fields: [
{ bits: "6:4",
name: "OPERATION",
desc: "Key manager operation selection. All values not enumerated below behave the same as disable",
diff --git a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
index 6360662..c1e29f7 100644
--- a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
+++ b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
@@ -219,7 +219,7 @@
UpdateHwOut: begin
kmac_digests_t key_shares = {item.rsp_digest_share1, item.rsp_digest_share0};
keymgr_pkg::keymgr_key_dest_e dest = keymgr_pkg::keymgr_key_dest_e'(
- `gmv(ral.control.dest_sel));
+ `gmv(ral.control_shadowed.dest_sel));
if (dest != keymgr_pkg::None && !get_fault_err()) begin
cfg.keymgr_vif.update_sideload_key(key_shares, current_state, current_cdi, dest);
@@ -271,7 +271,7 @@
if (cfg.en_cov && cfg.keymgr_vif.get_keymgr_en() && is_final_kdf) begin
keymgr_pkg::keymgr_key_dest_e dest = keymgr_pkg::keymgr_key_dest_e'(
- `gmv(ral.control.dest_sel));
+ `gmv(ral.control_shadowed.dest_sel));
cov.state_and_op_cg.sample(current_state, op, current_op_status, current_cdi, dest);
end
end
@@ -410,7 +410,7 @@
if (cfg.en_cov && ral.cfg_regwen.locks_reg_or_fld(dv_reg) &&
cfg.keymgr_vif.get_keymgr_en()) begin
bit cfg_regwen = (current_op_status == keymgr_pkg::OpWip);
- if (csr.get_name() == "control") begin
+ if (csr.get_name() == "control_shadowed") begin
cov.control_w_regwen_cg.sample(item.a_data, cfg_regwen);
end else if (csr.get_name() == "sideload_clear") begin
cov.sideload_clear_cg.sample(`gmv(ral.sideload_clear.val),
@@ -538,9 +538,9 @@
end
end
end
- "control": begin
+ "start": begin
if (addr_phase_write) begin
- bit start = `gmv(ral.control.start);
+ bit start = `gmv(ral.start.en);
if (start) begin
keymgr_pkg::keymgr_ops_e op = get_operation();
@@ -581,7 +581,7 @@
if (cfg.en_cov) begin
keymgr_pkg::keymgr_key_dest_e dest = keymgr_pkg::keymgr_key_dest_e'(
- `gmv(ral.control.dest_sel));
+ `gmv(ral.control_shadowed.dest_sel));
cov.state_and_op_cg.sample(current_state, op, current_op_status,
current_cdi, dest);
@@ -605,7 +605,7 @@
if (op == keymgr_pkg::OpAdvance) begin
current_cdi = get_adv_cdi_type();
end else begin
- int cdi_sel = `gmv(ral.control.cdi_sel);
+ int cdi_sel = `gmv(ral.control_shadowed.cdi_sel);
`downcast(current_cdi, cdi_sel)
end
// update kmac key for check
@@ -616,7 +616,7 @@
end
endcase
// start will be clear after OP is done
- void'(ral.control.start.predict(.value(0), .kind(UVM_PREDICT_WRITE)));
+ void'(ral.start.en.predict(.value(0), .kind(UVM_PREDICT_WRITE)));
end // start
end // addr_phase_write
end
@@ -660,7 +660,7 @@
if (cfg.en_cov) begin
keymgr_pkg::keymgr_key_dest_e dest = keymgr_pkg::keymgr_key_dest_e'(
- `gmv(ral.control.dest_sel));
+ `gmv(ral.control_shadowed.dest_sel));
cov.state_and_op_cg.sample(current_state, get_operation(), current_op_status,
current_cdi, dest);
@@ -1082,7 +1082,7 @@
gen_out_data_t exp, act;
keymgr_pkg::keymgr_ops_e op = get_operation();
keymgr_pkg::keymgr_key_dest_e dest = keymgr_pkg::keymgr_key_dest_e'(
- `gmv(ral.control.dest_sel));
+ `gmv(ral.control_shadowed.dest_sel));
string str;
act = {<<8{byte_data_q}};
@@ -1141,7 +1141,7 @@
// if it's not defined operation, treat as OpDisable
virtual function keymgr_pkg::keymgr_ops_e get_operation();
keymgr_pkg::keymgr_ops_e op;
- int op_int_val = `gmv(ral.control.operation);
+ int op_int_val = `gmv(ral.control_shadowed.operation);
if (!$cast(op, op_int_val)) op = keymgr_pkg::OpDisable;
return op;
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_base_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_base_vseq.sv
index a44d1fe..272a967 100644
--- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_base_vseq.sv
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_base_vseq.sv
@@ -141,7 +141,7 @@
keymgr_pkg::keymgr_op_status_e exp_status;
bit is_good_op = 1;
int key_verion = `gmv(ral.key_version[0]);
- keymgr_pkg::keymgr_ops_e operation = `gmv(ral.control.operation);
+ keymgr_pkg::keymgr_ops_e operation = `gmv(ral.control_shadowed.operation);
bit[TL_DW-1:0] rd_val;
if (operation inside {keymgr_pkg::OpGenSwOut, keymgr_pkg::OpGenHwOut}) begin
@@ -216,9 +216,10 @@
virtual task keymgr_advance(bit wait_done = 1);
keymgr_pkg::keymgr_working_state_e exp_next_state = get_next_state(current_state);
`uvm_info(`gfn, $sformatf("Advance key manager state from %0s", current_state.name), UVM_MEDIUM)
- ral.control.start.set(1'b1);
- ral.control.operation.set(keymgr_pkg::OpAdvance);
- csr_update(.csr(ral.control));
+ ral.control_shadowed.operation.set(keymgr_pkg::OpAdvance);
+ csr_update(.csr(ral.control_shadowed));
+ ral.start.en.set(1'b1);
+ csr_update(.csr(ral.start));
if (wait_done) begin
wait_op_done();
@@ -232,12 +233,13 @@
bit wait_done = 1);
`uvm_info(`gfn, "Generate key manager output", UVM_MEDIUM)
- ral.control.start.set(1'b1);
- ral.control.operation.set(int'(operation));
- `DV_CHECK_RANDOMIZE_FATAL(ral.control.cdi_sel)
- ral.control.dest_sel.set(int'(key_dest));
- csr_update(.csr(ral.control));
- ral.control.start.set(1'b0);
+ ral.control_shadowed.operation.set(int'(operation));
+ `DV_CHECK_RANDOMIZE_FATAL(ral.control_shadowed.cdi_sel)
+ ral.control_shadowed.dest_sel.set(int'(key_dest));
+ csr_update(.csr(ral.control_shadowed));
+ ral.start.en.set(1'b1);
+ csr_update(.csr(ral.start));
+ ral.start.en.set(1'b0);
if (wait_done) wait_op_done();
endtask : keymgr_generate
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfg_regwen_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfg_regwen_vseq.sv
index c0ed043..ffec5a0 100644
--- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfg_regwen_vseq.sv
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfg_regwen_vseq.sv
@@ -72,8 +72,8 @@
`uvm_info(`gfn, $sformatf("Write regwen lockable reg %0s, and this write should be ignored",
lockable_reg.get_name()), UVM_MEDIUM)
csr_wr(lockable_reg, val);
- // if it's control, wait until OP is done, so that control.start is clear
- if (lockable_reg.get_name() == "control") begin
+ // if it's control, wait until OP is done, so that start.en is clear
+ if (lockable_reg.get_name() == "control_shadowed") begin
csr_spinwait(.ptr(ral.op_status.status), .exp_data(keymgr_pkg::OpWip),
.compare_op(CompareOpNe));
end
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_direct_to_disabled_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_direct_to_disabled_vseq.sv
index 4fde772..12c5baa 100644
--- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_direct_to_disabled_vseq.sv
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_direct_to_disabled_vseq.sv
@@ -16,14 +16,14 @@
end
`uvm_info(`gfn, $sformatf("Directly go to Disabled from %0s", current_state.name), UVM_MEDIUM)
- ral.control.start.set(1'b1);
- `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.control.operation,
+ ral.start.en.set(1'b1);
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.control_shadowed.operation,
// All values not enumerated below behave the same as disable
!(value inside {keymgr_pkg::OpAdvance,
keymgr_pkg::OpGenId,
keymgr_pkg::OpGenSwOut,
keymgr_pkg::OpGenHwOut});)
- csr_update(.csr(ral.control));
+ csr_update(.csr(ral.start));
wait_op_done();
if (get_check_en()) `DV_CHECK_EQ(current_state, keymgr_pkg::StDisabled)
diff --git a/hw/ip/keymgr/rtl/keymgr.sv b/hw/ip/keymgr/rtl/keymgr.sv
index 3da9246..a6bb0c4 100644
--- a/hw/ip/keymgr/rtl/keymgr.sv
+++ b/hw/ip/keymgr/rtl/keymgr.sv
@@ -136,12 +136,18 @@
.devmode_i (1'b1) // connect to real devmode signal in the future
);
- assign shadowed_storage_err = reg2hw.reseed_interval_shadowed.err_storage |
+ assign shadowed_storage_err = reg2hw.control_shadowed.cdi_sel.err_storage |
+ reg2hw.control_shadowed.dest_sel.err_storage |
+ reg2hw.control_shadowed.operation.err_storage |
+ reg2hw.reseed_interval_shadowed.err_storage |
reg2hw.max_creator_key_ver_shadowed.err_storage |
reg2hw.max_owner_int_key_ver_shadowed.err_storage |
reg2hw.max_owner_key_ver_shadowed.err_storage;
- assign shadowed_update_err = reg2hw.reseed_interval_shadowed.err_update |
+ assign shadowed_update_err = reg2hw.control_shadowed.cdi_sel.err_update |
+ reg2hw.control_shadowed.dest_sel.err_update |
+ reg2hw.control_shadowed.operation.err_update |
+ reg2hw.reseed_interval_shadowed.err_update |
reg2hw.max_creator_key_ver_shadowed.err_update |
reg2hw.max_owner_int_key_ver_shadowed.err_update |
reg2hw.max_owner_key_ver_shadowed.err_update;
@@ -215,7 +221,7 @@
// DV. When an invalid operation is selected, the keymgr just starts transmitting
// whatever is at the prng output, however, this may cause a dv protocol violation
// if a reseed happens to coincide.
- .seed_en_i(seed_en & ~reg2hw.control.start.q),
+ .seed_en_i(seed_en & ~reg2hw.start.q),
.seed_i(seed),
.entropy_i('0),
.state_o(lfsr)
@@ -277,9 +283,9 @@
.prng_reseed_ack_i(reseed_ack),
.prng_en_o(ctrl_lfsr_en),
.entropy_i(ctrl_rand),
- .op_i(keymgr_ops_e'(reg2hw.control.operation.q)),
- .op_start_i(reg2hw.control.start.q),
- .op_cdi_sel_i(reg2hw.control.cdi_sel.q),
+ .op_i(keymgr_ops_e'(reg2hw.control_shadowed.operation.q)),
+ .op_start_i(reg2hw.start.q),
+ .op_cdi_sel_i(reg2hw.control_shadowed.cdi_sel.q),
.op_done_o(op_done),
.init_o(init),
.sw_binding_unlock_o(sw_binding_unlock),
@@ -307,10 +313,10 @@
.kmac_data_i(kmac_data_truncated)
);
- assign hw2reg.control.start.d = '0;
- assign hw2reg.control.start.de = op_done;
+ assign hw2reg.start.d = '0;
+ assign hw2reg.start.de = op_done;
// as long as operation is ongoing, capture status
- assign hw2reg.op_status.de = reg2hw.control.start.q;
+ assign hw2reg.op_status.de = reg2hw.start.q;
// working state is always visible
assign hw2reg.working_state.de = 1'b1;
@@ -323,8 +329,8 @@
.rst_ni,
.init_i(1'b1), // cfg_regwen does not care about init
.en_i(lc_keymgr_en[KeyMgrEnCfgEn] == lc_ctrl_pkg::On),
- .set_i(reg2hw.control.start.q & op_done),
- .clr_i(reg2hw.control.start.q),
+ .set_i(reg2hw.start.q & op_done),
+ .clr_i(reg2hw.start.q),
.out_o(cfg_regwen)
);
@@ -431,7 +437,7 @@
keymgr_key_dest_e cipher_sel;
logic [KeyWidth-1:0] cipher_seed;
- assign cipher_sel = keymgr_key_dest_e'(reg2hw.control.dest_sel);
+ assign cipher_sel = keymgr_key_dest_e'(reg2hw.control_shadowed.dest_sel.q);
assign cipher_seed = cipher_sel == Aes ? aes_seed :
cipher_sel == Kmac ? kmac_seed :
cipher_sel == Otbn ? otbn_seed : RndCnstNoneSeed;
@@ -684,11 +690,9 @@
`ASSERT_KNOWN(IntrKnownO_A, intr_op_done_o)
`ASSERT_KNOWN(AlertKnownO_A, alert_tx_o)
- // the keys are not reset to any specific values
- // TBD this may be changed depending on whether we want to support this
- // mode of operation going forward.
- `ASSERT_KNOWN(AesKeyKnownO_A, aes_key_o.valid)
- `ASSERT_KNOWN(KmacKeyKnownO_A, kmac_key_o.valid)
+ `ASSERT_KNOWN(AesKeyKnownO_A, aes_key_o)
+ `ASSERT_KNOWN(KmacKeyKnownO_A, kmac_key_o)
+ `ASSERT_KNOWN(OtbnKeyKnownO_A, otbn_key_o)
`ASSERT_KNOWN(KmacDataKnownO_A, kmac_data_o)
// kmac parameter consistency
diff --git a/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv b/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv
index 92b5a79..a9a0003 100644
--- a/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv
+++ b/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv
@@ -45,19 +45,26 @@
} keymgr_reg2hw_alert_test_reg_t;
typedef struct packed {
- struct packed {
- logic q;
- } start;
+ logic q;
+ } keymgr_reg2hw_start_reg_t;
+
+ typedef struct packed {
struct packed {
logic [2:0] q;
+ logic err_update;
+ logic err_storage;
} operation;
struct packed {
logic q;
+ logic err_update;
+ logic err_storage;
} cdi_sel;
struct packed {
logic [2:0] q;
+ logic err_update;
+ logic err_storage;
} dest_sel;
- } keymgr_reg2hw_control_reg_t;
+ } keymgr_reg2hw_control_shadowed_reg_t;
typedef struct packed {
logic [2:0] q;
@@ -151,11 +158,9 @@
} keymgr_hw2reg_cfg_regwen_reg_t;
typedef struct packed {
- struct packed {
- logic d;
- logic de;
- } start;
- } keymgr_hw2reg_control_reg_t;
+ logic d;
+ logic de;
+ } keymgr_hw2reg_start_reg_t;
typedef struct packed {
logic d;
@@ -245,7 +250,8 @@
keymgr_reg2hw_intr_enable_reg_t intr_enable; // [941:941]
keymgr_reg2hw_intr_test_reg_t intr_test; // [940:939]
keymgr_reg2hw_alert_test_reg_t alert_test; // [938:935]
- keymgr_reg2hw_control_reg_t control; // [934:927]
+ keymgr_reg2hw_start_reg_t start; // [934:934]
+ keymgr_reg2hw_control_shadowed_reg_t control_shadowed; // [933:927]
keymgr_reg2hw_sideload_clear_reg_t sideload_clear; // [926:924]
keymgr_reg2hw_reseed_interval_shadowed_reg_t reseed_interval_shadowed; // [923:908]
keymgr_reg2hw_sw_binding_regwen_reg_t sw_binding_regwen; // [907:906]
@@ -263,7 +269,7 @@
typedef struct packed {
keymgr_hw2reg_intr_state_reg_t intr_state; // [566:565]
keymgr_hw2reg_cfg_regwen_reg_t cfg_regwen; // [564:564]
- keymgr_hw2reg_control_reg_t control; // [563:562]
+ keymgr_hw2reg_start_reg_t start; // [563:562]
keymgr_hw2reg_sw_binding_regwen_reg_t sw_binding_regwen; // [561:561]
keymgr_hw2reg_sw_share0_output_mreg_t [7:0] sw_share0_output; // [560:297]
keymgr_hw2reg_sw_share1_output_mreg_t [7:0] sw_share1_output; // [296:33]
@@ -279,62 +285,63 @@
parameter logic [BlockAw-1:0] KEYMGR_INTR_TEST_OFFSET = 8'h 8;
parameter logic [BlockAw-1:0] KEYMGR_ALERT_TEST_OFFSET = 8'h c;
parameter logic [BlockAw-1:0] KEYMGR_CFG_REGWEN_OFFSET = 8'h 10;
- parameter logic [BlockAw-1:0] KEYMGR_CONTROL_OFFSET = 8'h 14;
- parameter logic [BlockAw-1:0] KEYMGR_SIDELOAD_CLEAR_OFFSET = 8'h 18;
- parameter logic [BlockAw-1:0] KEYMGR_RESEED_INTERVAL_REGWEN_OFFSET = 8'h 1c;
- parameter logic [BlockAw-1:0] KEYMGR_RESEED_INTERVAL_SHADOWED_OFFSET = 8'h 20;
- parameter logic [BlockAw-1:0] KEYMGR_SW_BINDING_REGWEN_OFFSET = 8'h 24;
- parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_0_OFFSET = 8'h 28;
- parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_1_OFFSET = 8'h 2c;
- parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_2_OFFSET = 8'h 30;
- parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_3_OFFSET = 8'h 34;
- parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_4_OFFSET = 8'h 38;
- parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_5_OFFSET = 8'h 3c;
- parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_6_OFFSET = 8'h 40;
- parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_7_OFFSET = 8'h 44;
- parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_0_OFFSET = 8'h 48;
- parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_1_OFFSET = 8'h 4c;
- parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_2_OFFSET = 8'h 50;
- parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_3_OFFSET = 8'h 54;
- parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_4_OFFSET = 8'h 58;
- parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_5_OFFSET = 8'h 5c;
- parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_6_OFFSET = 8'h 60;
- parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_7_OFFSET = 8'h 64;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_0_OFFSET = 8'h 68;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_1_OFFSET = 8'h 6c;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_2_OFFSET = 8'h 70;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_3_OFFSET = 8'h 74;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_4_OFFSET = 8'h 78;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_5_OFFSET = 8'h 7c;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_6_OFFSET = 8'h 80;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_7_OFFSET = 8'h 84;
- parameter logic [BlockAw-1:0] KEYMGR_KEY_VERSION_OFFSET = 8'h 88;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET = 8'h 8c;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_CREATOR_KEY_VER_SHADOWED_OFFSET = 8'h 90;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET = 8'h 94;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_INT_KEY_VER_SHADOWED_OFFSET = 8'h 98;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET = 8'h 9c;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_KEY_VER_SHADOWED_OFFSET = 8'h a0;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET = 8'h a4;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET = 8'h a8;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET = 8'h ac;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET = 8'h b0;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET = 8'h b4;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET = 8'h b8;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET = 8'h bc;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET = 8'h c0;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET = 8'h c4;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET = 8'h c8;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET = 8'h cc;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET = 8'h d0;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET = 8'h d4;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET = 8'h d8;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET = 8'h dc;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET = 8'h e0;
- parameter logic [BlockAw-1:0] KEYMGR_WORKING_STATE_OFFSET = 8'h e4;
- parameter logic [BlockAw-1:0] KEYMGR_OP_STATUS_OFFSET = 8'h e8;
- parameter logic [BlockAw-1:0] KEYMGR_ERR_CODE_OFFSET = 8'h ec;
- parameter logic [BlockAw-1:0] KEYMGR_FAULT_STATUS_OFFSET = 8'h f0;
+ parameter logic [BlockAw-1:0] KEYMGR_START_OFFSET = 8'h 14;
+ parameter logic [BlockAw-1:0] KEYMGR_CONTROL_SHADOWED_OFFSET = 8'h 18;
+ parameter logic [BlockAw-1:0] KEYMGR_SIDELOAD_CLEAR_OFFSET = 8'h 1c;
+ parameter logic [BlockAw-1:0] KEYMGR_RESEED_INTERVAL_REGWEN_OFFSET = 8'h 20;
+ parameter logic [BlockAw-1:0] KEYMGR_RESEED_INTERVAL_SHADOWED_OFFSET = 8'h 24;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_BINDING_REGWEN_OFFSET = 8'h 28;
+ parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_0_OFFSET = 8'h 2c;
+ parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_1_OFFSET = 8'h 30;
+ parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_2_OFFSET = 8'h 34;
+ parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_3_OFFSET = 8'h 38;
+ parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_4_OFFSET = 8'h 3c;
+ parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_5_OFFSET = 8'h 40;
+ parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_6_OFFSET = 8'h 44;
+ parameter logic [BlockAw-1:0] KEYMGR_SEALING_SW_BINDING_7_OFFSET = 8'h 48;
+ parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_0_OFFSET = 8'h 4c;
+ parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_1_OFFSET = 8'h 50;
+ parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_2_OFFSET = 8'h 54;
+ parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_3_OFFSET = 8'h 58;
+ parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_4_OFFSET = 8'h 5c;
+ parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_5_OFFSET = 8'h 60;
+ parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_6_OFFSET = 8'h 64;
+ parameter logic [BlockAw-1:0] KEYMGR_ATTEST_SW_BINDING_7_OFFSET = 8'h 68;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_0_OFFSET = 8'h 6c;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_1_OFFSET = 8'h 70;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_2_OFFSET = 8'h 74;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_3_OFFSET = 8'h 78;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_4_OFFSET = 8'h 7c;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_5_OFFSET = 8'h 80;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_6_OFFSET = 8'h 84;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_7_OFFSET = 8'h 88;
+ parameter logic [BlockAw-1:0] KEYMGR_KEY_VERSION_OFFSET = 8'h 8c;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET = 8'h 90;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_CREATOR_KEY_VER_SHADOWED_OFFSET = 8'h 94;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET = 8'h 98;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_INT_KEY_VER_SHADOWED_OFFSET = 8'h 9c;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET = 8'h a0;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_KEY_VER_SHADOWED_OFFSET = 8'h a4;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET = 8'h a8;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET = 8'h ac;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET = 8'h b0;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET = 8'h b4;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET = 8'h b8;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET = 8'h bc;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET = 8'h c0;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET = 8'h c4;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET = 8'h c8;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET = 8'h cc;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET = 8'h d0;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET = 8'h d4;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET = 8'h d8;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET = 8'h dc;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET = 8'h e0;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET = 8'h e4;
+ parameter logic [BlockAw-1:0] KEYMGR_WORKING_STATE_OFFSET = 8'h e8;
+ parameter logic [BlockAw-1:0] KEYMGR_OP_STATUS_OFFSET = 8'h ec;
+ parameter logic [BlockAw-1:0] KEYMGR_ERR_CODE_OFFSET = 8'h f0;
+ parameter logic [BlockAw-1:0] KEYMGR_FAULT_STATUS_OFFSET = 8'h f4;
// Reset values for hwext registers and their fields
parameter logic [0:0] KEYMGR_INTR_TEST_RESVAL = 1'h 0;
@@ -354,7 +361,8 @@
KEYMGR_INTR_TEST,
KEYMGR_ALERT_TEST,
KEYMGR_CFG_REGWEN,
- KEYMGR_CONTROL,
+ KEYMGR_START,
+ KEYMGR_CONTROL_SHADOWED,
KEYMGR_SIDELOAD_CLEAR,
KEYMGR_RESEED_INTERVAL_REGWEN,
KEYMGR_RESEED_INTERVAL_SHADOWED,
@@ -413,68 +421,69 @@
} keymgr_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] KEYMGR_PERMIT [61] = '{
+ parameter logic [3:0] KEYMGR_PERMIT [62] = '{
4'b 0001, // index[ 0] KEYMGR_INTR_STATE
4'b 0001, // index[ 1] KEYMGR_INTR_ENABLE
4'b 0001, // index[ 2] KEYMGR_INTR_TEST
4'b 0001, // index[ 3] KEYMGR_ALERT_TEST
4'b 0001, // index[ 4] KEYMGR_CFG_REGWEN
- 4'b 0011, // index[ 5] KEYMGR_CONTROL
- 4'b 0001, // index[ 6] KEYMGR_SIDELOAD_CLEAR
- 4'b 0001, // index[ 7] KEYMGR_RESEED_INTERVAL_REGWEN
- 4'b 0011, // index[ 8] KEYMGR_RESEED_INTERVAL_SHADOWED
- 4'b 0001, // index[ 9] KEYMGR_SW_BINDING_REGWEN
- 4'b 1111, // index[10] KEYMGR_SEALING_SW_BINDING_0
- 4'b 1111, // index[11] KEYMGR_SEALING_SW_BINDING_1
- 4'b 1111, // index[12] KEYMGR_SEALING_SW_BINDING_2
- 4'b 1111, // index[13] KEYMGR_SEALING_SW_BINDING_3
- 4'b 1111, // index[14] KEYMGR_SEALING_SW_BINDING_4
- 4'b 1111, // index[15] KEYMGR_SEALING_SW_BINDING_5
- 4'b 1111, // index[16] KEYMGR_SEALING_SW_BINDING_6
- 4'b 1111, // index[17] KEYMGR_SEALING_SW_BINDING_7
- 4'b 1111, // index[18] KEYMGR_ATTEST_SW_BINDING_0
- 4'b 1111, // index[19] KEYMGR_ATTEST_SW_BINDING_1
- 4'b 1111, // index[20] KEYMGR_ATTEST_SW_BINDING_2
- 4'b 1111, // index[21] KEYMGR_ATTEST_SW_BINDING_3
- 4'b 1111, // index[22] KEYMGR_ATTEST_SW_BINDING_4
- 4'b 1111, // index[23] KEYMGR_ATTEST_SW_BINDING_5
- 4'b 1111, // index[24] KEYMGR_ATTEST_SW_BINDING_6
- 4'b 1111, // index[25] KEYMGR_ATTEST_SW_BINDING_7
- 4'b 1111, // index[26] KEYMGR_SALT_0
- 4'b 1111, // index[27] KEYMGR_SALT_1
- 4'b 1111, // index[28] KEYMGR_SALT_2
- 4'b 1111, // index[29] KEYMGR_SALT_3
- 4'b 1111, // index[30] KEYMGR_SALT_4
- 4'b 1111, // index[31] KEYMGR_SALT_5
- 4'b 1111, // index[32] KEYMGR_SALT_6
- 4'b 1111, // index[33] KEYMGR_SALT_7
- 4'b 1111, // index[34] KEYMGR_KEY_VERSION
- 4'b 0001, // index[35] KEYMGR_MAX_CREATOR_KEY_VER_REGWEN
- 4'b 1111, // index[36] KEYMGR_MAX_CREATOR_KEY_VER_SHADOWED
- 4'b 0001, // index[37] KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN
- 4'b 1111, // index[38] KEYMGR_MAX_OWNER_INT_KEY_VER_SHADOWED
- 4'b 0001, // index[39] KEYMGR_MAX_OWNER_KEY_VER_REGWEN
- 4'b 1111, // index[40] KEYMGR_MAX_OWNER_KEY_VER_SHADOWED
- 4'b 1111, // index[41] KEYMGR_SW_SHARE0_OUTPUT_0
- 4'b 1111, // index[42] KEYMGR_SW_SHARE0_OUTPUT_1
- 4'b 1111, // index[43] KEYMGR_SW_SHARE0_OUTPUT_2
- 4'b 1111, // index[44] KEYMGR_SW_SHARE0_OUTPUT_3
- 4'b 1111, // index[45] KEYMGR_SW_SHARE0_OUTPUT_4
- 4'b 1111, // index[46] KEYMGR_SW_SHARE0_OUTPUT_5
- 4'b 1111, // index[47] KEYMGR_SW_SHARE0_OUTPUT_6
- 4'b 1111, // index[48] KEYMGR_SW_SHARE0_OUTPUT_7
- 4'b 1111, // index[49] KEYMGR_SW_SHARE1_OUTPUT_0
- 4'b 1111, // index[50] KEYMGR_SW_SHARE1_OUTPUT_1
- 4'b 1111, // index[51] KEYMGR_SW_SHARE1_OUTPUT_2
- 4'b 1111, // index[52] KEYMGR_SW_SHARE1_OUTPUT_3
- 4'b 1111, // index[53] KEYMGR_SW_SHARE1_OUTPUT_4
- 4'b 1111, // index[54] KEYMGR_SW_SHARE1_OUTPUT_5
- 4'b 1111, // index[55] KEYMGR_SW_SHARE1_OUTPUT_6
- 4'b 1111, // index[56] KEYMGR_SW_SHARE1_OUTPUT_7
- 4'b 0001, // index[57] KEYMGR_WORKING_STATE
- 4'b 0001, // index[58] KEYMGR_OP_STATUS
- 4'b 0001, // index[59] KEYMGR_ERR_CODE
- 4'b 0011 // index[60] KEYMGR_FAULT_STATUS
+ 4'b 0001, // index[ 5] KEYMGR_START
+ 4'b 0011, // index[ 6] KEYMGR_CONTROL_SHADOWED
+ 4'b 0001, // index[ 7] KEYMGR_SIDELOAD_CLEAR
+ 4'b 0001, // index[ 8] KEYMGR_RESEED_INTERVAL_REGWEN
+ 4'b 0011, // index[ 9] KEYMGR_RESEED_INTERVAL_SHADOWED
+ 4'b 0001, // index[10] KEYMGR_SW_BINDING_REGWEN
+ 4'b 1111, // index[11] KEYMGR_SEALING_SW_BINDING_0
+ 4'b 1111, // index[12] KEYMGR_SEALING_SW_BINDING_1
+ 4'b 1111, // index[13] KEYMGR_SEALING_SW_BINDING_2
+ 4'b 1111, // index[14] KEYMGR_SEALING_SW_BINDING_3
+ 4'b 1111, // index[15] KEYMGR_SEALING_SW_BINDING_4
+ 4'b 1111, // index[16] KEYMGR_SEALING_SW_BINDING_5
+ 4'b 1111, // index[17] KEYMGR_SEALING_SW_BINDING_6
+ 4'b 1111, // index[18] KEYMGR_SEALING_SW_BINDING_7
+ 4'b 1111, // index[19] KEYMGR_ATTEST_SW_BINDING_0
+ 4'b 1111, // index[20] KEYMGR_ATTEST_SW_BINDING_1
+ 4'b 1111, // index[21] KEYMGR_ATTEST_SW_BINDING_2
+ 4'b 1111, // index[22] KEYMGR_ATTEST_SW_BINDING_3
+ 4'b 1111, // index[23] KEYMGR_ATTEST_SW_BINDING_4
+ 4'b 1111, // index[24] KEYMGR_ATTEST_SW_BINDING_5
+ 4'b 1111, // index[25] KEYMGR_ATTEST_SW_BINDING_6
+ 4'b 1111, // index[26] KEYMGR_ATTEST_SW_BINDING_7
+ 4'b 1111, // index[27] KEYMGR_SALT_0
+ 4'b 1111, // index[28] KEYMGR_SALT_1
+ 4'b 1111, // index[29] KEYMGR_SALT_2
+ 4'b 1111, // index[30] KEYMGR_SALT_3
+ 4'b 1111, // index[31] KEYMGR_SALT_4
+ 4'b 1111, // index[32] KEYMGR_SALT_5
+ 4'b 1111, // index[33] KEYMGR_SALT_6
+ 4'b 1111, // index[34] KEYMGR_SALT_7
+ 4'b 1111, // index[35] KEYMGR_KEY_VERSION
+ 4'b 0001, // index[36] KEYMGR_MAX_CREATOR_KEY_VER_REGWEN
+ 4'b 1111, // index[37] KEYMGR_MAX_CREATOR_KEY_VER_SHADOWED
+ 4'b 0001, // index[38] KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN
+ 4'b 1111, // index[39] KEYMGR_MAX_OWNER_INT_KEY_VER_SHADOWED
+ 4'b 0001, // index[40] KEYMGR_MAX_OWNER_KEY_VER_REGWEN
+ 4'b 1111, // index[41] KEYMGR_MAX_OWNER_KEY_VER_SHADOWED
+ 4'b 1111, // index[42] KEYMGR_SW_SHARE0_OUTPUT_0
+ 4'b 1111, // index[43] KEYMGR_SW_SHARE0_OUTPUT_1
+ 4'b 1111, // index[44] KEYMGR_SW_SHARE0_OUTPUT_2
+ 4'b 1111, // index[45] KEYMGR_SW_SHARE0_OUTPUT_3
+ 4'b 1111, // index[46] KEYMGR_SW_SHARE0_OUTPUT_4
+ 4'b 1111, // index[47] KEYMGR_SW_SHARE0_OUTPUT_5
+ 4'b 1111, // index[48] KEYMGR_SW_SHARE0_OUTPUT_6
+ 4'b 1111, // index[49] KEYMGR_SW_SHARE0_OUTPUT_7
+ 4'b 1111, // index[50] KEYMGR_SW_SHARE1_OUTPUT_0
+ 4'b 1111, // index[51] KEYMGR_SW_SHARE1_OUTPUT_1
+ 4'b 1111, // index[52] KEYMGR_SW_SHARE1_OUTPUT_2
+ 4'b 1111, // index[53] KEYMGR_SW_SHARE1_OUTPUT_3
+ 4'b 1111, // index[54] KEYMGR_SW_SHARE1_OUTPUT_4
+ 4'b 1111, // index[55] KEYMGR_SW_SHARE1_OUTPUT_5
+ 4'b 1111, // index[56] KEYMGR_SW_SHARE1_OUTPUT_6
+ 4'b 1111, // index[57] KEYMGR_SW_SHARE1_OUTPUT_7
+ 4'b 0001, // index[58] KEYMGR_WORKING_STATE
+ 4'b 0001, // index[59] KEYMGR_OP_STATUS
+ 4'b 0001, // index[60] KEYMGR_ERR_CODE
+ 4'b 0011 // index[61] KEYMGR_FAULT_STATUS
};
endpackage
diff --git a/hw/ip/keymgr/rtl/keymgr_reg_top.sv b/hw/ip/keymgr/rtl/keymgr_reg_top.sv
index cb498e1..2939eea 100644
--- a/hw/ip/keymgr/rtl/keymgr_reg_top.sv
+++ b/hw/ip/keymgr/rtl/keymgr_reg_top.sv
@@ -122,15 +122,17 @@
logic alert_test_recov_operation_err_wd;
logic cfg_regwen_re;
logic cfg_regwen_qs;
- logic control_we;
- logic control_start_qs;
- logic control_start_wd;
- logic [2:0] control_operation_qs;
- logic [2:0] control_operation_wd;
- logic control_cdi_sel_qs;
- logic control_cdi_sel_wd;
- logic [2:0] control_dest_sel_qs;
- logic [2:0] control_dest_sel_wd;
+ logic start_we;
+ logic start_qs;
+ logic start_wd;
+ logic control_shadowed_re;
+ logic control_shadowed_we;
+ logic [2:0] control_shadowed_operation_qs;
+ logic [2:0] control_shadowed_operation_wd;
+ logic control_shadowed_cdi_sel_qs;
+ logic control_shadowed_cdi_sel_wd;
+ logic [2:0] control_shadowed_dest_sel_qs;
+ logic [2:0] control_shadowed_dest_sel_wd;
logic sideload_clear_we;
logic [2:0] sideload_clear_qs;
logic [2:0] sideload_clear_wd;
@@ -424,44 +426,47 @@
);
- // R[control]: V(False)
- // F[start]: 0:0
+ // R[start]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_control_start (
+ ) u_start (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (control_we & cfg_regwen_qs),
- .wd (control_start_wd),
+ .we (start_we & cfg_regwen_qs),
+ .wd (start_wd),
// from internal hardware
- .de (hw2reg.control.start.de),
- .d (hw2reg.control.start.d),
+ .de (hw2reg.start.de),
+ .d (hw2reg.start.d),
// to internal hardware
.qe (),
- .q (reg2hw.control.start.q),
+ .q (reg2hw.start.q),
// to register interface (read)
- .qs (control_start_qs)
+ .qs (start_qs)
);
+
+ // R[control_shadowed]: V(False)
// F[operation]: 6:4
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (3),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (3'h1)
- ) u_control_operation (
+ ) u_control_shadowed_operation (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (control_we & cfg_regwen_qs),
- .wd (control_operation_wd),
+ .re (control_shadowed_re),
+ .we (control_shadowed_we & cfg_regwen_qs),
+ .wd (control_shadowed_operation_wd),
// from internal hardware
.de (1'b0),
@@ -469,24 +474,30 @@
// to internal hardware
.qe (),
- .q (reg2hw.control.operation.q),
+ .q (reg2hw.control_shadowed.operation.q),
// to register interface (read)
- .qs (control_operation_qs)
+ .qs (control_shadowed_operation_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.control_shadowed.operation.err_update),
+ .err_storage (reg2hw.control_shadowed.operation.err_storage)
);
// F[cdi_sel]: 7:7
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_control_cdi_sel (
+ ) u_control_shadowed_cdi_sel (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (control_we & cfg_regwen_qs),
- .wd (control_cdi_sel_wd),
+ .re (control_shadowed_re),
+ .we (control_shadowed_we & cfg_regwen_qs),
+ .wd (control_shadowed_cdi_sel_wd),
// from internal hardware
.de (1'b0),
@@ -494,24 +505,30 @@
// to internal hardware
.qe (),
- .q (reg2hw.control.cdi_sel.q),
+ .q (reg2hw.control_shadowed.cdi_sel.q),
// to register interface (read)
- .qs (control_cdi_sel_qs)
+ .qs (control_shadowed_cdi_sel_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.control_shadowed.cdi_sel.err_update),
+ .err_storage (reg2hw.control_shadowed.cdi_sel.err_storage)
);
// F[dest_sel]: 14:12
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (3),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (3'h0)
- ) u_control_dest_sel (
+ ) u_control_shadowed_dest_sel (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (control_we & cfg_regwen_qs),
- .wd (control_dest_sel_wd),
+ .re (control_shadowed_re),
+ .we (control_shadowed_we & cfg_regwen_qs),
+ .wd (control_shadowed_dest_sel_wd),
// from internal hardware
.de (1'b0),
@@ -519,10 +536,14 @@
// to internal hardware
.qe (),
- .q (reg2hw.control.dest_sel.q),
+ .q (reg2hw.control_shadowed.dest_sel.q),
// to register interface (read)
- .qs (control_dest_sel_qs)
+ .qs (control_shadowed_dest_sel_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.control_shadowed.dest_sel.err_update),
+ .err_storage (reg2hw.control_shadowed.dest_sel.err_storage)
);
@@ -2288,7 +2309,7 @@
- logic [60:0] addr_hit;
+ logic [61:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == KEYMGR_INTR_STATE_OFFSET);
@@ -2296,62 +2317,63 @@
addr_hit[ 2] = (reg_addr == KEYMGR_INTR_TEST_OFFSET);
addr_hit[ 3] = (reg_addr == KEYMGR_ALERT_TEST_OFFSET);
addr_hit[ 4] = (reg_addr == KEYMGR_CFG_REGWEN_OFFSET);
- addr_hit[ 5] = (reg_addr == KEYMGR_CONTROL_OFFSET);
- addr_hit[ 6] = (reg_addr == KEYMGR_SIDELOAD_CLEAR_OFFSET);
- addr_hit[ 7] = (reg_addr == KEYMGR_RESEED_INTERVAL_REGWEN_OFFSET);
- addr_hit[ 8] = (reg_addr == KEYMGR_RESEED_INTERVAL_SHADOWED_OFFSET);
- addr_hit[ 9] = (reg_addr == KEYMGR_SW_BINDING_REGWEN_OFFSET);
- addr_hit[10] = (reg_addr == KEYMGR_SEALING_SW_BINDING_0_OFFSET);
- addr_hit[11] = (reg_addr == KEYMGR_SEALING_SW_BINDING_1_OFFSET);
- addr_hit[12] = (reg_addr == KEYMGR_SEALING_SW_BINDING_2_OFFSET);
- addr_hit[13] = (reg_addr == KEYMGR_SEALING_SW_BINDING_3_OFFSET);
- addr_hit[14] = (reg_addr == KEYMGR_SEALING_SW_BINDING_4_OFFSET);
- addr_hit[15] = (reg_addr == KEYMGR_SEALING_SW_BINDING_5_OFFSET);
- addr_hit[16] = (reg_addr == KEYMGR_SEALING_SW_BINDING_6_OFFSET);
- addr_hit[17] = (reg_addr == KEYMGR_SEALING_SW_BINDING_7_OFFSET);
- addr_hit[18] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_0_OFFSET);
- addr_hit[19] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_1_OFFSET);
- addr_hit[20] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_2_OFFSET);
- addr_hit[21] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_3_OFFSET);
- addr_hit[22] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_4_OFFSET);
- addr_hit[23] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_5_OFFSET);
- addr_hit[24] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_6_OFFSET);
- addr_hit[25] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_7_OFFSET);
- addr_hit[26] = (reg_addr == KEYMGR_SALT_0_OFFSET);
- addr_hit[27] = (reg_addr == KEYMGR_SALT_1_OFFSET);
- addr_hit[28] = (reg_addr == KEYMGR_SALT_2_OFFSET);
- addr_hit[29] = (reg_addr == KEYMGR_SALT_3_OFFSET);
- addr_hit[30] = (reg_addr == KEYMGR_SALT_4_OFFSET);
- addr_hit[31] = (reg_addr == KEYMGR_SALT_5_OFFSET);
- addr_hit[32] = (reg_addr == KEYMGR_SALT_6_OFFSET);
- addr_hit[33] = (reg_addr == KEYMGR_SALT_7_OFFSET);
- addr_hit[34] = (reg_addr == KEYMGR_KEY_VERSION_OFFSET);
- addr_hit[35] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET);
- addr_hit[36] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_SHADOWED_OFFSET);
- addr_hit[37] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET);
- addr_hit[38] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_SHADOWED_OFFSET);
- addr_hit[39] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET);
- addr_hit[40] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_SHADOWED_OFFSET);
- addr_hit[41] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET);
- addr_hit[42] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET);
- addr_hit[43] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET);
- addr_hit[44] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET);
- addr_hit[45] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET);
- addr_hit[46] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET);
- addr_hit[47] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET);
- addr_hit[48] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET);
- addr_hit[49] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET);
- addr_hit[50] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET);
- addr_hit[51] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET);
- addr_hit[52] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET);
- addr_hit[53] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET);
- addr_hit[54] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET);
- addr_hit[55] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET);
- addr_hit[56] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET);
- addr_hit[57] = (reg_addr == KEYMGR_WORKING_STATE_OFFSET);
- addr_hit[58] = (reg_addr == KEYMGR_OP_STATUS_OFFSET);
- addr_hit[59] = (reg_addr == KEYMGR_ERR_CODE_OFFSET);
- addr_hit[60] = (reg_addr == KEYMGR_FAULT_STATUS_OFFSET);
+ addr_hit[ 5] = (reg_addr == KEYMGR_START_OFFSET);
+ addr_hit[ 6] = (reg_addr == KEYMGR_CONTROL_SHADOWED_OFFSET);
+ addr_hit[ 7] = (reg_addr == KEYMGR_SIDELOAD_CLEAR_OFFSET);
+ addr_hit[ 8] = (reg_addr == KEYMGR_RESEED_INTERVAL_REGWEN_OFFSET);
+ addr_hit[ 9] = (reg_addr == KEYMGR_RESEED_INTERVAL_SHADOWED_OFFSET);
+ addr_hit[10] = (reg_addr == KEYMGR_SW_BINDING_REGWEN_OFFSET);
+ addr_hit[11] = (reg_addr == KEYMGR_SEALING_SW_BINDING_0_OFFSET);
+ addr_hit[12] = (reg_addr == KEYMGR_SEALING_SW_BINDING_1_OFFSET);
+ addr_hit[13] = (reg_addr == KEYMGR_SEALING_SW_BINDING_2_OFFSET);
+ addr_hit[14] = (reg_addr == KEYMGR_SEALING_SW_BINDING_3_OFFSET);
+ addr_hit[15] = (reg_addr == KEYMGR_SEALING_SW_BINDING_4_OFFSET);
+ addr_hit[16] = (reg_addr == KEYMGR_SEALING_SW_BINDING_5_OFFSET);
+ addr_hit[17] = (reg_addr == KEYMGR_SEALING_SW_BINDING_6_OFFSET);
+ addr_hit[18] = (reg_addr == KEYMGR_SEALING_SW_BINDING_7_OFFSET);
+ addr_hit[19] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_0_OFFSET);
+ addr_hit[20] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_1_OFFSET);
+ addr_hit[21] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_2_OFFSET);
+ addr_hit[22] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_3_OFFSET);
+ addr_hit[23] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_4_OFFSET);
+ addr_hit[24] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_5_OFFSET);
+ addr_hit[25] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_6_OFFSET);
+ addr_hit[26] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_7_OFFSET);
+ addr_hit[27] = (reg_addr == KEYMGR_SALT_0_OFFSET);
+ addr_hit[28] = (reg_addr == KEYMGR_SALT_1_OFFSET);
+ addr_hit[29] = (reg_addr == KEYMGR_SALT_2_OFFSET);
+ addr_hit[30] = (reg_addr == KEYMGR_SALT_3_OFFSET);
+ addr_hit[31] = (reg_addr == KEYMGR_SALT_4_OFFSET);
+ addr_hit[32] = (reg_addr == KEYMGR_SALT_5_OFFSET);
+ addr_hit[33] = (reg_addr == KEYMGR_SALT_6_OFFSET);
+ addr_hit[34] = (reg_addr == KEYMGR_SALT_7_OFFSET);
+ addr_hit[35] = (reg_addr == KEYMGR_KEY_VERSION_OFFSET);
+ addr_hit[36] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET);
+ addr_hit[37] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_SHADOWED_OFFSET);
+ addr_hit[38] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET);
+ addr_hit[39] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_SHADOWED_OFFSET);
+ addr_hit[40] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET);
+ addr_hit[41] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_SHADOWED_OFFSET);
+ addr_hit[42] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET);
+ addr_hit[43] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET);
+ addr_hit[44] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET);
+ addr_hit[45] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET);
+ addr_hit[46] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET);
+ addr_hit[47] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET);
+ addr_hit[48] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET);
+ addr_hit[49] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET);
+ addr_hit[50] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET);
+ addr_hit[51] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET);
+ addr_hit[52] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET);
+ addr_hit[53] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET);
+ addr_hit[54] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET);
+ addr_hit[55] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET);
+ addr_hit[56] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET);
+ addr_hit[57] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET);
+ addr_hit[58] = (reg_addr == KEYMGR_WORKING_STATE_OFFSET);
+ addr_hit[59] = (reg_addr == KEYMGR_OP_STATUS_OFFSET);
+ addr_hit[60] = (reg_addr == KEYMGR_ERR_CODE_OFFSET);
+ addr_hit[61] = (reg_addr == KEYMGR_FAULT_STATUS_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -2419,7 +2441,8 @@
(addr_hit[57] & (|(KEYMGR_PERMIT[57] & ~reg_be))) |
(addr_hit[58] & (|(KEYMGR_PERMIT[58] & ~reg_be))) |
(addr_hit[59] & (|(KEYMGR_PERMIT[59] & ~reg_be))) |
- (addr_hit[60] & (|(KEYMGR_PERMIT[60] & ~reg_be)))));
+ (addr_hit[60] & (|(KEYMGR_PERMIT[60] & ~reg_be))) |
+ (addr_hit[61] & (|(KEYMGR_PERMIT[61] & ~reg_be)))));
end
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
@@ -2436,177 +2459,179 @@
assign alert_test_recov_operation_err_wd = reg_wdata[1];
assign cfg_regwen_re = addr_hit[4] & reg_re & !reg_error;
- assign control_we = addr_hit[5] & reg_we & !reg_error;
+ assign start_we = addr_hit[5] & reg_we & !reg_error;
- assign control_start_wd = reg_wdata[0];
+ assign start_wd = reg_wdata[0];
+ assign control_shadowed_re = addr_hit[6] & reg_re & !reg_error;
+ assign control_shadowed_we = addr_hit[6] & reg_we & !reg_error;
- assign control_operation_wd = reg_wdata[6:4];
+ assign control_shadowed_operation_wd = reg_wdata[6:4];
- assign control_cdi_sel_wd = reg_wdata[7];
+ assign control_shadowed_cdi_sel_wd = reg_wdata[7];
- assign control_dest_sel_wd = reg_wdata[14:12];
- assign sideload_clear_we = addr_hit[6] & reg_we & !reg_error;
+ assign control_shadowed_dest_sel_wd = reg_wdata[14:12];
+ assign sideload_clear_we = addr_hit[7] & reg_we & !reg_error;
assign sideload_clear_wd = reg_wdata[2:0];
- assign reseed_interval_regwen_we = addr_hit[7] & reg_we & !reg_error;
+ assign reseed_interval_regwen_we = addr_hit[8] & reg_we & !reg_error;
assign reseed_interval_regwen_wd = reg_wdata[0];
- assign reseed_interval_shadowed_re = addr_hit[8] & reg_re & !reg_error;
- assign reseed_interval_shadowed_we = addr_hit[8] & reg_we & !reg_error;
+ assign reseed_interval_shadowed_re = addr_hit[9] & reg_re & !reg_error;
+ assign reseed_interval_shadowed_we = addr_hit[9] & reg_we & !reg_error;
assign reseed_interval_shadowed_wd = reg_wdata[15:0];
- assign sw_binding_regwen_re = addr_hit[9] & reg_re & !reg_error;
- assign sw_binding_regwen_we = addr_hit[9] & reg_we & !reg_error;
+ assign sw_binding_regwen_re = addr_hit[10] & reg_re & !reg_error;
+ assign sw_binding_regwen_we = addr_hit[10] & reg_we & !reg_error;
assign sw_binding_regwen_wd = reg_wdata[0];
- assign sealing_sw_binding_0_we = addr_hit[10] & reg_we & !reg_error;
+ assign sealing_sw_binding_0_we = addr_hit[11] & reg_we & !reg_error;
assign sealing_sw_binding_0_wd = reg_wdata[31:0];
- assign sealing_sw_binding_1_we = addr_hit[11] & reg_we & !reg_error;
+ assign sealing_sw_binding_1_we = addr_hit[12] & reg_we & !reg_error;
assign sealing_sw_binding_1_wd = reg_wdata[31:0];
- assign sealing_sw_binding_2_we = addr_hit[12] & reg_we & !reg_error;
+ assign sealing_sw_binding_2_we = addr_hit[13] & reg_we & !reg_error;
assign sealing_sw_binding_2_wd = reg_wdata[31:0];
- assign sealing_sw_binding_3_we = addr_hit[13] & reg_we & !reg_error;
+ assign sealing_sw_binding_3_we = addr_hit[14] & reg_we & !reg_error;
assign sealing_sw_binding_3_wd = reg_wdata[31:0];
- assign sealing_sw_binding_4_we = addr_hit[14] & reg_we & !reg_error;
+ assign sealing_sw_binding_4_we = addr_hit[15] & reg_we & !reg_error;
assign sealing_sw_binding_4_wd = reg_wdata[31:0];
- assign sealing_sw_binding_5_we = addr_hit[15] & reg_we & !reg_error;
+ assign sealing_sw_binding_5_we = addr_hit[16] & reg_we & !reg_error;
assign sealing_sw_binding_5_wd = reg_wdata[31:0];
- assign sealing_sw_binding_6_we = addr_hit[16] & reg_we & !reg_error;
+ assign sealing_sw_binding_6_we = addr_hit[17] & reg_we & !reg_error;
assign sealing_sw_binding_6_wd = reg_wdata[31:0];
- assign sealing_sw_binding_7_we = addr_hit[17] & reg_we & !reg_error;
+ assign sealing_sw_binding_7_we = addr_hit[18] & reg_we & !reg_error;
assign sealing_sw_binding_7_wd = reg_wdata[31:0];
- assign attest_sw_binding_0_we = addr_hit[18] & reg_we & !reg_error;
+ assign attest_sw_binding_0_we = addr_hit[19] & reg_we & !reg_error;
assign attest_sw_binding_0_wd = reg_wdata[31:0];
- assign attest_sw_binding_1_we = addr_hit[19] & reg_we & !reg_error;
+ assign attest_sw_binding_1_we = addr_hit[20] & reg_we & !reg_error;
assign attest_sw_binding_1_wd = reg_wdata[31:0];
- assign attest_sw_binding_2_we = addr_hit[20] & reg_we & !reg_error;
+ assign attest_sw_binding_2_we = addr_hit[21] & reg_we & !reg_error;
assign attest_sw_binding_2_wd = reg_wdata[31:0];
- assign attest_sw_binding_3_we = addr_hit[21] & reg_we & !reg_error;
+ assign attest_sw_binding_3_we = addr_hit[22] & reg_we & !reg_error;
assign attest_sw_binding_3_wd = reg_wdata[31:0];
- assign attest_sw_binding_4_we = addr_hit[22] & reg_we & !reg_error;
+ assign attest_sw_binding_4_we = addr_hit[23] & reg_we & !reg_error;
assign attest_sw_binding_4_wd = reg_wdata[31:0];
- assign attest_sw_binding_5_we = addr_hit[23] & reg_we & !reg_error;
+ assign attest_sw_binding_5_we = addr_hit[24] & reg_we & !reg_error;
assign attest_sw_binding_5_wd = reg_wdata[31:0];
- assign attest_sw_binding_6_we = addr_hit[24] & reg_we & !reg_error;
+ assign attest_sw_binding_6_we = addr_hit[25] & reg_we & !reg_error;
assign attest_sw_binding_6_wd = reg_wdata[31:0];
- assign attest_sw_binding_7_we = addr_hit[25] & reg_we & !reg_error;
+ assign attest_sw_binding_7_we = addr_hit[26] & reg_we & !reg_error;
assign attest_sw_binding_7_wd = reg_wdata[31:0];
- assign salt_0_we = addr_hit[26] & reg_we & !reg_error;
+ assign salt_0_we = addr_hit[27] & reg_we & !reg_error;
assign salt_0_wd = reg_wdata[31:0];
- assign salt_1_we = addr_hit[27] & reg_we & !reg_error;
+ assign salt_1_we = addr_hit[28] & reg_we & !reg_error;
assign salt_1_wd = reg_wdata[31:0];
- assign salt_2_we = addr_hit[28] & reg_we & !reg_error;
+ assign salt_2_we = addr_hit[29] & reg_we & !reg_error;
assign salt_2_wd = reg_wdata[31:0];
- assign salt_3_we = addr_hit[29] & reg_we & !reg_error;
+ assign salt_3_we = addr_hit[30] & reg_we & !reg_error;
assign salt_3_wd = reg_wdata[31:0];
- assign salt_4_we = addr_hit[30] & reg_we & !reg_error;
+ assign salt_4_we = addr_hit[31] & reg_we & !reg_error;
assign salt_4_wd = reg_wdata[31:0];
- assign salt_5_we = addr_hit[31] & reg_we & !reg_error;
+ assign salt_5_we = addr_hit[32] & reg_we & !reg_error;
assign salt_5_wd = reg_wdata[31:0];
- assign salt_6_we = addr_hit[32] & reg_we & !reg_error;
+ assign salt_6_we = addr_hit[33] & reg_we & !reg_error;
assign salt_6_wd = reg_wdata[31:0];
- assign salt_7_we = addr_hit[33] & reg_we & !reg_error;
+ assign salt_7_we = addr_hit[34] & reg_we & !reg_error;
assign salt_7_wd = reg_wdata[31:0];
- assign key_version_we = addr_hit[34] & reg_we & !reg_error;
+ assign key_version_we = addr_hit[35] & reg_we & !reg_error;
assign key_version_wd = reg_wdata[31:0];
- assign max_creator_key_ver_regwen_we = addr_hit[35] & reg_we & !reg_error;
+ assign max_creator_key_ver_regwen_we = addr_hit[36] & reg_we & !reg_error;
assign max_creator_key_ver_regwen_wd = reg_wdata[0];
- assign max_creator_key_ver_shadowed_re = addr_hit[36] & reg_re & !reg_error;
- assign max_creator_key_ver_shadowed_we = addr_hit[36] & reg_we & !reg_error;
+ assign max_creator_key_ver_shadowed_re = addr_hit[37] & reg_re & !reg_error;
+ assign max_creator_key_ver_shadowed_we = addr_hit[37] & reg_we & !reg_error;
assign max_creator_key_ver_shadowed_wd = reg_wdata[31:0];
- assign max_owner_int_key_ver_regwen_we = addr_hit[37] & reg_we & !reg_error;
+ assign max_owner_int_key_ver_regwen_we = addr_hit[38] & reg_we & !reg_error;
assign max_owner_int_key_ver_regwen_wd = reg_wdata[0];
- assign max_owner_int_key_ver_shadowed_re = addr_hit[38] & reg_re & !reg_error;
- assign max_owner_int_key_ver_shadowed_we = addr_hit[38] & reg_we & !reg_error;
+ assign max_owner_int_key_ver_shadowed_re = addr_hit[39] & reg_re & !reg_error;
+ assign max_owner_int_key_ver_shadowed_we = addr_hit[39] & reg_we & !reg_error;
assign max_owner_int_key_ver_shadowed_wd = reg_wdata[31:0];
- assign max_owner_key_ver_regwen_we = addr_hit[39] & reg_we & !reg_error;
+ assign max_owner_key_ver_regwen_we = addr_hit[40] & reg_we & !reg_error;
assign max_owner_key_ver_regwen_wd = reg_wdata[0];
- assign max_owner_key_ver_shadowed_re = addr_hit[40] & reg_re & !reg_error;
- assign max_owner_key_ver_shadowed_we = addr_hit[40] & reg_we & !reg_error;
+ assign max_owner_key_ver_shadowed_re = addr_hit[41] & reg_re & !reg_error;
+ assign max_owner_key_ver_shadowed_we = addr_hit[41] & reg_we & !reg_error;
assign max_owner_key_ver_shadowed_wd = reg_wdata[31:0];
- assign sw_share0_output_0_re = addr_hit[41] & reg_re & !reg_error;
+ assign sw_share0_output_0_re = addr_hit[42] & reg_re & !reg_error;
assign sw_share0_output_0_wd = '1;
- assign sw_share0_output_1_re = addr_hit[42] & reg_re & !reg_error;
+ assign sw_share0_output_1_re = addr_hit[43] & reg_re & !reg_error;
assign sw_share0_output_1_wd = '1;
- assign sw_share0_output_2_re = addr_hit[43] & reg_re & !reg_error;
+ assign sw_share0_output_2_re = addr_hit[44] & reg_re & !reg_error;
assign sw_share0_output_2_wd = '1;
- assign sw_share0_output_3_re = addr_hit[44] & reg_re & !reg_error;
+ assign sw_share0_output_3_re = addr_hit[45] & reg_re & !reg_error;
assign sw_share0_output_3_wd = '1;
- assign sw_share0_output_4_re = addr_hit[45] & reg_re & !reg_error;
+ assign sw_share0_output_4_re = addr_hit[46] & reg_re & !reg_error;
assign sw_share0_output_4_wd = '1;
- assign sw_share0_output_5_re = addr_hit[46] & reg_re & !reg_error;
+ assign sw_share0_output_5_re = addr_hit[47] & reg_re & !reg_error;
assign sw_share0_output_5_wd = '1;
- assign sw_share0_output_6_re = addr_hit[47] & reg_re & !reg_error;
+ assign sw_share0_output_6_re = addr_hit[48] & reg_re & !reg_error;
assign sw_share0_output_6_wd = '1;
- assign sw_share0_output_7_re = addr_hit[48] & reg_re & !reg_error;
+ assign sw_share0_output_7_re = addr_hit[49] & reg_re & !reg_error;
assign sw_share0_output_7_wd = '1;
- assign sw_share1_output_0_re = addr_hit[49] & reg_re & !reg_error;
+ assign sw_share1_output_0_re = addr_hit[50] & reg_re & !reg_error;
assign sw_share1_output_0_wd = '1;
- assign sw_share1_output_1_re = addr_hit[50] & reg_re & !reg_error;
+ assign sw_share1_output_1_re = addr_hit[51] & reg_re & !reg_error;
assign sw_share1_output_1_wd = '1;
- assign sw_share1_output_2_re = addr_hit[51] & reg_re & !reg_error;
+ assign sw_share1_output_2_re = addr_hit[52] & reg_re & !reg_error;
assign sw_share1_output_2_wd = '1;
- assign sw_share1_output_3_re = addr_hit[52] & reg_re & !reg_error;
+ assign sw_share1_output_3_re = addr_hit[53] & reg_re & !reg_error;
assign sw_share1_output_3_wd = '1;
- assign sw_share1_output_4_re = addr_hit[53] & reg_re & !reg_error;
+ assign sw_share1_output_4_re = addr_hit[54] & reg_re & !reg_error;
assign sw_share1_output_4_wd = '1;
- assign sw_share1_output_5_re = addr_hit[54] & reg_re & !reg_error;
+ assign sw_share1_output_5_re = addr_hit[55] & reg_re & !reg_error;
assign sw_share1_output_5_wd = '1;
- assign sw_share1_output_6_re = addr_hit[55] & reg_re & !reg_error;
+ assign sw_share1_output_6_re = addr_hit[56] & reg_re & !reg_error;
assign sw_share1_output_6_wd = '1;
- assign sw_share1_output_7_re = addr_hit[56] & reg_re & !reg_error;
+ assign sw_share1_output_7_re = addr_hit[57] & reg_re & !reg_error;
assign sw_share1_output_7_wd = '1;
- assign op_status_we = addr_hit[58] & reg_we & !reg_error;
+ assign op_status_we = addr_hit[59] & reg_we & !reg_error;
assign op_status_wd = reg_wdata[1:0];
- assign err_code_we = addr_hit[59] & reg_we & !reg_error;
+ assign err_code_we = addr_hit[60] & reg_we & !reg_error;
assign err_code_invalid_op_wd = reg_wdata[0];
@@ -2640,231 +2665,234 @@
end
addr_hit[5]: begin
- reg_rdata_next[0] = control_start_qs;
- reg_rdata_next[6:4] = control_operation_qs;
- reg_rdata_next[7] = control_cdi_sel_qs;
- reg_rdata_next[14:12] = control_dest_sel_qs;
+ reg_rdata_next[0] = start_qs;
end
addr_hit[6]: begin
- reg_rdata_next[2:0] = sideload_clear_qs;
+ reg_rdata_next[6:4] = control_shadowed_operation_qs;
+ reg_rdata_next[7] = control_shadowed_cdi_sel_qs;
+ reg_rdata_next[14:12] = control_shadowed_dest_sel_qs;
end
addr_hit[7]: begin
- reg_rdata_next[0] = reseed_interval_regwen_qs;
+ reg_rdata_next[2:0] = sideload_clear_qs;
end
addr_hit[8]: begin
- reg_rdata_next[15:0] = reseed_interval_shadowed_qs;
+ reg_rdata_next[0] = reseed_interval_regwen_qs;
end
addr_hit[9]: begin
- reg_rdata_next[0] = sw_binding_regwen_qs;
+ reg_rdata_next[15:0] = reseed_interval_shadowed_qs;
end
addr_hit[10]: begin
- reg_rdata_next[31:0] = sealing_sw_binding_0_qs;
+ reg_rdata_next[0] = sw_binding_regwen_qs;
end
addr_hit[11]: begin
- reg_rdata_next[31:0] = sealing_sw_binding_1_qs;
+ reg_rdata_next[31:0] = sealing_sw_binding_0_qs;
end
addr_hit[12]: begin
- reg_rdata_next[31:0] = sealing_sw_binding_2_qs;
+ reg_rdata_next[31:0] = sealing_sw_binding_1_qs;
end
addr_hit[13]: begin
- reg_rdata_next[31:0] = sealing_sw_binding_3_qs;
+ reg_rdata_next[31:0] = sealing_sw_binding_2_qs;
end
addr_hit[14]: begin
- reg_rdata_next[31:0] = sealing_sw_binding_4_qs;
+ reg_rdata_next[31:0] = sealing_sw_binding_3_qs;
end
addr_hit[15]: begin
- reg_rdata_next[31:0] = sealing_sw_binding_5_qs;
+ reg_rdata_next[31:0] = sealing_sw_binding_4_qs;
end
addr_hit[16]: begin
- reg_rdata_next[31:0] = sealing_sw_binding_6_qs;
+ reg_rdata_next[31:0] = sealing_sw_binding_5_qs;
end
addr_hit[17]: begin
- reg_rdata_next[31:0] = sealing_sw_binding_7_qs;
+ reg_rdata_next[31:0] = sealing_sw_binding_6_qs;
end
addr_hit[18]: begin
- reg_rdata_next[31:0] = attest_sw_binding_0_qs;
+ reg_rdata_next[31:0] = sealing_sw_binding_7_qs;
end
addr_hit[19]: begin
- reg_rdata_next[31:0] = attest_sw_binding_1_qs;
+ reg_rdata_next[31:0] = attest_sw_binding_0_qs;
end
addr_hit[20]: begin
- reg_rdata_next[31:0] = attest_sw_binding_2_qs;
+ reg_rdata_next[31:0] = attest_sw_binding_1_qs;
end
addr_hit[21]: begin
- reg_rdata_next[31:0] = attest_sw_binding_3_qs;
+ reg_rdata_next[31:0] = attest_sw_binding_2_qs;
end
addr_hit[22]: begin
- reg_rdata_next[31:0] = attest_sw_binding_4_qs;
+ reg_rdata_next[31:0] = attest_sw_binding_3_qs;
end
addr_hit[23]: begin
- reg_rdata_next[31:0] = attest_sw_binding_5_qs;
+ reg_rdata_next[31:0] = attest_sw_binding_4_qs;
end
addr_hit[24]: begin
- reg_rdata_next[31:0] = attest_sw_binding_6_qs;
+ reg_rdata_next[31:0] = attest_sw_binding_5_qs;
end
addr_hit[25]: begin
- reg_rdata_next[31:0] = attest_sw_binding_7_qs;
+ reg_rdata_next[31:0] = attest_sw_binding_6_qs;
end
addr_hit[26]: begin
- reg_rdata_next[31:0] = salt_0_qs;
+ reg_rdata_next[31:0] = attest_sw_binding_7_qs;
end
addr_hit[27]: begin
- reg_rdata_next[31:0] = salt_1_qs;
+ reg_rdata_next[31:0] = salt_0_qs;
end
addr_hit[28]: begin
- reg_rdata_next[31:0] = salt_2_qs;
+ reg_rdata_next[31:0] = salt_1_qs;
end
addr_hit[29]: begin
- reg_rdata_next[31:0] = salt_3_qs;
+ reg_rdata_next[31:0] = salt_2_qs;
end
addr_hit[30]: begin
- reg_rdata_next[31:0] = salt_4_qs;
+ reg_rdata_next[31:0] = salt_3_qs;
end
addr_hit[31]: begin
- reg_rdata_next[31:0] = salt_5_qs;
+ reg_rdata_next[31:0] = salt_4_qs;
end
addr_hit[32]: begin
- reg_rdata_next[31:0] = salt_6_qs;
+ reg_rdata_next[31:0] = salt_5_qs;
end
addr_hit[33]: begin
- reg_rdata_next[31:0] = salt_7_qs;
+ reg_rdata_next[31:0] = salt_6_qs;
end
addr_hit[34]: begin
- reg_rdata_next[31:0] = key_version_qs;
+ reg_rdata_next[31:0] = salt_7_qs;
end
addr_hit[35]: begin
- reg_rdata_next[0] = max_creator_key_ver_regwen_qs;
+ reg_rdata_next[31:0] = key_version_qs;
end
addr_hit[36]: begin
- reg_rdata_next[31:0] = max_creator_key_ver_shadowed_qs;
+ reg_rdata_next[0] = max_creator_key_ver_regwen_qs;
end
addr_hit[37]: begin
- reg_rdata_next[0] = max_owner_int_key_ver_regwen_qs;
+ reg_rdata_next[31:0] = max_creator_key_ver_shadowed_qs;
end
addr_hit[38]: begin
- reg_rdata_next[31:0] = max_owner_int_key_ver_shadowed_qs;
+ reg_rdata_next[0] = max_owner_int_key_ver_regwen_qs;
end
addr_hit[39]: begin
- reg_rdata_next[0] = max_owner_key_ver_regwen_qs;
+ reg_rdata_next[31:0] = max_owner_int_key_ver_shadowed_qs;
end
addr_hit[40]: begin
- reg_rdata_next[31:0] = max_owner_key_ver_shadowed_qs;
+ reg_rdata_next[0] = max_owner_key_ver_regwen_qs;
end
addr_hit[41]: begin
- reg_rdata_next[31:0] = sw_share0_output_0_qs;
+ reg_rdata_next[31:0] = max_owner_key_ver_shadowed_qs;
end
addr_hit[42]: begin
- reg_rdata_next[31:0] = sw_share0_output_1_qs;
+ reg_rdata_next[31:0] = sw_share0_output_0_qs;
end
addr_hit[43]: begin
- reg_rdata_next[31:0] = sw_share0_output_2_qs;
+ reg_rdata_next[31:0] = sw_share0_output_1_qs;
end
addr_hit[44]: begin
- reg_rdata_next[31:0] = sw_share0_output_3_qs;
+ reg_rdata_next[31:0] = sw_share0_output_2_qs;
end
addr_hit[45]: begin
- reg_rdata_next[31:0] = sw_share0_output_4_qs;
+ reg_rdata_next[31:0] = sw_share0_output_3_qs;
end
addr_hit[46]: begin
- reg_rdata_next[31:0] = sw_share0_output_5_qs;
+ reg_rdata_next[31:0] = sw_share0_output_4_qs;
end
addr_hit[47]: begin
- reg_rdata_next[31:0] = sw_share0_output_6_qs;
+ reg_rdata_next[31:0] = sw_share0_output_5_qs;
end
addr_hit[48]: begin
- reg_rdata_next[31:0] = sw_share0_output_7_qs;
+ reg_rdata_next[31:0] = sw_share0_output_6_qs;
end
addr_hit[49]: begin
- reg_rdata_next[31:0] = sw_share1_output_0_qs;
+ reg_rdata_next[31:0] = sw_share0_output_7_qs;
end
addr_hit[50]: begin
- reg_rdata_next[31:0] = sw_share1_output_1_qs;
+ reg_rdata_next[31:0] = sw_share1_output_0_qs;
end
addr_hit[51]: begin
- reg_rdata_next[31:0] = sw_share1_output_2_qs;
+ reg_rdata_next[31:0] = sw_share1_output_1_qs;
end
addr_hit[52]: begin
- reg_rdata_next[31:0] = sw_share1_output_3_qs;
+ reg_rdata_next[31:0] = sw_share1_output_2_qs;
end
addr_hit[53]: begin
- reg_rdata_next[31:0] = sw_share1_output_4_qs;
+ reg_rdata_next[31:0] = sw_share1_output_3_qs;
end
addr_hit[54]: begin
- reg_rdata_next[31:0] = sw_share1_output_5_qs;
+ reg_rdata_next[31:0] = sw_share1_output_4_qs;
end
addr_hit[55]: begin
- reg_rdata_next[31:0] = sw_share1_output_6_qs;
+ reg_rdata_next[31:0] = sw_share1_output_5_qs;
end
addr_hit[56]: begin
- reg_rdata_next[31:0] = sw_share1_output_7_qs;
+ reg_rdata_next[31:0] = sw_share1_output_6_qs;
end
addr_hit[57]: begin
- reg_rdata_next[2:0] = working_state_qs;
+ reg_rdata_next[31:0] = sw_share1_output_7_qs;
end
addr_hit[58]: begin
- reg_rdata_next[1:0] = op_status_qs;
+ reg_rdata_next[2:0] = working_state_qs;
end
addr_hit[59]: begin
+ reg_rdata_next[1:0] = op_status_qs;
+ end
+
+ addr_hit[60]: begin
reg_rdata_next[0] = err_code_invalid_op_qs;
reg_rdata_next[1] = err_code_invalid_kmac_input_qs;
reg_rdata_next[2] = err_code_invalid_shadow_update_qs;
end
- addr_hit[60]: begin
+ addr_hit[61]: begin
reg_rdata_next[0] = fault_status_cmd_qs;
reg_rdata_next[1] = fault_status_kmac_fsm_qs;
reg_rdata_next[2] = fault_status_kmac_op_qs;
diff --git a/sw/device/lib/dif/dif_keymgr.c b/sw/device/lib/dif/dif_keymgr.c
index e8d0c68..0b00e6f 100644
--- a/sw/device/lib/dif/dif_keymgr.c
+++ b/sw/device/lib/dif/dif_keymgr.c
@@ -221,14 +221,14 @@
*/
static void start_operation(const dif_keymgr_t *keymgr,
start_operation_params_t params) {
- uint32_t reg_control =
- bitfield_field32_write(0, KEYMGR_CONTROL_DEST_SEL_FIELD, params.dest);
+ uint32_t reg_control = bitfield_field32_write(
+ 0, KEYMGR_CONTROL_SHADOWED_DEST_SEL_FIELD, params.dest);
reg_control = bitfield_field32_write(
- reg_control, KEYMGR_CONTROL_OPERATION_FIELD, params.op);
- reg_control =
- bitfield_bit32_write(reg_control, KEYMGR_CONTROL_START_BIT, true);
- mmio_region_write32(keymgr->base_addr, KEYMGR_CONTROL_REG_OFFSET,
- reg_control);
+ reg_control, KEYMGR_CONTROL_SHADOWED_OPERATION_FIELD, params.op);
+ mmio_region_write32_shadowed(keymgr->base_addr,
+ KEYMGR_CONTROL_SHADOWED_REG_OFFSET, reg_control);
+ mmio_region_write32(keymgr->base_addr, KEYMGR_START_REG_OFFSET,
+ 1 << KEYMGR_START_EN_BIT);
}
dif_result_t dif_keymgr_configure(const dif_keymgr_t *keymgr,
@@ -310,10 +310,11 @@
}
// Advance state.
- start_operation(keymgr, (start_operation_params_t){
- .dest = KEYMGR_CONTROL_DEST_SEL_VALUE_NONE,
- .op = KEYMGR_CONTROL_OPERATION_VALUE_ADVANCE,
- });
+ start_operation(keymgr,
+ (start_operation_params_t){
+ .dest = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE,
+ .op = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_ADVANCE,
+ });
return kDifOk;
}
@@ -328,10 +329,11 @@
}
// Disable key manager.
- start_operation(keymgr, (start_operation_params_t){
- .dest = KEYMGR_CONTROL_DEST_SEL_VALUE_NONE,
- .op = KEYMGR_CONTROL_OPERATION_VALUE_DISABLE,
- });
+ start_operation(keymgr,
+ (start_operation_params_t){
+ .dest = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE,
+ .op = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_DISABLE,
+ });
return kDifOk;
}
@@ -438,10 +440,11 @@
return kDifLocked;
}
- start_operation(keymgr, (start_operation_params_t){
- .dest = KEYMGR_CONTROL_DEST_SEL_VALUE_NONE,
- .op = KEYMGR_CONTROL_OPERATION_VALUE_GENERATE_ID,
- });
+ start_operation(keymgr,
+ (start_operation_params_t){
+ .dest = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE,
+ .op = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_ID,
+ });
return kDifOk;
}
@@ -456,20 +459,20 @@
switch (params.dest) {
case kDifKeymgrVersionedKeyDestSw:
hw_op_params = (start_operation_params_t){
- .dest = KEYMGR_CONTROL_DEST_SEL_VALUE_NONE,
- .op = KEYMGR_CONTROL_OPERATION_VALUE_GENERATE_SW_OUTPUT,
+ .dest = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE,
+ .op = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_SW_OUTPUT,
};
break;
case kDifKeymgrVersionedKeyDestAes:
hw_op_params = (start_operation_params_t){
- .dest = KEYMGR_CONTROL_DEST_SEL_VALUE_AES,
- .op = KEYMGR_CONTROL_OPERATION_VALUE_GENERATE_HW_OUTPUT,
+ .dest = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_AES,
+ .op = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT,
};
break;
case kDifKeymgrVersionedKeyDestKmac:
hw_op_params = (start_operation_params_t){
- .dest = KEYMGR_CONTROL_DEST_SEL_VALUE_KMAC,
- .op = KEYMGR_CONTROL_OPERATION_VALUE_GENERATE_HW_OUTPUT,
+ .dest = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_KMAC,
+ .op = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT,
};
break;
default:
diff --git a/sw/device/lib/dif/dif_keymgr_unittest.cc b/sw/device/lib/dif/dif_keymgr_unittest.cc
index 134178a..0556182 100644
--- a/sw/device/lib/dif/dif_keymgr_unittest.cc
+++ b/sw/device/lib/dif/dif_keymgr_unittest.cc
@@ -209,19 +209,21 @@
* Expectations for starting an operation.
*/
void ExpectOperationStart(const OperationStartParams ¶ms) {
- EXPECT_WRITE32(KEYMGR_CONTROL_REG_OFFSET,
- {{
- .offset = KEYMGR_CONTROL_DEST_SEL_OFFSET,
- .value = params.dest_sel,
- },
- {
- .offset = KEYMGR_CONTROL_OPERATION_OFFSET,
- .value = params.operation,
- },
- {
- .offset = KEYMGR_CONTROL_START_BIT,
- .value = 1,
- }});
+ EXPECT_WRITE32_SHADOWED(
+ KEYMGR_CONTROL_SHADOWED_REG_OFFSET,
+ {{
+ .offset = KEYMGR_CONTROL_SHADOWED_DEST_SEL_OFFSET,
+ .value = params.dest_sel,
+ },
+ {
+ .offset = KEYMGR_CONTROL_SHADOWED_OPERATION_OFFSET,
+ .value = params.operation,
+ }});
+
+ EXPECT_WRITE32(KEYMGR_START_REG_OFFSET, {{
+ .offset = KEYMGR_START_EN_BIT,
+ .value = 1,
+ }});
}
/**
@@ -372,8 +374,8 @@
EXPECT_WRITE32_SHADOWED(reg_info.offset, kStateParams.max_key_version);
EXPECT_WRITE32(reg_info.wen_offset, 0);
ExpectOperationStart({
- .dest_sel = KEYMGR_CONTROL_DEST_SEL_VALUE_NONE,
- .operation = KEYMGR_CONTROL_OPERATION_VALUE_ADVANCE,
+ .dest_sel = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE,
+ .operation = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_ADVANCE,
});
EXPECT_EQ(dif_keymgr_advance_state(&keymgr_, &kStateParams), kDifOk);
@@ -382,8 +384,8 @@
TEST_P(AdvanceToNonOperational, Success) {
ExpectIdleAtState(GetParam());
ExpectOperationStart({
- .dest_sel = KEYMGR_CONTROL_DEST_SEL_VALUE_NONE,
- .operation = KEYMGR_CONTROL_OPERATION_VALUE_ADVANCE,
+ .dest_sel = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE,
+ .operation = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_ADVANCE,
});
EXPECT_EQ(dif_keymgr_advance_state(&keymgr_, nullptr), kDifOk);
@@ -409,8 +411,8 @@
TEST_F(DisableTest, Disable) {
ExpectIdle();
ExpectOperationStart({
- .dest_sel = KEYMGR_CONTROL_DEST_SEL_VALUE_NONE,
- .operation = KEYMGR_CONTROL_OPERATION_VALUE_DISABLE,
+ .dest_sel = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE,
+ .operation = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_DISABLE,
});
EXPECT_EQ(dif_keymgr_disable(&keymgr_), kDifOk);
@@ -637,8 +639,8 @@
TEST_F(GenerateIdentityTest, Generate) {
ExpectIdle();
ExpectOperationStart({
- .dest_sel = KEYMGR_CONTROL_DEST_SEL_VALUE_NONE,
- .operation = KEYMGR_CONTROL_OPERATION_VALUE_GENERATE_ID,
+ .dest_sel = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE,
+ .operation = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_ID,
});
EXPECT_EQ(dif_keymgr_generate_identity_seed(&keymgr_), kDifOk);
@@ -712,18 +714,21 @@
testing::Values(
GenerateVersionedKeyTestCase{
.dest = kDifKeymgrVersionedKeyDestSw,
- .exp_dest_sel = KEYMGR_CONTROL_DEST_SEL_VALUE_NONE,
- .exp_operation = KEYMGR_CONTROL_OPERATION_VALUE_GENERATE_SW_OUTPUT,
+ .exp_dest_sel = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE,
+ .exp_operation =
+ KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_SW_OUTPUT,
},
GenerateVersionedKeyTestCase{
.dest = kDifKeymgrVersionedKeyDestAes,
- .exp_dest_sel = KEYMGR_CONTROL_DEST_SEL_VALUE_AES,
- .exp_operation = KEYMGR_CONTROL_OPERATION_VALUE_GENERATE_HW_OUTPUT,
+ .exp_dest_sel = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_AES,
+ .exp_operation =
+ KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT,
},
GenerateVersionedKeyTestCase{
.dest = kDifKeymgrVersionedKeyDestKmac,
- .exp_dest_sel = KEYMGR_CONTROL_DEST_SEL_VALUE_KMAC,
- .exp_operation = KEYMGR_CONTROL_OPERATION_VALUE_GENERATE_HW_OUTPUT,
+ .exp_dest_sel = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_KMAC,
+ .exp_operation =
+ KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT,
}));
class SideloadClearTest : public DifKeymgrInitialized {};
diff --git a/sw/device/silicon_creator/lib/drivers/keymgr.c b/sw/device/silicon_creator/lib/drivers/keymgr.c
index 6b6b13e..fc40f35 100644
--- a/sw/device/silicon_creator/lib/drivers/keymgr.c
+++ b/sw/device/silicon_creator/lib/drivers/keymgr.c
@@ -114,12 +114,14 @@
}
void keymgr_advance_state(void) {
- uint32_t reg = bitfield_bit32_write(0, KEYMGR_CONTROL_START_BIT, true);
- reg = bitfield_field32_write(reg, KEYMGR_CONTROL_DEST_SEL_FIELD,
- KEYMGR_CONTROL_DEST_SEL_VALUE_NONE);
- reg = bitfield_field32_write(reg, KEYMGR_CONTROL_OPERATION_FIELD,
- KEYMGR_CONTROL_OPERATION_VALUE_ADVANCE);
- abs_mmio_write32(kBase + KEYMGR_CONTROL_REG_OFFSET, reg);
+ uint32_t reg =
+ bitfield_field32_write(0, KEYMGR_CONTROL_SHADOWED_DEST_SEL_FIELD,
+ KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE);
+ reg = bitfield_field32_write(reg, KEYMGR_CONTROL_SHADOWED_OPERATION_FIELD,
+ KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_ADVANCE);
+ abs_mmio_write32_shadowed(kBase + KEYMGR_CONTROL_SHADOWED_REG_OFFSET, reg);
+
+ abs_mmio_write32(kBase + KEYMGR_START_REG_OFFSET, 1);
}
rom_error_t keymgr_state_check(keymgr_state_t expected_state) {
diff --git a/sw/device/silicon_creator/lib/drivers/keymgr_unittest.cc b/sw/device/silicon_creator/lib/drivers/keymgr_unittest.cc
index dfe19ae..b8b8668 100644
--- a/sw/device/silicon_creator/lib/drivers/keymgr_unittest.cc
+++ b/sw/device/silicon_creator/lib/drivers/keymgr_unittest.cc
@@ -122,14 +122,18 @@
}
TEST_F(KeymgrTest, AdvanceState) {
- EXPECT_ABS_WRITE32(
- base_ + KEYMGR_CONTROL_REG_OFFSET,
+ EXPECT_ABS_WRITE32_SHADOWED(
+ base_ + KEYMGR_CONTROL_SHADOWED_REG_OFFSET,
{
- {KEYMGR_CONTROL_START_BIT, true},
- {KEYMGR_CONTROL_DEST_SEL_OFFSET, KEYMGR_CONTROL_DEST_SEL_VALUE_NONE},
- {KEYMGR_CONTROL_OPERATION_OFFSET,
- KEYMGR_CONTROL_OPERATION_VALUE_ADVANCE},
+ {KEYMGR_CONTROL_SHADOWED_DEST_SEL_OFFSET,
+ KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE},
+ {KEYMGR_CONTROL_SHADOWED_OPERATION_OFFSET,
+ KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_ADVANCE},
});
+ EXPECT_ABS_WRITE32(base_ + KEYMGR_START_REG_OFFSET,
+ {
+ {KEYMGR_START_EN_BIT, true},
+ });
keymgr_advance_state();
}
diff --git a/sw/device/silicon_creator/lib/shutdown.c b/sw/device/silicon_creator/lib/shutdown.c
index fa24236..fa41ff3 100644
--- a/sw/device/silicon_creator/lib/shutdown.c
+++ b/sw/device/silicon_creator/lib/shutdown.c
@@ -277,12 +277,14 @@
enum {
kBase = TOP_EARLGREY_KEYMGR_BASE_ADDR,
};
- uint32_t reg = bitfield_bit32_write(0, KEYMGR_CONTROL_START_BIT, true);
- reg = bitfield_field32_write(reg, KEYMGR_CONTROL_DEST_SEL_FIELD,
- KEYMGR_CONTROL_DEST_SEL_VALUE_NONE);
- reg = bitfield_field32_write(reg, KEYMGR_CONTROL_OPERATION_FIELD,
- KEYMGR_CONTROL_OPERATION_VALUE_DISABLE);
- abs_mmio_write32(kBase + KEYMGR_CONTROL_REG_OFFSET, reg);
+ uint32_t reg =
+ bitfield_field32_write(0, KEYMGR_CONTROL_SHADOWED_DEST_SEL_FIELD,
+ KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE);
+ reg = bitfield_field32_write(reg, KEYMGR_CONTROL_SHADOWED_OPERATION_FIELD,
+ KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_DISABLE);
+ abs_mmio_write32_shadowed(kBase + KEYMGR_CONTROL_SHADOWED_REG_OFFSET, reg);
+
+ abs_mmio_write32(kBase + KEYMGR_START_REG_OFFSET, 1);
abs_mmio_write32(kBase + KEYMGR_SIDELOAD_CLEAR_REG_OFFSET, 1);
}
